12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ac991dceSLaurent Pinchart /* 3ac991dceSLaurent Pinchart * Copyright 2013 Ideas On Board SPRL 4ac991dceSLaurent Pinchart */ 5ac991dceSLaurent Pinchart 6ac991dceSLaurent Pinchart #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ 7ac991dceSLaurent Pinchart #define __DT_BINDINGS_CLOCK_R8A7790_H__ 8ac991dceSLaurent Pinchart 9ac991dceSLaurent Pinchart /* CPG */ 10ac991dceSLaurent Pinchart #define R8A7790_CLK_MAIN 0 11ac991dceSLaurent Pinchart #define R8A7790_CLK_PLL0 1 12ac991dceSLaurent Pinchart #define R8A7790_CLK_PLL1 2 13ac991dceSLaurent Pinchart #define R8A7790_CLK_PLL3 3 14ac991dceSLaurent Pinchart #define R8A7790_CLK_LB 4 15ac991dceSLaurent Pinchart #define R8A7790_CLK_QSPI 5 16ac991dceSLaurent Pinchart #define R8A7790_CLK_SDH 6 17ac991dceSLaurent Pinchart #define R8A7790_CLK_SD0 7 18ac991dceSLaurent Pinchart #define R8A7790_CLK_SD1 8 19ac991dceSLaurent Pinchart #define R8A7790_CLK_Z 9 2041650f40SSergei Shtylyov #define R8A7790_CLK_RCAN 10 213453ca9eSSergei Shtylyov #define R8A7790_CLK_ADSP 11 22ac991dceSLaurent Pinchart 239d90951aSLaurent Pinchart /* MSTP0 */ 249d90951aSLaurent Pinchart #define R8A7790_CLK_MSIOF0 0 259d90951aSLaurent Pinchart 26ac991dceSLaurent Pinchart /* MSTP1 */ 274ba8f246SYoshifumi Hosoya #define R8A7790_CLK_VCP1 0 284ba8f246SYoshifumi Hosoya #define R8A7790_CLK_VCP0 1 294ba8f246SYoshifumi Hosoya #define R8A7790_CLK_VPC1 2 304ba8f246SYoshifumi Hosoya #define R8A7790_CLK_VPC0 3 31da076a88SMikhail Ulyanov #define R8A7790_CLK_JPU 6 324ba8f246SYoshifumi Hosoya #define R8A7790_CLK_SSP1 9 33ac991dceSLaurent Pinchart #define R8A7790_CLK_TMU1 11 342284ff5fSKouei Abe #define R8A7790_CLK_3DG 12 354ba8f246SYoshifumi Hosoya #define R8A7790_CLK_2DDMAC 15 364ba8f246SYoshifumi Hosoya #define R8A7790_CLK_FDP1_2 17 374ba8f246SYoshifumi Hosoya #define R8A7790_CLK_FDP1_1 18 384ba8f246SYoshifumi Hosoya #define R8A7790_CLK_FDP1_0 19 39ac991dceSLaurent Pinchart #define R8A7790_CLK_TMU3 21 40ac991dceSLaurent Pinchart #define R8A7790_CLK_TMU2 22 41ac991dceSLaurent Pinchart #define R8A7790_CLK_CMT0 24 42ac991dceSLaurent Pinchart #define R8A7790_CLK_TMU0 25 43ac991dceSLaurent Pinchart #define R8A7790_CLK_VSP1_DU1 27 44ac991dceSLaurent Pinchart #define R8A7790_CLK_VSP1_DU0 28 4579ea9934SLaurent Pinchart #define R8A7790_CLK_VSP1_R 30 4679ea9934SLaurent Pinchart #define R8A7790_CLK_VSP1_S 31 47ac991dceSLaurent Pinchart 48ac991dceSLaurent Pinchart /* MSTP2 */ 49ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIFA2 2 50ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIFA1 3 51ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIFA0 4 529d90951aSLaurent Pinchart #define R8A7790_CLK_MSIOF2 5 53ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIFB0 6 54ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIFB1 7 559d90951aSLaurent Pinchart #define R8A7790_CLK_MSIOF1 8 569d90951aSLaurent Pinchart #define R8A7790_CLK_MSIOF3 15 57ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIFB2 16 58b998da05SSimon Horman #define R8A7790_CLK_SYS_DMAC1 18 59b998da05SSimon Horman #define R8A7790_CLK_SYS_DMAC0 19 60ac991dceSLaurent Pinchart 61ac991dceSLaurent Pinchart /* MSTP3 */ 6201d968e9SWolfram Sang #define R8A7790_CLK_IIC2 0 63ac991dceSLaurent Pinchart #define R8A7790_CLK_TPU0 4 64ac991dceSLaurent Pinchart #define R8A7790_CLK_MMCIF1 5 6538805823SGeert Uytterhoeven #define R8A7790_CLK_SCIF2 10 66ac991dceSLaurent Pinchart #define R8A7790_CLK_SDHI3 11 67ac991dceSLaurent Pinchart #define R8A7790_CLK_SDHI2 12 68ac991dceSLaurent Pinchart #define R8A7790_CLK_SDHI1 13 69ac991dceSLaurent Pinchart #define R8A7790_CLK_SDHI0 14 70ac991dceSLaurent Pinchart #define R8A7790_CLK_MMCIF0 15 7101d968e9SWolfram Sang #define R8A7790_CLK_IIC0 18 72ecafea8cSPhil Edworthy #define R8A7790_CLK_PCIEC 19 7301d968e9SWolfram Sang #define R8A7790_CLK_IIC1 23 74ac991dceSLaurent Pinchart #define R8A7790_CLK_SSUSB 28 75ac991dceSLaurent Pinchart #define R8A7790_CLK_CMT1 29 76ac991dceSLaurent Pinchart #define R8A7790_CLK_USBDMAC0 30 77ac991dceSLaurent Pinchart #define R8A7790_CLK_USBDMAC1 31 78ac991dceSLaurent Pinchart 7961624cafSGeert Uytterhoeven /* MSTP4 */ 8061624cafSGeert Uytterhoeven #define R8A7790_CLK_IRQC 7 819e585236SGeert Uytterhoeven #define R8A7790_CLK_INTC_SYS 8 8261624cafSGeert Uytterhoeven 83ac991dceSLaurent Pinchart /* MSTP5 */ 84ba3240beSKuninori Morimoto #define R8A7790_CLK_AUDIO_DMAC1 1 85ba3240beSKuninori Morimoto #define R8A7790_CLK_AUDIO_DMAC0 2 863453ca9eSSergei Shtylyov #define R8A7790_CLK_ADSP_MOD 6 87ac991dceSLaurent Pinchart #define R8A7790_CLK_THERMAL 22 88ac991dceSLaurent Pinchart #define R8A7790_CLK_PWM 23 89ac991dceSLaurent Pinchart 90ac991dceSLaurent Pinchart /* MSTP7 */ 91ac991dceSLaurent Pinchart #define R8A7790_CLK_EHCI 3 92ac991dceSLaurent Pinchart #define R8A7790_CLK_HSUSB 4 93ac991dceSLaurent Pinchart #define R8A7790_CLK_HSCIF1 16 94ac991dceSLaurent Pinchart #define R8A7790_CLK_HSCIF0 17 95ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIF1 20 96ac991dceSLaurent Pinchart #define R8A7790_CLK_SCIF0 21 97ac991dceSLaurent Pinchart #define R8A7790_CLK_DU2 22 98ac991dceSLaurent Pinchart #define R8A7790_CLK_DU1 23 99ac991dceSLaurent Pinchart #define R8A7790_CLK_DU0 24 100ac991dceSLaurent Pinchart #define R8A7790_CLK_LVDS1 25 101ac991dceSLaurent Pinchart #define R8A7790_CLK_LVDS0 26 102ac991dceSLaurent Pinchart 103ac991dceSLaurent Pinchart /* MSTP8 */ 104f6b5dd40SAndrey Gusakov #define R8A7790_CLK_MLB 2 105ac991dceSLaurent Pinchart #define R8A7790_CLK_VIN3 8 106ac991dceSLaurent Pinchart #define R8A7790_CLK_VIN2 9 107ac991dceSLaurent Pinchart #define R8A7790_CLK_VIN1 10 108ac991dceSLaurent Pinchart #define R8A7790_CLK_VIN0 11 10963d2d750SSergei Shtylyov #define R8A7790_CLK_ETHERAVB 12 110ac991dceSLaurent Pinchart #define R8A7790_CLK_ETHER 13 111ac991dceSLaurent Pinchart #define R8A7790_CLK_SATA1 14 112ac991dceSLaurent Pinchart #define R8A7790_CLK_SATA0 15 113ac991dceSLaurent Pinchart 114ac991dceSLaurent Pinchart /* MSTP9 */ 115ac991dceSLaurent Pinchart #define R8A7790_CLK_GPIO5 7 116ac991dceSLaurent Pinchart #define R8A7790_CLK_GPIO4 8 117ac991dceSLaurent Pinchart #define R8A7790_CLK_GPIO3 9 118ac991dceSLaurent Pinchart #define R8A7790_CLK_GPIO2 10 119ac991dceSLaurent Pinchart #define R8A7790_CLK_GPIO1 11 120ac991dceSLaurent Pinchart #define R8A7790_CLK_GPIO0 12 121ac991dceSLaurent Pinchart #define R8A7790_CLK_RCAN1 15 122ac991dceSLaurent Pinchart #define R8A7790_CLK_RCAN0 16 12391b56ca1SLaurent Pinchart #define R8A7790_CLK_QSPI_MOD 17 124ac991dceSLaurent Pinchart #define R8A7790_CLK_IICDVFS 26 125ac991dceSLaurent Pinchart #define R8A7790_CLK_I2C3 28 126ac991dceSLaurent Pinchart #define R8A7790_CLK_I2C2 29 127ac991dceSLaurent Pinchart #define R8A7790_CLK_I2C1 30 128ac991dceSLaurent Pinchart #define R8A7790_CLK_I2C0 31 129ac991dceSLaurent Pinchart 130bcde3722SKuninori Morimoto /* MSTP10 */ 131bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI_ALL 5 132bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI9 6 133bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI8 7 134bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI7 8 135bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI6 9 136bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI5 10 137bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI4 11 138bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI3 12 139bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI2 13 140bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI1 14 141bcde3722SKuninori Morimoto #define R8A7790_CLK_SSI0 15 142bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_ALL 17 143bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_DVC1 18 144bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_DVC0 19 145a7163784SKuninori Morimoto #define R8A7790_CLK_SCU_CTU1_MIX1 20 146a7163784SKuninori Morimoto #define R8A7790_CLK_SCU_CTU0_MIX0 21 147bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC9 22 148bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC8 23 149bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC7 24 150bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC6 25 151bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC5 26 152bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC4 27 153bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC3 28 154bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC2 29 155bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC1 30 156bcde3722SKuninori Morimoto #define R8A7790_CLK_SCU_SRC0 31 157bcde3722SKuninori Morimoto 158ac991dceSLaurent Pinchart #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ 159