101404648SChun-Jie Chen /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 201404648SChun-Jie Chen /* 301404648SChun-Jie Chen * Copyright (c) 2021 MediaTek Inc. 401404648SChun-Jie Chen * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 501404648SChun-Jie Chen */ 601404648SChun-Jie Chen 701404648SChun-Jie Chen #ifndef _DT_BINDINGS_CLK_MT8195_H 801404648SChun-Jie Chen #define _DT_BINDINGS_CLK_MT8195_H 901404648SChun-Jie Chen 1001404648SChun-Jie Chen /* TOPCKGEN */ 1101404648SChun-Jie Chen 1201404648SChun-Jie Chen #define CLK_TOP_AXI 0 1301404648SChun-Jie Chen #define CLK_TOP_SPM 1 1401404648SChun-Jie Chen #define CLK_TOP_SCP 2 1501404648SChun-Jie Chen #define CLK_TOP_BUS_AXIMEM 3 1601404648SChun-Jie Chen #define CLK_TOP_VPP 4 1701404648SChun-Jie Chen #define CLK_TOP_ETHDR 5 1801404648SChun-Jie Chen #define CLK_TOP_IPE 6 1901404648SChun-Jie Chen #define CLK_TOP_CAM 7 2001404648SChun-Jie Chen #define CLK_TOP_CCU 8 2101404648SChun-Jie Chen #define CLK_TOP_IMG 9 2201404648SChun-Jie Chen #define CLK_TOP_CAMTM 10 2301404648SChun-Jie Chen #define CLK_TOP_DSP 11 2401404648SChun-Jie Chen #define CLK_TOP_DSP1 12 2501404648SChun-Jie Chen #define CLK_TOP_DSP2 13 2601404648SChun-Jie Chen #define CLK_TOP_DSP3 14 2701404648SChun-Jie Chen #define CLK_TOP_DSP4 15 2801404648SChun-Jie Chen #define CLK_TOP_DSP5 16 2901404648SChun-Jie Chen #define CLK_TOP_DSP6 17 3001404648SChun-Jie Chen #define CLK_TOP_DSP7 18 3101404648SChun-Jie Chen #define CLK_TOP_IPU_IF 19 3201404648SChun-Jie Chen #define CLK_TOP_MFG_CORE_TMP 20 3301404648SChun-Jie Chen #define CLK_TOP_CAMTG 21 3401404648SChun-Jie Chen #define CLK_TOP_CAMTG2 22 3501404648SChun-Jie Chen #define CLK_TOP_CAMTG3 23 3601404648SChun-Jie Chen #define CLK_TOP_CAMTG4 24 3701404648SChun-Jie Chen #define CLK_TOP_CAMTG5 25 3801404648SChun-Jie Chen #define CLK_TOP_UART 26 3901404648SChun-Jie Chen #define CLK_TOP_SPI 27 4001404648SChun-Jie Chen #define CLK_TOP_SPIS 28 4101404648SChun-Jie Chen #define CLK_TOP_MSDC50_0_HCLK 29 4201404648SChun-Jie Chen #define CLK_TOP_MSDC50_0 30 4301404648SChun-Jie Chen #define CLK_TOP_MSDC30_1 31 4401404648SChun-Jie Chen #define CLK_TOP_MSDC30_2 32 4501404648SChun-Jie Chen #define CLK_TOP_INTDIR 33 4601404648SChun-Jie Chen #define CLK_TOP_AUD_INTBUS 34 4701404648SChun-Jie Chen #define CLK_TOP_AUDIO_H 35 4801404648SChun-Jie Chen #define CLK_TOP_PWRAP_ULPOSC 36 4901404648SChun-Jie Chen #define CLK_TOP_ATB 37 5001404648SChun-Jie Chen #define CLK_TOP_PWRMCU 38 5101404648SChun-Jie Chen #define CLK_TOP_DP 39 5201404648SChun-Jie Chen #define CLK_TOP_EDP 40 5301404648SChun-Jie Chen #define CLK_TOP_DPI 41 5401404648SChun-Jie Chen #define CLK_TOP_DISP_PWM0 42 5501404648SChun-Jie Chen #define CLK_TOP_DISP_PWM1 43 5601404648SChun-Jie Chen #define CLK_TOP_USB_TOP 44 5701404648SChun-Jie Chen #define CLK_TOP_SSUSB_XHCI 45 5801404648SChun-Jie Chen #define CLK_TOP_USB_TOP_1P 46 5901404648SChun-Jie Chen #define CLK_TOP_SSUSB_XHCI_1P 47 6001404648SChun-Jie Chen #define CLK_TOP_USB_TOP_2P 48 6101404648SChun-Jie Chen #define CLK_TOP_SSUSB_XHCI_2P 49 6201404648SChun-Jie Chen #define CLK_TOP_USB_TOP_3P 50 6301404648SChun-Jie Chen #define CLK_TOP_SSUSB_XHCI_3P 51 6401404648SChun-Jie Chen #define CLK_TOP_I2C 52 6501404648SChun-Jie Chen #define CLK_TOP_SENINF 53 6601404648SChun-Jie Chen #define CLK_TOP_SENINF1 54 6701404648SChun-Jie Chen #define CLK_TOP_SENINF2 55 6801404648SChun-Jie Chen #define CLK_TOP_SENINF3 56 6901404648SChun-Jie Chen #define CLK_TOP_GCPU 57 7001404648SChun-Jie Chen #define CLK_TOP_DXCC 58 7101404648SChun-Jie Chen #define CLK_TOP_DPMAIF_MAIN 59 7201404648SChun-Jie Chen #define CLK_TOP_AES_UFSFDE 60 7301404648SChun-Jie Chen #define CLK_TOP_UFS 61 7401404648SChun-Jie Chen #define CLK_TOP_UFS_TICK1US 62 7501404648SChun-Jie Chen #define CLK_TOP_UFS_MP_SAP_CFG 63 7601404648SChun-Jie Chen #define CLK_TOP_VENC 64 7701404648SChun-Jie Chen #define CLK_TOP_VDEC 65 7801404648SChun-Jie Chen #define CLK_TOP_PWM 66 7901404648SChun-Jie Chen #define CLK_TOP_MCUPM 67 8001404648SChun-Jie Chen #define CLK_TOP_SPMI_P_MST 68 8101404648SChun-Jie Chen #define CLK_TOP_SPMI_M_MST 69 8201404648SChun-Jie Chen #define CLK_TOP_DVFSRC 70 8301404648SChun-Jie Chen #define CLK_TOP_TL 71 8401404648SChun-Jie Chen #define CLK_TOP_TL_P1 72 8501404648SChun-Jie Chen #define CLK_TOP_AES_MSDCFDE 73 8601404648SChun-Jie Chen #define CLK_TOP_DSI_OCC 74 8701404648SChun-Jie Chen #define CLK_TOP_WPE_VPP 75 8801404648SChun-Jie Chen #define CLK_TOP_HDCP 76 8901404648SChun-Jie Chen #define CLK_TOP_HDCP_24M 77 9001404648SChun-Jie Chen #define CLK_TOP_HD20_DACR_REF_CLK 78 9101404648SChun-Jie Chen #define CLK_TOP_HD20_HDCP_CCLK 79 9201404648SChun-Jie Chen #define CLK_TOP_HDMI_XTAL 80 9301404648SChun-Jie Chen #define CLK_TOP_HDMI_APB 81 9401404648SChun-Jie Chen #define CLK_TOP_SNPS_ETH_250M 82 9501404648SChun-Jie Chen #define CLK_TOP_SNPS_ETH_62P4M_PTP 83 9601404648SChun-Jie Chen #define CLK_TOP_SNPS_ETH_50M_RMII 84 9701404648SChun-Jie Chen #define CLK_TOP_DGI_OUT 85 9801404648SChun-Jie Chen #define CLK_TOP_NNA0 86 9901404648SChun-Jie Chen #define CLK_TOP_NNA1 87 10001404648SChun-Jie Chen #define CLK_TOP_ADSP 88 10101404648SChun-Jie Chen #define CLK_TOP_ASM_H 89 10201404648SChun-Jie Chen #define CLK_TOP_ASM_M 90 10301404648SChun-Jie Chen #define CLK_TOP_ASM_L 91 10401404648SChun-Jie Chen #define CLK_TOP_APLL1 92 10501404648SChun-Jie Chen #define CLK_TOP_APLL2 93 10601404648SChun-Jie Chen #define CLK_TOP_APLL3 94 10701404648SChun-Jie Chen #define CLK_TOP_APLL4 95 10801404648SChun-Jie Chen #define CLK_TOP_APLL5 96 10901404648SChun-Jie Chen #define CLK_TOP_I2SO1_MCK 97 11001404648SChun-Jie Chen #define CLK_TOP_I2SO2_MCK 98 11101404648SChun-Jie Chen #define CLK_TOP_I2SI1_MCK 99 11201404648SChun-Jie Chen #define CLK_TOP_I2SI2_MCK 100 11301404648SChun-Jie Chen #define CLK_TOP_DPTX_MCK 101 11401404648SChun-Jie Chen #define CLK_TOP_AUD_IEC_CLK 102 11501404648SChun-Jie Chen #define CLK_TOP_A1SYS_HP 103 11601404648SChun-Jie Chen #define CLK_TOP_A2SYS_HF 104 11701404648SChun-Jie Chen #define CLK_TOP_A3SYS_HF 105 11801404648SChun-Jie Chen #define CLK_TOP_A4SYS_HF 106 11901404648SChun-Jie Chen #define CLK_TOP_SPINFI_BCLK 107 12001404648SChun-Jie Chen #define CLK_TOP_NFI1X 108 12101404648SChun-Jie Chen #define CLK_TOP_ECC 109 12201404648SChun-Jie Chen #define CLK_TOP_AUDIO_LOCAL_BUS 110 12301404648SChun-Jie Chen #define CLK_TOP_SPINOR 111 12401404648SChun-Jie Chen #define CLK_TOP_DVIO_DGI_REF 112 12501404648SChun-Jie Chen #define CLK_TOP_ULPOSC 113 12601404648SChun-Jie Chen #define CLK_TOP_ULPOSC_CORE 114 12701404648SChun-Jie Chen #define CLK_TOP_SRCK 115 12801404648SChun-Jie Chen #define CLK_TOP_MFG_CK_FAST_REF 116 12901404648SChun-Jie Chen #define CLK_TOP_CLK26M_D2 117 13001404648SChun-Jie Chen #define CLK_TOP_CLK26M_D52 118 13101404648SChun-Jie Chen #define CLK_TOP_IN_DGI 119 13201404648SChun-Jie Chen #define CLK_TOP_IN_DGI_D2 120 13301404648SChun-Jie Chen #define CLK_TOP_IN_DGI_D4 121 13401404648SChun-Jie Chen #define CLK_TOP_IN_DGI_D6 122 13501404648SChun-Jie Chen #define CLK_TOP_IN_DGI_D8 123 13601404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D3 124 13701404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D4 125 13801404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D4_D2 126 13901404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D4_D4 127 14001404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D4_D8 128 14101404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D5 129 14201404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D5_D2 130 14301404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D5_D4 131 14401404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D5_D8 132 14501404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D6 133 14601404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D6_D2 134 14701404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D6_D4 135 14801404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D6_D8 136 14901404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D7 137 15001404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D7_D2 138 15101404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D7_D4 139 15201404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D7_D8 140 15301404648SChun-Jie Chen #define CLK_TOP_MAINPLL_D9 141 15401404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D2 142 15501404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D3 143 15601404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D4 144 15701404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D4_D2 145 15801404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D4_D4 146 15901404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D4_D8 147 16001404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D5 148 16101404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D5_D2 149 16201404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D5_D4 150 16301404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D5_D8 151 16401404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D6 152 16501404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D6_D2 153 16601404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D6_D4 154 16701404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D6_D8 155 16801404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D6_D16 156 16901404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_D7 157 17001404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_192M 158 17101404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D4 159 17201404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D8 160 17301404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D16 161 17401404648SChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D32 162 17501404648SChun-Jie Chen #define CLK_TOP_APLL1_D3 163 17601404648SChun-Jie Chen #define CLK_TOP_APLL1_D4 164 17701404648SChun-Jie Chen #define CLK_TOP_APLL2_D3 165 17801404648SChun-Jie Chen #define CLK_TOP_APLL2_D4 166 17901404648SChun-Jie Chen #define CLK_TOP_APLL3_D4 167 18001404648SChun-Jie Chen #define CLK_TOP_APLL4_D4 168 18101404648SChun-Jie Chen #define CLK_TOP_APLL5_D4 169 18201404648SChun-Jie Chen #define CLK_TOP_HDMIRX_APLL_D3 170 18301404648SChun-Jie Chen #define CLK_TOP_HDMIRX_APLL_D4 171 18401404648SChun-Jie Chen #define CLK_TOP_HDMIRX_APLL_D6 172 18501404648SChun-Jie Chen #define CLK_TOP_MMPLL_D4 173 18601404648SChun-Jie Chen #define CLK_TOP_MMPLL_D4_D2 174 18701404648SChun-Jie Chen #define CLK_TOP_MMPLL_D4_D4 175 18801404648SChun-Jie Chen #define CLK_TOP_MMPLL_D5 176 18901404648SChun-Jie Chen #define CLK_TOP_MMPLL_D5_D2 177 19001404648SChun-Jie Chen #define CLK_TOP_MMPLL_D5_D4 178 19101404648SChun-Jie Chen #define CLK_TOP_MMPLL_D6 179 19201404648SChun-Jie Chen #define CLK_TOP_MMPLL_D6_D2 180 19301404648SChun-Jie Chen #define CLK_TOP_MMPLL_D7 181 19401404648SChun-Jie Chen #define CLK_TOP_MMPLL_D9 182 19501404648SChun-Jie Chen #define CLK_TOP_TVDPLL1_D2 183 19601404648SChun-Jie Chen #define CLK_TOP_TVDPLL1_D4 184 19701404648SChun-Jie Chen #define CLK_TOP_TVDPLL1_D8 185 19801404648SChun-Jie Chen #define CLK_TOP_TVDPLL1_D16 186 19901404648SChun-Jie Chen #define CLK_TOP_TVDPLL2_D2 187 20001404648SChun-Jie Chen #define CLK_TOP_TVDPLL2_D4 188 20101404648SChun-Jie Chen #define CLK_TOP_TVDPLL2_D8 189 20201404648SChun-Jie Chen #define CLK_TOP_TVDPLL2_D16 190 20301404648SChun-Jie Chen #define CLK_TOP_MSDCPLL_D2 191 20401404648SChun-Jie Chen #define CLK_TOP_MSDCPLL_D4 192 20501404648SChun-Jie Chen #define CLK_TOP_MSDCPLL_D16 193 20601404648SChun-Jie Chen #define CLK_TOP_ETHPLL_D2 194 20701404648SChun-Jie Chen #define CLK_TOP_ETHPLL_D8 195 20801404648SChun-Jie Chen #define CLK_TOP_ETHPLL_D10 196 20901404648SChun-Jie Chen #define CLK_TOP_DGIPLL_D2 197 21001404648SChun-Jie Chen #define CLK_TOP_ULPOSC1 198 21101404648SChun-Jie Chen #define CLK_TOP_ULPOSC1_D2 199 21201404648SChun-Jie Chen #define CLK_TOP_ULPOSC1_D4 200 21301404648SChun-Jie Chen #define CLK_TOP_ULPOSC1_D7 201 21401404648SChun-Jie Chen #define CLK_TOP_ULPOSC1_D8 202 21501404648SChun-Jie Chen #define CLK_TOP_ULPOSC1_D10 203 21601404648SChun-Jie Chen #define CLK_TOP_ULPOSC1_D16 204 21701404648SChun-Jie Chen #define CLK_TOP_ULPOSC2 205 21801404648SChun-Jie Chen #define CLK_TOP_ADSPPLL_D2 206 21901404648SChun-Jie Chen #define CLK_TOP_ADSPPLL_D4 207 22001404648SChun-Jie Chen #define CLK_TOP_ADSPPLL_D8 208 22101404648SChun-Jie Chen #define CLK_TOP_MEM_466M 209 22201404648SChun-Jie Chen #define CLK_TOP_MPHONE_SLAVE_B 210 22301404648SChun-Jie Chen #define CLK_TOP_PEXTP_PIPE 211 22401404648SChun-Jie Chen #define CLK_TOP_UFS_RX_SYMBOL 212 22501404648SChun-Jie Chen #define CLK_TOP_UFS_TX_SYMBOL 213 22601404648SChun-Jie Chen #define CLK_TOP_SSUSB_U3PHY_P1_P_P0 214 22701404648SChun-Jie Chen #define CLK_TOP_UFS_RX_SYMBOL1 215 22801404648SChun-Jie Chen #define CLK_TOP_FPC 216 22901404648SChun-Jie Chen #define CLK_TOP_HDMIRX_P 217 23001404648SChun-Jie Chen #define CLK_TOP_APLL12_DIV0 218 23101404648SChun-Jie Chen #define CLK_TOP_APLL12_DIV1 219 23201404648SChun-Jie Chen #define CLK_TOP_APLL12_DIV2 220 23301404648SChun-Jie Chen #define CLK_TOP_APLL12_DIV3 221 23401404648SChun-Jie Chen #define CLK_TOP_APLL12_DIV4 222 23501404648SChun-Jie Chen #define CLK_TOP_APLL12_DIV9 223 23601404648SChun-Jie Chen #define CLK_TOP_CFG_VPP0 224 23701404648SChun-Jie Chen #define CLK_TOP_CFG_VPP1 225 23801404648SChun-Jie Chen #define CLK_TOP_CFG_VDO0 226 23901404648SChun-Jie Chen #define CLK_TOP_CFG_VDO1 227 24001404648SChun-Jie Chen #define CLK_TOP_CFG_UNIPLL_SES 228 24101404648SChun-Jie Chen #define CLK_TOP_CFG_26M_VPP0 229 24201404648SChun-Jie Chen #define CLK_TOP_CFG_26M_VPP1 230 24301404648SChun-Jie Chen #define CLK_TOP_CFG_26M_AUD 231 24401404648SChun-Jie Chen #define CLK_TOP_CFG_AXI_EAST 232 24501404648SChun-Jie Chen #define CLK_TOP_CFG_AXI_EAST_NORTH 233 24601404648SChun-Jie Chen #define CLK_TOP_CFG_AXI_NORTH 234 24701404648SChun-Jie Chen #define CLK_TOP_CFG_AXI_SOUTH 235 24801404648SChun-Jie Chen #define CLK_TOP_CFG_EXT_TEST 236 24901404648SChun-Jie Chen #define CLK_TOP_SSUSB_REF 237 25001404648SChun-Jie Chen #define CLK_TOP_SSUSB_PHY_REF 238 25101404648SChun-Jie Chen #define CLK_TOP_SSUSB_P1_REF 239 25201404648SChun-Jie Chen #define CLK_TOP_SSUSB_PHY_P1_REF 240 25301404648SChun-Jie Chen #define CLK_TOP_SSUSB_P2_REF 241 25401404648SChun-Jie Chen #define CLK_TOP_SSUSB_PHY_P2_REF 242 25501404648SChun-Jie Chen #define CLK_TOP_SSUSB_P3_REF 243 25601404648SChun-Jie Chen #define CLK_TOP_SSUSB_PHY_P3_REF 244 25701404648SChun-Jie Chen #define CLK_TOP_NR_CLK 245 25801404648SChun-Jie Chen 25901404648SChun-Jie Chen /* INFRACFG_AO */ 26001404648SChun-Jie Chen 26101404648SChun-Jie Chen #define CLK_INFRA_AO_PMIC_TMR 0 26201404648SChun-Jie Chen #define CLK_INFRA_AO_PMIC_AP 1 26301404648SChun-Jie Chen #define CLK_INFRA_AO_PMIC_MD 2 26401404648SChun-Jie Chen #define CLK_INFRA_AO_PMIC_CONN 3 26501404648SChun-Jie Chen #define CLK_INFRA_AO_SEJ 4 26601404648SChun-Jie Chen #define CLK_INFRA_AO_APXGPT 5 26701404648SChun-Jie Chen #define CLK_INFRA_AO_GCE 6 26801404648SChun-Jie Chen #define CLK_INFRA_AO_GCE2 7 26901404648SChun-Jie Chen #define CLK_INFRA_AO_THERM 8 27001404648SChun-Jie Chen #define CLK_INFRA_AO_PWM_H 9 27101404648SChun-Jie Chen #define CLK_INFRA_AO_PWM1 10 27201404648SChun-Jie Chen #define CLK_INFRA_AO_PWM2 11 27301404648SChun-Jie Chen #define CLK_INFRA_AO_PWM3 12 27401404648SChun-Jie Chen #define CLK_INFRA_AO_PWM4 13 27501404648SChun-Jie Chen #define CLK_INFRA_AO_PWM 14 27601404648SChun-Jie Chen #define CLK_INFRA_AO_UART0 15 27701404648SChun-Jie Chen #define CLK_INFRA_AO_UART1 16 27801404648SChun-Jie Chen #define CLK_INFRA_AO_UART2 17 27901404648SChun-Jie Chen #define CLK_INFRA_AO_UART3 18 28001404648SChun-Jie Chen #define CLK_INFRA_AO_UART4 19 28101404648SChun-Jie Chen #define CLK_INFRA_AO_GCE_26M 20 28201404648SChun-Jie Chen #define CLK_INFRA_AO_CQ_DMA_FPC 21 28301404648SChun-Jie Chen #define CLK_INFRA_AO_UART5 22 28401404648SChun-Jie Chen #define CLK_INFRA_AO_HDMI_26M 23 28501404648SChun-Jie Chen #define CLK_INFRA_AO_SPI0 24 28601404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC0 25 28701404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC1 26 28801404648SChun-Jie Chen #define CLK_INFRA_AO_CG1_MSDC2 27 28901404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC0_SRC 28 29001404648SChun-Jie Chen #define CLK_INFRA_AO_TRNG 29 29101404648SChun-Jie Chen #define CLK_INFRA_AO_AUXADC 30 29201404648SChun-Jie Chen #define CLK_INFRA_AO_CPUM 31 29301404648SChun-Jie Chen #define CLK_INFRA_AO_HDMI_32K 32 29401404648SChun-Jie Chen #define CLK_INFRA_AO_CEC_66M_H 33 29501404648SChun-Jie Chen #define CLK_INFRA_AO_IRRX 34 29601404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_TL_26M 35 29701404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC1_SRC 36 29801404648SChun-Jie Chen #define CLK_INFRA_AO_CEC_66M_B 37 29901404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_TL_96M 38 30001404648SChun-Jie Chen #define CLK_INFRA_AO_DEVICE_APC 39 30101404648SChun-Jie Chen #define CLK_INFRA_AO_ECC_66M_H 40 30201404648SChun-Jie Chen #define CLK_INFRA_AO_DEBUGSYS 41 30301404648SChun-Jie Chen #define CLK_INFRA_AO_AUDIO 42 30401404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_TL_32K 43 30501404648SChun-Jie Chen #define CLK_INFRA_AO_DBG_TRACE 44 30601404648SChun-Jie Chen #define CLK_INFRA_AO_DRAMC_F26M 45 30701404648SChun-Jie Chen #define CLK_INFRA_AO_IRTX 46 30801404648SChun-Jie Chen #define CLK_INFRA_AO_SSUSB 47 30901404648SChun-Jie Chen #define CLK_INFRA_AO_DISP_PWM 48 31001404648SChun-Jie Chen #define CLK_INFRA_AO_CLDMA_B 49 31101404648SChun-Jie Chen #define CLK_INFRA_AO_AUDIO_26M_B 50 31201404648SChun-Jie Chen #define CLK_INFRA_AO_SPI1 51 31301404648SChun-Jie Chen #define CLK_INFRA_AO_SPI2 52 31401404648SChun-Jie Chen #define CLK_INFRA_AO_SPI3 53 31501404648SChun-Jie Chen #define CLK_INFRA_AO_UNIPRO_SYS 54 31601404648SChun-Jie Chen #define CLK_INFRA_AO_UNIPRO_TICK 55 31701404648SChun-Jie Chen #define CLK_INFRA_AO_UFS_MP_SAP_B 56 31801404648SChun-Jie Chen #define CLK_INFRA_AO_PWRMCU 57 31901404648SChun-Jie Chen #define CLK_INFRA_AO_PWRMCU_BUS_H 58 32001404648SChun-Jie Chen #define CLK_INFRA_AO_APDMA_B 59 32101404648SChun-Jie Chen #define CLK_INFRA_AO_SPI4 60 32201404648SChun-Jie Chen #define CLK_INFRA_AO_SPI5 61 32301404648SChun-Jie Chen #define CLK_INFRA_AO_CQ_DMA 62 32401404648SChun-Jie Chen #define CLK_INFRA_AO_AES_UFSFDE 63 32501404648SChun-Jie Chen #define CLK_INFRA_AO_AES 64 32601404648SChun-Jie Chen #define CLK_INFRA_AO_UFS_TICK 65 32701404648SChun-Jie Chen #define CLK_INFRA_AO_SSUSB_XHCI 66 32801404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC0_SELF 67 32901404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC1_SELF 68 33001404648SChun-Jie Chen #define CLK_INFRA_AO_MSDC2_SELF 69 33101404648SChun-Jie Chen #define CLK_INFRA_AO_I2S_DMA 70 33201404648SChun-Jie Chen #define CLK_INFRA_AO_AP_MSDC0 71 33301404648SChun-Jie Chen #define CLK_INFRA_AO_MD_MSDC0 72 33401404648SChun-Jie Chen #define CLK_INFRA_AO_CG3_MSDC2 73 33501404648SChun-Jie Chen #define CLK_INFRA_AO_GCPU 74 33601404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_PERI_26M 75 33701404648SChun-Jie Chen #define CLK_INFRA_AO_GCPU_66M_B 76 33801404648SChun-Jie Chen #define CLK_INFRA_AO_GCPU_133M_B 77 33901404648SChun-Jie Chen #define CLK_INFRA_AO_DISP_PWM1 78 34001404648SChun-Jie Chen #define CLK_INFRA_AO_FBIST2FPC 79 34101404648SChun-Jie Chen #define CLK_INFRA_AO_DEVICE_APC_SYNC 80 34201404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_P1_PERI_26M 81 34301404648SChun-Jie Chen #define CLK_INFRA_AO_SPIS0 82 34401404648SChun-Jie Chen #define CLK_INFRA_AO_SPIS1 83 34501404648SChun-Jie Chen #define CLK_INFRA_AO_133M_M_PERI 84 34601404648SChun-Jie Chen #define CLK_INFRA_AO_66M_M_PERI 85 34701404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_PL_P_250M_P0 86 34801404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_PL_P_250M_P1 87 34901404648SChun-Jie Chen #define CLK_INFRA_AO_PCIE_P1_TL_96M 88 35001404648SChun-Jie Chen #define CLK_INFRA_AO_AES_MSDCFDE_0P 89 35101404648SChun-Jie Chen #define CLK_INFRA_AO_UFS_TX_SYMBOL 90 35201404648SChun-Jie Chen #define CLK_INFRA_AO_UFS_RX_SYMBOL 91 35301404648SChun-Jie Chen #define CLK_INFRA_AO_UFS_RX_SYMBOL1 92 35401404648SChun-Jie Chen #define CLK_INFRA_AO_PERI_UFS_MEM_SUB 93 35501404648SChun-Jie Chen #define CLK_INFRA_AO_NR_CLK 94 35601404648SChun-Jie Chen 35701404648SChun-Jie Chen /* APMIXEDSYS */ 35801404648SChun-Jie Chen 35901404648SChun-Jie Chen #define CLK_APMIXED_NNAPLL 0 36001404648SChun-Jie Chen #define CLK_APMIXED_RESPLL 1 36101404648SChun-Jie Chen #define CLK_APMIXED_ETHPLL 2 36201404648SChun-Jie Chen #define CLK_APMIXED_MSDCPLL 3 36301404648SChun-Jie Chen #define CLK_APMIXED_TVDPLL1 4 36401404648SChun-Jie Chen #define CLK_APMIXED_TVDPLL2 5 36501404648SChun-Jie Chen #define CLK_APMIXED_MMPLL 6 36601404648SChun-Jie Chen #define CLK_APMIXED_MAINPLL 7 36701404648SChun-Jie Chen #define CLK_APMIXED_VDECPLL 8 36801404648SChun-Jie Chen #define CLK_APMIXED_IMGPLL 9 36901404648SChun-Jie Chen #define CLK_APMIXED_UNIVPLL 10 37001404648SChun-Jie Chen #define CLK_APMIXED_HDMIPLL1 11 37101404648SChun-Jie Chen #define CLK_APMIXED_HDMIPLL2 12 37201404648SChun-Jie Chen #define CLK_APMIXED_HDMIRX_APLL 13 37301404648SChun-Jie Chen #define CLK_APMIXED_USB1PLL 14 37401404648SChun-Jie Chen #define CLK_APMIXED_ADSPPLL 15 37501404648SChun-Jie Chen #define CLK_APMIXED_APLL1 16 37601404648SChun-Jie Chen #define CLK_APMIXED_APLL2 17 37701404648SChun-Jie Chen #define CLK_APMIXED_APLL3 18 37801404648SChun-Jie Chen #define CLK_APMIXED_APLL4 19 37901404648SChun-Jie Chen #define CLK_APMIXED_APLL5 20 38001404648SChun-Jie Chen #define CLK_APMIXED_MFGPLL 21 38101404648SChun-Jie Chen #define CLK_APMIXED_DGIPLL 22 38201404648SChun-Jie Chen #define CLK_APMIXED_PLL_SSUSB26M 23 38301404648SChun-Jie Chen #define CLK_APMIXED_NR_CLK 24 38401404648SChun-Jie Chen 38501404648SChun-Jie Chen /* SCP_ADSP */ 38601404648SChun-Jie Chen 38701404648SChun-Jie Chen #define CLK_SCP_ADSP_AUDIODSP 0 38801404648SChun-Jie Chen #define CLK_SCP_ADSP_NR_CLK 1 38901404648SChun-Jie Chen 39001404648SChun-Jie Chen /* PERICFG_AO */ 39101404648SChun-Jie Chen 39201404648SChun-Jie Chen #define CLK_PERI_AO_ETHERNET 0 39301404648SChun-Jie Chen #define CLK_PERI_AO_ETHERNET_BUS 1 39401404648SChun-Jie Chen #define CLK_PERI_AO_FLASHIF_BUS 2 39501404648SChun-Jie Chen #define CLK_PERI_AO_FLASHIF_FLASH 3 39601404648SChun-Jie Chen #define CLK_PERI_AO_SSUSB_1P_BUS 4 39701404648SChun-Jie Chen #define CLK_PERI_AO_SSUSB_1P_XHCI 5 39801404648SChun-Jie Chen #define CLK_PERI_AO_SSUSB_2P_BUS 6 39901404648SChun-Jie Chen #define CLK_PERI_AO_SSUSB_2P_XHCI 7 40001404648SChun-Jie Chen #define CLK_PERI_AO_SSUSB_3P_BUS 8 40101404648SChun-Jie Chen #define CLK_PERI_AO_SSUSB_3P_XHCI 9 40201404648SChun-Jie Chen #define CLK_PERI_AO_SPINFI 10 40301404648SChun-Jie Chen #define CLK_PERI_AO_ETHERNET_MAC 11 40401404648SChun-Jie Chen #define CLK_PERI_AO_NFI_H 12 40501404648SChun-Jie Chen #define CLK_PERI_AO_FNFI1X 13 40601404648SChun-Jie Chen #define CLK_PERI_AO_PCIE_P0_MEM 14 40701404648SChun-Jie Chen #define CLK_PERI_AO_PCIE_P1_MEM 15 40801404648SChun-Jie Chen #define CLK_PERI_AO_NR_CLK 16 40901404648SChun-Jie Chen 41001404648SChun-Jie Chen /* IMP_IIC_WRAP_S */ 41101404648SChun-Jie Chen 41201404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_S_I2C5 0 41301404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_S_I2C6 1 41401404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_S_I2C7 2 41501404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_S_NR_CLK 3 41601404648SChun-Jie Chen 41701404648SChun-Jie Chen /* IMP_IIC_WRAP_W */ 41801404648SChun-Jie Chen 41901404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_W_I2C0 0 42001404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_W_I2C1 1 42101404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_W_I2C2 2 42201404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_W_I2C3 3 42301404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_W_I2C4 4 42401404648SChun-Jie Chen #define CLK_IMP_IIC_WRAP_W_NR_CLK 5 42501404648SChun-Jie Chen 42601404648SChun-Jie Chen /* MFGCFG */ 42701404648SChun-Jie Chen 42801404648SChun-Jie Chen #define CLK_MFG_BG3D 0 42901404648SChun-Jie Chen #define CLK_MFG_NR_CLK 1 43001404648SChun-Jie Chen 43101404648SChun-Jie Chen /* VPPSYS0 */ 43201404648SChun-Jie Chen 43301404648SChun-Jie Chen #define CLK_VPP0_MDP_FG 0 43401404648SChun-Jie Chen #define CLK_VPP0_STITCH 1 43501404648SChun-Jie Chen #define CLK_VPP0_PADDING 2 43601404648SChun-Jie Chen #define CLK_VPP0_MDP_TCC 3 43701404648SChun-Jie Chen #define CLK_VPP0_WARP0_ASYNC_TX 4 43801404648SChun-Jie Chen #define CLK_VPP0_WARP1_ASYNC_TX 5 43901404648SChun-Jie Chen #define CLK_VPP0_MUTEX 6 44001404648SChun-Jie Chen #define CLK_VPP0_VPP02VPP1_RELAY 7 44101404648SChun-Jie Chen #define CLK_VPP0_VPP12VPP0_ASYNC 8 44201404648SChun-Jie Chen #define CLK_VPP0_MMSYSRAM_TOP 9 44301404648SChun-Jie Chen #define CLK_VPP0_MDP_AAL 10 44401404648SChun-Jie Chen #define CLK_VPP0_MDP_RSZ 11 44501404648SChun-Jie Chen #define CLK_VPP0_SMI_COMMON 12 44601404648SChun-Jie Chen #define CLK_VPP0_GALS_VDO0_LARB0 13 44701404648SChun-Jie Chen #define CLK_VPP0_GALS_VDO0_LARB1 14 44801404648SChun-Jie Chen #define CLK_VPP0_GALS_VENCSYS 15 44901404648SChun-Jie Chen #define CLK_VPP0_GALS_VENCSYS_CORE1 16 45001404648SChun-Jie Chen #define CLK_VPP0_GALS_INFRA 17 45101404648SChun-Jie Chen #define CLK_VPP0_GALS_CAMSYS 18 45201404648SChun-Jie Chen #define CLK_VPP0_GALS_VPP1_LARB5 19 45301404648SChun-Jie Chen #define CLK_VPP0_GALS_VPP1_LARB6 20 45401404648SChun-Jie Chen #define CLK_VPP0_SMI_REORDER 21 45501404648SChun-Jie Chen #define CLK_VPP0_SMI_IOMMU 22 45601404648SChun-Jie Chen #define CLK_VPP0_GALS_IMGSYS_CAMSYS 23 45701404648SChun-Jie Chen #define CLK_VPP0_MDP_RDMA 24 45801404648SChun-Jie Chen #define CLK_VPP0_MDP_WROT 25 45901404648SChun-Jie Chen #define CLK_VPP0_GALS_EMI0_EMI1 26 46001404648SChun-Jie Chen #define CLK_VPP0_SMI_SUB_COMMON_REORDER 27 46101404648SChun-Jie Chen #define CLK_VPP0_SMI_RSI 28 46201404648SChun-Jie Chen #define CLK_VPP0_SMI_COMMON_LARB4 29 46301404648SChun-Jie Chen #define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30 46401404648SChun-Jie Chen #define CLK_VPP0_GALS_VPP1_WPE 31 46501404648SChun-Jie Chen #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 46601404648SChun-Jie Chen #define CLK_VPP0_FAKE_ENG 33 46701404648SChun-Jie Chen #define CLK_VPP0_MDP_HDR 34 46801404648SChun-Jie Chen #define CLK_VPP0_MDP_TDSHP 35 46901404648SChun-Jie Chen #define CLK_VPP0_MDP_COLOR 36 47001404648SChun-Jie Chen #define CLK_VPP0_MDP_OVL 37 47101404648SChun-Jie Chen #define CLK_VPP0_WARP0_RELAY 38 47201404648SChun-Jie Chen #define CLK_VPP0_WARP0_MDP_DL_ASYNC 39 47301404648SChun-Jie Chen #define CLK_VPP0_WARP1_RELAY 40 47401404648SChun-Jie Chen #define CLK_VPP0_WARP1_MDP_DL_ASYNC 41 47501404648SChun-Jie Chen #define CLK_VPP0_NR_CLK 42 47601404648SChun-Jie Chen 47701404648SChun-Jie Chen /* WPESYS */ 47801404648SChun-Jie Chen 47901404648SChun-Jie Chen #define CLK_WPE_VPP0 0 48001404648SChun-Jie Chen #define CLK_WPE_VPP1 1 48101404648SChun-Jie Chen #define CLK_WPE_SMI_LARB7 2 48201404648SChun-Jie Chen #define CLK_WPE_SMI_LARB8 3 48301404648SChun-Jie Chen #define CLK_WPE_EVENT_TX 4 48401404648SChun-Jie Chen #define CLK_WPE_SMI_LARB7_P 5 48501404648SChun-Jie Chen #define CLK_WPE_SMI_LARB8_P 6 48601404648SChun-Jie Chen #define CLK_WPE_NR_CLK 7 48701404648SChun-Jie Chen 48801404648SChun-Jie Chen /* WPESYS_VPP0 */ 48901404648SChun-Jie Chen 49001404648SChun-Jie Chen #define CLK_WPE_VPP0_VECI 0 49101404648SChun-Jie Chen #define CLK_WPE_VPP0_VEC2I 1 49201404648SChun-Jie Chen #define CLK_WPE_VPP0_VEC3I 2 49301404648SChun-Jie Chen #define CLK_WPE_VPP0_WPEO 3 49401404648SChun-Jie Chen #define CLK_WPE_VPP0_MSKO 4 49501404648SChun-Jie Chen #define CLK_WPE_VPP0_VGEN 5 49601404648SChun-Jie Chen #define CLK_WPE_VPP0_EXT 6 49701404648SChun-Jie Chen #define CLK_WPE_VPP0_VFC 7 49801404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH0_TOP 8 49901404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH0_DMA 9 50001404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH1_TOP 10 50101404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH1_DMA 11 50201404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH2_TOP 12 50301404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH2_DMA 13 50401404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH3_TOP 14 50501404648SChun-Jie Chen #define CLK_WPE_VPP0_CACH3_DMA 15 50601404648SChun-Jie Chen #define CLK_WPE_VPP0_PSP 16 50701404648SChun-Jie Chen #define CLK_WPE_VPP0_PSP2 17 50801404648SChun-Jie Chen #define CLK_WPE_VPP0_SYNC 18 50901404648SChun-Jie Chen #define CLK_WPE_VPP0_C24 19 51001404648SChun-Jie Chen #define CLK_WPE_VPP0_MDP_CROP 20 51101404648SChun-Jie Chen #define CLK_WPE_VPP0_ISP_CROP 21 51201404648SChun-Jie Chen #define CLK_WPE_VPP0_TOP 22 51301404648SChun-Jie Chen #define CLK_WPE_VPP0_NR_CLK 23 51401404648SChun-Jie Chen 51501404648SChun-Jie Chen /* WPESYS_VPP1 */ 51601404648SChun-Jie Chen 51701404648SChun-Jie Chen #define CLK_WPE_VPP1_VECI 0 51801404648SChun-Jie Chen #define CLK_WPE_VPP1_VEC2I 1 51901404648SChun-Jie Chen #define CLK_WPE_VPP1_VEC3I 2 52001404648SChun-Jie Chen #define CLK_WPE_VPP1_WPEO 3 52101404648SChun-Jie Chen #define CLK_WPE_VPP1_MSKO 4 52201404648SChun-Jie Chen #define CLK_WPE_VPP1_VGEN 5 52301404648SChun-Jie Chen #define CLK_WPE_VPP1_EXT 6 52401404648SChun-Jie Chen #define CLK_WPE_VPP1_VFC 7 52501404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH0_TOP 8 52601404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH0_DMA 9 52701404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH1_TOP 10 52801404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH1_DMA 11 52901404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH2_TOP 12 53001404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH2_DMA 13 53101404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH3_TOP 14 53201404648SChun-Jie Chen #define CLK_WPE_VPP1_CACH3_DMA 15 53301404648SChun-Jie Chen #define CLK_WPE_VPP1_PSP 16 53401404648SChun-Jie Chen #define CLK_WPE_VPP1_PSP2 17 53501404648SChun-Jie Chen #define CLK_WPE_VPP1_SYNC 18 53601404648SChun-Jie Chen #define CLK_WPE_VPP1_C24 19 53701404648SChun-Jie Chen #define CLK_WPE_VPP1_MDP_CROP 20 53801404648SChun-Jie Chen #define CLK_WPE_VPP1_ISP_CROP 21 53901404648SChun-Jie Chen #define CLK_WPE_VPP1_TOP 22 54001404648SChun-Jie Chen #define CLK_WPE_VPP1_NR_CLK 23 54101404648SChun-Jie Chen 54201404648SChun-Jie Chen /* VPPSYS1 */ 54301404648SChun-Jie Chen 54401404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_OVL 0 54501404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_TCC 1 54601404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_WROT 2 54701404648SChun-Jie Chen #define CLK_VPP1_SVPP1_VPP_PAD 3 54801404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_WROT 4 54901404648SChun-Jie Chen #define CLK_VPP1_SVPP2_VPP_PAD 5 55001404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_WROT 6 55101404648SChun-Jie Chen #define CLK_VPP1_SVPP3_VPP_PAD 7 55201404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_RDMA 8 55301404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_FG 9 55401404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_RDMA 10 55501404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_FG 11 55601404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_RDMA 12 55701404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_FG 13 55801404648SChun-Jie Chen #define CLK_VPP1_VPP_SPLIT 14 55901404648SChun-Jie Chen #define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15 56001404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_TDSHP 16 56101404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_COLOR 17 56201404648SChun-Jie Chen #define CLK_VPP1_SVPP3_VDO1_DL_RELAY 18 56301404648SChun-Jie Chen #define CLK_VPP1_SVPP2_VPP_MERGE 19 56401404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_COLOR 20 56501404648SChun-Jie Chen #define CLK_VPP1_VPPSYS1_GALS 21 56601404648SChun-Jie Chen #define CLK_VPP1_SVPP3_VPP_MERGE 22 56701404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_COLOR 23 56801404648SChun-Jie Chen #define CLK_VPP1_VPPSYS1_LARB 24 56901404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_RSZ 25 57001404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_HDR 26 57101404648SChun-Jie Chen #define CLK_VPP1_SVPP1_MDP_AAL 27 57201404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_HDR 28 57301404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_AAL 29 57401404648SChun-Jie Chen #define CLK_VPP1_DL_ASYNC 30 57501404648SChun-Jie Chen #define CLK_VPP1_LARB5_FAKE_ENG 31 57601404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_HDR 32 57701404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_AAL 33 57801404648SChun-Jie Chen #define CLK_VPP1_SVPP2_VDO1_DL_RELAY 34 57901404648SChun-Jie Chen #define CLK_VPP1_LARB6_FAKE_ENG 35 58001404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_RSZ 36 58101404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_RSZ 37 58201404648SChun-Jie Chen #define CLK_VPP1_SVPP3_VDO0_DL_RELAY 38 58301404648SChun-Jie Chen #define CLK_VPP1_DISP_MUTEX 39 58401404648SChun-Jie Chen #define CLK_VPP1_SVPP2_MDP_TDSHP 40 58501404648SChun-Jie Chen #define CLK_VPP1_SVPP3_MDP_TDSHP 41 58601404648SChun-Jie Chen #define CLK_VPP1_VPP0_DL1_RELAY 42 58701404648SChun-Jie Chen #define CLK_VPP1_HDMI_META 43 58801404648SChun-Jie Chen #define CLK_VPP1_VPP_SPLIT_HDMI 44 58901404648SChun-Jie Chen #define CLK_VPP1_DGI_IN 45 59001404648SChun-Jie Chen #define CLK_VPP1_DGI_OUT 46 59101404648SChun-Jie Chen #define CLK_VPP1_VPP_SPLIT_DGI 47 59201404648SChun-Jie Chen #define CLK_VPP1_VPP0_DL_ASYNC 48 59301404648SChun-Jie Chen #define CLK_VPP1_VPP0_DL_RELAY 49 59401404648SChun-Jie Chen #define CLK_VPP1_VPP_SPLIT_26M 50 59501404648SChun-Jie Chen #define CLK_VPP1_NR_CLK 51 59601404648SChun-Jie Chen 59701404648SChun-Jie Chen /* IMGSYS */ 59801404648SChun-Jie Chen 59901404648SChun-Jie Chen #define CLK_IMG_LARB9 0 60001404648SChun-Jie Chen #define CLK_IMG_TRAW0 1 60101404648SChun-Jie Chen #define CLK_IMG_TRAW1 2 60201404648SChun-Jie Chen #define CLK_IMG_TRAW2 3 60301404648SChun-Jie Chen #define CLK_IMG_TRAW3 4 60401404648SChun-Jie Chen #define CLK_IMG_DIP0 5 60501404648SChun-Jie Chen #define CLK_IMG_WPE0 6 60601404648SChun-Jie Chen #define CLK_IMG_IPE 7 60701404648SChun-Jie Chen #define CLK_IMG_DIP1 8 60801404648SChun-Jie Chen #define CLK_IMG_WPE1 9 60901404648SChun-Jie Chen #define CLK_IMG_GALS 10 61001404648SChun-Jie Chen #define CLK_IMG_NR_CLK 11 61101404648SChun-Jie Chen 61201404648SChun-Jie Chen /* IMGSYS1_DIP_TOP */ 61301404648SChun-Jie Chen 61401404648SChun-Jie Chen #define CLK_IMG1_DIP_TOP_LARB10 0 61501404648SChun-Jie Chen #define CLK_IMG1_DIP_TOP_DIP_TOP 1 61601404648SChun-Jie Chen #define CLK_IMG1_DIP_TOP_NR_CLK 2 61701404648SChun-Jie Chen 61801404648SChun-Jie Chen /* IMGSYS1_DIP_NR */ 61901404648SChun-Jie Chen 62001404648SChun-Jie Chen #define CLK_IMG1_DIP_NR_RESERVE 0 62101404648SChun-Jie Chen #define CLK_IMG1_DIP_NR_DIP_NR 1 62201404648SChun-Jie Chen #define CLK_IMG1_DIP_NR_NR_CLK 2 62301404648SChun-Jie Chen 62401404648SChun-Jie Chen /* IMGSYS1_WPE */ 62501404648SChun-Jie Chen 62601404648SChun-Jie Chen #define CLK_IMG1_WPE_LARB11 0 62701404648SChun-Jie Chen #define CLK_IMG1_WPE_WPE 1 62801404648SChun-Jie Chen #define CLK_IMG1_WPE_NR_CLK 2 62901404648SChun-Jie Chen 63001404648SChun-Jie Chen /* IPESYS */ 63101404648SChun-Jie Chen 63201404648SChun-Jie Chen #define CLK_IPE_DPE 0 63301404648SChun-Jie Chen #define CLK_IPE_FDVT 1 63401404648SChun-Jie Chen #define CLK_IPE_ME 2 63501404648SChun-Jie Chen #define CLK_IPE_TOP 3 63601404648SChun-Jie Chen #define CLK_IPE_SMI_LARB12 4 63701404648SChun-Jie Chen #define CLK_IPE_NR_CLK 5 63801404648SChun-Jie Chen 63901404648SChun-Jie Chen /* CAMSYS */ 64001404648SChun-Jie Chen 64101404648SChun-Jie Chen #define CLK_CAM_LARB13 0 64201404648SChun-Jie Chen #define CLK_CAM_LARB14 1 64301404648SChun-Jie Chen #define CLK_CAM_MAIN_CAM 2 64401404648SChun-Jie Chen #define CLK_CAM_MAIN_CAMTG 3 64501404648SChun-Jie Chen #define CLK_CAM_SENINF 4 64601404648SChun-Jie Chen #define CLK_CAM_GCAMSVA 5 64701404648SChun-Jie Chen #define CLK_CAM_GCAMSVB 6 64801404648SChun-Jie Chen #define CLK_CAM_GCAMSVC 7 64901404648SChun-Jie Chen #define CLK_CAM_SCAMSA 8 65001404648SChun-Jie Chen #define CLK_CAM_SCAMSB 9 65101404648SChun-Jie Chen #define CLK_CAM_CAMSV_TOP 10 65201404648SChun-Jie Chen #define CLK_CAM_CAMSV_CQ 11 65301404648SChun-Jie Chen #define CLK_CAM_ADL 12 65401404648SChun-Jie Chen #define CLK_CAM_ASG 13 65501404648SChun-Jie Chen #define CLK_CAM_PDA 14 65601404648SChun-Jie Chen #define CLK_CAM_FAKE_ENG 15 65701404648SChun-Jie Chen #define CLK_CAM_MAIN_MRAW0 16 65801404648SChun-Jie Chen #define CLK_CAM_MAIN_MRAW1 17 65901404648SChun-Jie Chen #define CLK_CAM_MAIN_MRAW2 18 66001404648SChun-Jie Chen #define CLK_CAM_MAIN_MRAW3 19 66101404648SChun-Jie Chen #define CLK_CAM_CAM2MM0_GALS 20 66201404648SChun-Jie Chen #define CLK_CAM_CAM2MM1_GALS 21 66301404648SChun-Jie Chen #define CLK_CAM_CAM2SYS_GALS 22 66401404648SChun-Jie Chen #define CLK_CAM_NR_CLK 23 66501404648SChun-Jie Chen 66601404648SChun-Jie Chen /* CAMSYS_RAWA */ 66701404648SChun-Jie Chen 66801404648SChun-Jie Chen #define CLK_CAM_RAWA_LARBX 0 66901404648SChun-Jie Chen #define CLK_CAM_RAWA_CAM 1 67001404648SChun-Jie Chen #define CLK_CAM_RAWA_CAMTG 2 67101404648SChun-Jie Chen #define CLK_CAM_RAWA_NR_CLK 3 67201404648SChun-Jie Chen 67301404648SChun-Jie Chen /* CAMSYS_YUVA */ 67401404648SChun-Jie Chen 67501404648SChun-Jie Chen #define CLK_CAM_YUVA_LARBX 0 67601404648SChun-Jie Chen #define CLK_CAM_YUVA_CAM 1 67701404648SChun-Jie Chen #define CLK_CAM_YUVA_CAMTG 2 67801404648SChun-Jie Chen #define CLK_CAM_YUVA_NR_CLK 3 67901404648SChun-Jie Chen 68001404648SChun-Jie Chen /* CAMSYS_RAWB */ 68101404648SChun-Jie Chen 68201404648SChun-Jie Chen #define CLK_CAM_RAWB_LARBX 0 68301404648SChun-Jie Chen #define CLK_CAM_RAWB_CAM 1 68401404648SChun-Jie Chen #define CLK_CAM_RAWB_CAMTG 2 68501404648SChun-Jie Chen #define CLK_CAM_RAWB_NR_CLK 3 68601404648SChun-Jie Chen 68701404648SChun-Jie Chen /* CAMSYS_YUVB */ 68801404648SChun-Jie Chen 68901404648SChun-Jie Chen #define CLK_CAM_YUVB_LARBX 0 69001404648SChun-Jie Chen #define CLK_CAM_YUVB_CAM 1 69101404648SChun-Jie Chen #define CLK_CAM_YUVB_CAMTG 2 69201404648SChun-Jie Chen #define CLK_CAM_YUVB_NR_CLK 3 69301404648SChun-Jie Chen 69401404648SChun-Jie Chen /* CAMSYS_MRAW */ 69501404648SChun-Jie Chen 69601404648SChun-Jie Chen #define CLK_CAM_MRAW_LARBX 0 69701404648SChun-Jie Chen #define CLK_CAM_MRAW_CAMTG 1 69801404648SChun-Jie Chen #define CLK_CAM_MRAW_MRAW0 2 69901404648SChun-Jie Chen #define CLK_CAM_MRAW_MRAW1 3 70001404648SChun-Jie Chen #define CLK_CAM_MRAW_MRAW2 4 70101404648SChun-Jie Chen #define CLK_CAM_MRAW_MRAW3 5 70201404648SChun-Jie Chen #define CLK_CAM_MRAW_NR_CLK 6 70301404648SChun-Jie Chen 70401404648SChun-Jie Chen /* CCUSYS */ 70501404648SChun-Jie Chen 70601404648SChun-Jie Chen #define CLK_CCU_LARB18 0 70701404648SChun-Jie Chen #define CLK_CCU_AHB 1 70801404648SChun-Jie Chen #define CLK_CCU_CCU0 2 70901404648SChun-Jie Chen #define CLK_CCU_CCU1 3 71001404648SChun-Jie Chen #define CLK_CCU_NR_CLK 4 71101404648SChun-Jie Chen 71201404648SChun-Jie Chen /* VDECSYS_SOC */ 71301404648SChun-Jie Chen 71401404648SChun-Jie Chen #define CLK_VDEC_SOC_LARB1 0 71501404648SChun-Jie Chen #define CLK_VDEC_SOC_LAT 1 71601404648SChun-Jie Chen #define CLK_VDEC_SOC_VDEC 2 71701404648SChun-Jie Chen #define CLK_VDEC_SOC_NR_CLK 3 71801404648SChun-Jie Chen 71901404648SChun-Jie Chen /* VDECSYS */ 72001404648SChun-Jie Chen 72101404648SChun-Jie Chen #define CLK_VDEC_LARB1 0 72201404648SChun-Jie Chen #define CLK_VDEC_LAT 1 72301404648SChun-Jie Chen #define CLK_VDEC_VDEC 2 72401404648SChun-Jie Chen #define CLK_VDEC_NR_CLK 3 72501404648SChun-Jie Chen 72601404648SChun-Jie Chen /* VDECSYS_CORE1 */ 72701404648SChun-Jie Chen 72801404648SChun-Jie Chen #define CLK_VDEC_CORE1_LARB1 0 72901404648SChun-Jie Chen #define CLK_VDEC_CORE1_LAT 1 73001404648SChun-Jie Chen #define CLK_VDEC_CORE1_VDEC 2 73101404648SChun-Jie Chen #define CLK_VDEC_CORE1_NR_CLK 3 73201404648SChun-Jie Chen 73301404648SChun-Jie Chen /* APUSYS_PLL */ 73401404648SChun-Jie Chen 73501404648SChun-Jie Chen #define CLK_APUSYS_PLL_APUPLL 0 73601404648SChun-Jie Chen #define CLK_APUSYS_PLL_NPUPLL 1 73701404648SChun-Jie Chen #define CLK_APUSYS_PLL_APUPLL1 2 73801404648SChun-Jie Chen #define CLK_APUSYS_PLL_APUPLL2 3 73901404648SChun-Jie Chen #define CLK_APUSYS_PLL_NR_CLK 4 74001404648SChun-Jie Chen 74101404648SChun-Jie Chen /* VENCSYS */ 74201404648SChun-Jie Chen 74301404648SChun-Jie Chen #define CLK_VENC_LARB 0 74401404648SChun-Jie Chen #define CLK_VENC_VENC 1 74501404648SChun-Jie Chen #define CLK_VENC_JPGENC 2 74601404648SChun-Jie Chen #define CLK_VENC_JPGDEC 3 74701404648SChun-Jie Chen #define CLK_VENC_JPGDEC_C1 4 74801404648SChun-Jie Chen #define CLK_VENC_GALS 5 74901404648SChun-Jie Chen #define CLK_VENC_NR_CLK 6 75001404648SChun-Jie Chen 75101404648SChun-Jie Chen /* VENCSYS_CORE1 */ 75201404648SChun-Jie Chen 75301404648SChun-Jie Chen #define CLK_VENC_CORE1_LARB 0 75401404648SChun-Jie Chen #define CLK_VENC_CORE1_VENC 1 75501404648SChun-Jie Chen #define CLK_VENC_CORE1_JPGENC 2 75601404648SChun-Jie Chen #define CLK_VENC_CORE1_JPGDEC 3 75701404648SChun-Jie Chen #define CLK_VENC_CORE1_JPGDEC_C1 4 75801404648SChun-Jie Chen #define CLK_VENC_CORE1_GALS 5 75901404648SChun-Jie Chen #define CLK_VENC_CORE1_NR_CLK 6 76001404648SChun-Jie Chen 76101404648SChun-Jie Chen /* VDOSYS0 */ 76201404648SChun-Jie Chen 76301404648SChun-Jie Chen #define CLK_VDO0_DISP_OVL0 0 76401404648SChun-Jie Chen #define CLK_VDO0_DISP_COLOR0 1 76501404648SChun-Jie Chen #define CLK_VDO0_DISP_COLOR1 2 76601404648SChun-Jie Chen #define CLK_VDO0_DISP_CCORR0 3 76701404648SChun-Jie Chen #define CLK_VDO0_DISP_CCORR1 4 76801404648SChun-Jie Chen #define CLK_VDO0_DISP_AAL0 5 76901404648SChun-Jie Chen #define CLK_VDO0_DISP_AAL1 6 77001404648SChun-Jie Chen #define CLK_VDO0_DISP_GAMMA0 7 77101404648SChun-Jie Chen #define CLK_VDO0_DISP_GAMMA1 8 77201404648SChun-Jie Chen #define CLK_VDO0_DISP_DITHER0 9 77301404648SChun-Jie Chen #define CLK_VDO0_DISP_DITHER1 10 77401404648SChun-Jie Chen #define CLK_VDO0_DISP_OVL1 11 77501404648SChun-Jie Chen #define CLK_VDO0_DISP_WDMA0 12 77601404648SChun-Jie Chen #define CLK_VDO0_DISP_WDMA1 13 77701404648SChun-Jie Chen #define CLK_VDO0_DISP_RDMA0 14 77801404648SChun-Jie Chen #define CLK_VDO0_DISP_RDMA1 15 77901404648SChun-Jie Chen #define CLK_VDO0_DSI0 16 78001404648SChun-Jie Chen #define CLK_VDO0_DSI1 17 78101404648SChun-Jie Chen #define CLK_VDO0_DSC_WRAP0 18 78201404648SChun-Jie Chen #define CLK_VDO0_VPP_MERGE0 19 78301404648SChun-Jie Chen #define CLK_VDO0_DP_INTF0 20 78401404648SChun-Jie Chen #define CLK_VDO0_DISP_MUTEX0 21 78501404648SChun-Jie Chen #define CLK_VDO0_DISP_IL_ROT0 22 78601404648SChun-Jie Chen #define CLK_VDO0_APB_BUS 23 78701404648SChun-Jie Chen #define CLK_VDO0_FAKE_ENG0 24 78801404648SChun-Jie Chen #define CLK_VDO0_FAKE_ENG1 25 78901404648SChun-Jie Chen #define CLK_VDO0_DL_ASYNC0 26 79001404648SChun-Jie Chen #define CLK_VDO0_DL_ASYNC1 27 79101404648SChun-Jie Chen #define CLK_VDO0_DL_ASYNC2 28 79201404648SChun-Jie Chen #define CLK_VDO0_DL_ASYNC3 29 79301404648SChun-Jie Chen #define CLK_VDO0_DL_ASYNC4 30 79401404648SChun-Jie Chen #define CLK_VDO0_DISP_MONITOR0 31 79501404648SChun-Jie Chen #define CLK_VDO0_DISP_MONITOR1 32 79601404648SChun-Jie Chen #define CLK_VDO0_DISP_MONITOR2 33 79701404648SChun-Jie Chen #define CLK_VDO0_DISP_MONITOR3 34 79801404648SChun-Jie Chen #define CLK_VDO0_DISP_MONITOR4 35 79901404648SChun-Jie Chen #define CLK_VDO0_SMI_GALS 36 80001404648SChun-Jie Chen #define CLK_VDO0_SMI_COMMON 37 80101404648SChun-Jie Chen #define CLK_VDO0_SMI_EMI 38 80201404648SChun-Jie Chen #define CLK_VDO0_SMI_IOMMU 39 80301404648SChun-Jie Chen #define CLK_VDO0_SMI_LARB 40 80401404648SChun-Jie Chen #define CLK_VDO0_SMI_RSI 41 80501404648SChun-Jie Chen #define CLK_VDO0_DSI0_DSI 42 80601404648SChun-Jie Chen #define CLK_VDO0_DSI1_DSI 43 80701404648SChun-Jie Chen #define CLK_VDO0_DP_INTF0_DP_INTF 44 80801404648SChun-Jie Chen #define CLK_VDO0_NR_CLK 45 80901404648SChun-Jie Chen 81001404648SChun-Jie Chen /* VDOSYS1 */ 81101404648SChun-Jie Chen 81201404648SChun-Jie Chen #define CLK_VDO1_SMI_LARB2 0 81301404648SChun-Jie Chen #define CLK_VDO1_SMI_LARB3 1 81401404648SChun-Jie Chen #define CLK_VDO1_GALS 2 81501404648SChun-Jie Chen #define CLK_VDO1_FAKE_ENG0 3 81601404648SChun-Jie Chen #define CLK_VDO1_FAKE_ENG 4 81701404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA0 5 81801404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA1 6 81901404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA2 7 82001404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA3 8 82101404648SChun-Jie Chen #define CLK_VDO1_VPP_MERGE0 9 82201404648SChun-Jie Chen #define CLK_VDO1_VPP_MERGE1 10 82301404648SChun-Jie Chen #define CLK_VDO1_VPP_MERGE2 11 82401404648SChun-Jie Chen #define CLK_VDO1_VPP_MERGE3 12 82501404648SChun-Jie Chen #define CLK_VDO1_VPP_MERGE4 13 82601404648SChun-Jie Chen #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 82701404648SChun-Jie Chen #define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15 82801404648SChun-Jie Chen #define CLK_VDO1_DISP_MUTEX 16 82901404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA4 17 83001404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA5 18 83101404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA6 19 83201404648SChun-Jie Chen #define CLK_VDO1_MDP_RDMA7 20 83301404648SChun-Jie Chen #define CLK_VDO1_DP_INTF0_MM 21 83401404648SChun-Jie Chen #define CLK_VDO1_DPI0_MM 22 83501404648SChun-Jie Chen #define CLK_VDO1_DPI1_MM 23 83601404648SChun-Jie Chen #define CLK_VDO1_DISP_MONITOR 24 83701404648SChun-Jie Chen #define CLK_VDO1_MERGE0_DL_ASYNC 25 83801404648SChun-Jie Chen #define CLK_VDO1_MERGE1_DL_ASYNC 26 83901404648SChun-Jie Chen #define CLK_VDO1_MERGE2_DL_ASYNC 27 84001404648SChun-Jie Chen #define CLK_VDO1_MERGE3_DL_ASYNC 28 84101404648SChun-Jie Chen #define CLK_VDO1_MERGE4_DL_ASYNC 29 84201404648SChun-Jie Chen #define CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC 30 84301404648SChun-Jie Chen #define CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 84401404648SChun-Jie Chen #define CLK_VDO1_HDR_VDO_FE0 32 84501404648SChun-Jie Chen #define CLK_VDO1_HDR_GFX_FE0 33 84601404648SChun-Jie Chen #define CLK_VDO1_HDR_VDO_BE 34 84701404648SChun-Jie Chen #define CLK_VDO1_HDR_VDO_FE1 35 84801404648SChun-Jie Chen #define CLK_VDO1_HDR_GFX_FE1 36 84901404648SChun-Jie Chen #define CLK_VDO1_DISP_MIXER 37 85001404648SChun-Jie Chen #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38 85101404648SChun-Jie Chen #define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 39 85201404648SChun-Jie Chen #define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 40 85301404648SChun-Jie Chen #define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41 85401404648SChun-Jie Chen #define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 42 85501404648SChun-Jie Chen #define CLK_VDO1_DPI0 43 85601404648SChun-Jie Chen #define CLK_VDO1_DISP_MONITOR_DPI0 44 85701404648SChun-Jie Chen #define CLK_VDO1_DPI1 45 85801404648SChun-Jie Chen #define CLK_VDO1_DISP_MONITOR_DPI1 46 85901404648SChun-Jie Chen #define CLK_VDO1_DPINTF 47 86001404648SChun-Jie Chen #define CLK_VDO1_DISP_MONITOR_DPINTF 48 86101404648SChun-Jie Chen #define CLK_VDO1_26M_SLOW 49 862*879b752bSPablo Sun #define CLK_VDO1_DPI1_HDMI 50 863*879b752bSPablo Sun #define CLK_VDO1_NR_CLK 51 864*879b752bSPablo Sun 86501404648SChun-Jie Chen 86601404648SChun-Jie Chen #endif /* _DT_BINDINGS_CLK_MT8195_H */ 867