124db8c91SSandeep Tripathy /* 224db8c91SSandeep Tripathy * BSD LICENSE 324db8c91SSandeep Tripathy * 424db8c91SSandeep Tripathy * Copyright(c) 2017 Broadcom. All rights reserved. 524db8c91SSandeep Tripathy * 624db8c91SSandeep Tripathy * Redistribution and use in source and binary forms, with or without 724db8c91SSandeep Tripathy * modification, are permitted provided that the following conditions 824db8c91SSandeep Tripathy * are met: 924db8c91SSandeep Tripathy * 1024db8c91SSandeep Tripathy * * Redistributions of source code must retain the above copyright 1124db8c91SSandeep Tripathy * notice, this list of conditions and the following disclaimer. 1224db8c91SSandeep Tripathy * * Redistributions in binary form must reproduce the above copyright 1324db8c91SSandeep Tripathy * notice, this list of conditions and the following disclaimer in 1424db8c91SSandeep Tripathy * the documentation and/or other materials provided with the 1524db8c91SSandeep Tripathy * distribution. 1624db8c91SSandeep Tripathy * * Neither the name of Broadcom Corporation nor the names of its 1724db8c91SSandeep Tripathy * contributors may be used to endorse or promote products derived 1824db8c91SSandeep Tripathy * from this software without specific prior written permission. 1924db8c91SSandeep Tripathy * 2024db8c91SSandeep Tripathy * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2124db8c91SSandeep Tripathy * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2224db8c91SSandeep Tripathy * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2324db8c91SSandeep Tripathy * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2424db8c91SSandeep Tripathy * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2524db8c91SSandeep Tripathy * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2624db8c91SSandeep Tripathy * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2724db8c91SSandeep Tripathy * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2824db8c91SSandeep Tripathy * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2924db8c91SSandeep Tripathy * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3024db8c91SSandeep Tripathy * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3124db8c91SSandeep Tripathy */ 3224db8c91SSandeep Tripathy 3324db8c91SSandeep Tripathy #ifndef _CLOCK_BCM_SR_H 3424db8c91SSandeep Tripathy #define _CLOCK_BCM_SR_H 3524db8c91SSandeep Tripathy 3624db8c91SSandeep Tripathy /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ 3724db8c91SSandeep Tripathy #define BCM_SR_GENPLL0 0 3848bf9a52SPramod Kumar #define BCM_SR_GENPLL0_125M_CLK 1 3924db8c91SSandeep Tripathy #define BCM_SR_GENPLL0_SCR_CLK 2 4024db8c91SSandeep Tripathy #define BCM_SR_GENPLL0_250M_CLK 3 4124db8c91SSandeep Tripathy #define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 4224db8c91SSandeep Tripathy #define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 5 4324db8c91SSandeep Tripathy #define BCM_SR_GENPLL0_PAXC_AXI_CLK 6 4424db8c91SSandeep Tripathy 4524db8c91SSandeep Tripathy /* GENPLL 1 clock channel ID MHB PCIE NITRO */ 4624db8c91SSandeep Tripathy #define BCM_SR_GENPLL1 0 4724db8c91SSandeep Tripathy #define BCM_SR_GENPLL1_PCIE_TL_CLK 1 4824db8c91SSandeep Tripathy #define BCM_SR_GENPLL1_MHB_APB_CLK 2 4924db8c91SSandeep Tripathy 5024db8c91SSandeep Tripathy /* GENPLL 2 clock channel ID NITRO MHB*/ 5124db8c91SSandeep Tripathy #define BCM_SR_GENPLL2 0 5224db8c91SSandeep Tripathy #define BCM_SR_GENPLL2_NIC_CLK 1 5348bf9a52SPramod Kumar #define BCM_SR_GENPLL2_TS_500_CLK 2 5424db8c91SSandeep Tripathy #define BCM_SR_GENPLL2_125_NITRO_CLK 3 5524db8c91SSandeep Tripathy #define BCM_SR_GENPLL2_CHIMP_CLK 4 5648bf9a52SPramod Kumar #define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 5748bf9a52SPramod Kumar #define BCM_SR_GENPLL2_FS4_CLK 6 5824db8c91SSandeep Tripathy 5924db8c91SSandeep Tripathy /* GENPLL 3 HSLS clock channel ID */ 6024db8c91SSandeep Tripathy #define BCM_SR_GENPLL3 0 6124db8c91SSandeep Tripathy #define BCM_SR_GENPLL3_HSLS_CLK 1 6224db8c91SSandeep Tripathy #define BCM_SR_GENPLL3_SDIO_CLK 2 6324db8c91SSandeep Tripathy 6424db8c91SSandeep Tripathy /* GENPLL 4 SCR clock channel ID */ 6524db8c91SSandeep Tripathy #define BCM_SR_GENPLL4 0 6624db8c91SSandeep Tripathy #define BCM_SR_GENPLL4_CCN_CLK 1 6748bf9a52SPramod Kumar #define BCM_SR_GENPLL4_TPIU_PLL_CLK 2 6848bf9a52SPramod Kumar #define BCM_SR_GENPLL4_NOC_CLK 3 6948bf9a52SPramod Kumar #define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4 7048bf9a52SPramod Kumar #define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5 7124db8c91SSandeep Tripathy 7224db8c91SSandeep Tripathy /* GENPLL 5 FS4 clock channel ID */ 7324db8c91SSandeep Tripathy #define BCM_SR_GENPLL5 0 7448bf9a52SPramod Kumar #define BCM_SR_GENPLL5_FS4_HF_CLK 1 7548bf9a52SPramod Kumar #define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2 7648bf9a52SPramod Kumar #define BCM_SR_GENPLL5_RAID_AE_CLK 3 7724db8c91SSandeep Tripathy 7824db8c91SSandeep Tripathy /* GENPLL 6 NITRO clock channel ID */ 7924db8c91SSandeep Tripathy #define BCM_SR_GENPLL6 0 8024db8c91SSandeep Tripathy #define BCM_SR_GENPLL6_48_USB_CLK 1 8124db8c91SSandeep Tripathy 8224db8c91SSandeep Tripathy /* LCPLL0 clock channel ID */ 8324db8c91SSandeep Tripathy #define BCM_SR_LCPLL0 0 8448bf9a52SPramod Kumar #define BCM_SR_LCPLL0_SATA_REFP_CLK 1 8548bf9a52SPramod Kumar #define BCM_SR_LCPLL0_SATA_REFN_CLK 2 8648bf9a52SPramod Kumar #define BCM_SR_LCPLL0_SATA_350_CLK 3 8748bf9a52SPramod Kumar #define BCM_SR_LCPLL0_SATA_500_CLK 4 8824db8c91SSandeep Tripathy 8924db8c91SSandeep Tripathy /* LCPLL1 clock channel ID */ 9024db8c91SSandeep Tripathy #define BCM_SR_LCPLL1 0 9124db8c91SSandeep Tripathy #define BCM_SR_LCPLL1_WAN_CLK 1 9248bf9a52SPramod Kumar #define BCM_SR_LCPLL1_USB_REF_CLK 2 9348bf9a52SPramod Kumar #define BCM_SR_LCPLL1_CRMU_TS_CLK 3 9424db8c91SSandeep Tripathy 9524db8c91SSandeep Tripathy /* LCPLL PCIE clock channel ID */ 9624db8c91SSandeep Tripathy #define BCM_SR_LCPLL_PCIE 0 9724db8c91SSandeep Tripathy #define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 1 9824db8c91SSandeep Tripathy 9924db8c91SSandeep Tripathy /* GENPLL EMEM0 clock channel ID */ 10024db8c91SSandeep Tripathy #define BCM_SR_EMEMPLL0 0 10124db8c91SSandeep Tripathy #define BCM_SR_EMEMPLL0_EMEM_CLK 1 10224db8c91SSandeep Tripathy 10324db8c91SSandeep Tripathy /* GENPLL EMEM0 clock channel ID */ 10424db8c91SSandeep Tripathy #define BCM_SR_EMEMPLL1 0 10524db8c91SSandeep Tripathy #define BCM_SR_EMEMPLL1_EMEM_CLK 1 10624db8c91SSandeep Tripathy 10724db8c91SSandeep Tripathy /* GENPLL EMEM0 clock channel ID */ 10824db8c91SSandeep Tripathy #define BCM_SR_EMEMPLL2 0 10924db8c91SSandeep Tripathy #define BCM_SR_EMEMPLL2_EMEM_CLK 1 11024db8c91SSandeep Tripathy 11124db8c91SSandeep Tripathy #endif /* _CLOCK_BCM_SR_H */ 112