1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 14 15/ { 16 compatible = "toshiba,tmpv7708"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x81100000>; 61 reg = <0x00>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x0 0x81100000>; 69 reg = <0x01>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x0 0x81100000>; 77 reg = <0x02>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53"; 82 device_type = "cpu"; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0x0 0x81100000>; 85 reg = <0x03>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 cpu-release-addr = <0x0 0x81100000>; 93 reg = <0x100>; 94 }; 95 96 cpu5: cpu@101 { 97 compatible = "arm,cortex-a53"; 98 device_type = "cpu"; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0x0 0x81100000>; 101 reg = <0x101>; 102 }; 103 104 cpu6: cpu@102 { 105 compatible = "arm,cortex-a53"; 106 device_type = "cpu"; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0x0 0x81100000>; 109 reg = <0x102>; 110 }; 111 112 cpu7: cpu@103 { 113 compatible = "arm,cortex-a53"; 114 device_type = "cpu"; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0x0 0x81100000>; 117 reg = <0x103>; 118 }; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupt-parent = <&gic>; 124 interrupts = 125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 uart_clk: uart-clk { 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 #clock-cells = <0>; 135 }; 136 137 clk125mhz: clk125mhz { 138 compatible = "fixed-clock"; 139 clock-frequency = <125000000>; 140 #clock-cells = <0>; 141 clock-output-names = "clk125mhz"; 142 }; 143 144 clk300mhz: clk300mhz { 145 compatible = "fixed-clock"; 146 clock-frequency = <300000000>; 147 #clock-cells = <0>; 148 clock-output-names = "clk300mhz"; 149 }; 150 151 soc { 152 #address-cells = <2>; 153 #size-cells = <2>; 154 compatible = "simple-bus"; 155 interrupt-parent = <&gic>; 156 ranges; 157 158 gic: interrupt-controller@24001000 { 159 compatible = "arm,gic-400"; 160 interrupt-controller; 161 #interrupt-cells = <3>; 162 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 163 reg = <0 0x24001000 0 0x1000>, 164 <0 0x24002000 0 0x2000>, 165 <0 0x24004000 0 0x2000>, 166 <0 0x24006000 0 0x2000>; 167 }; 168 169 pmux: pmux@24190000 { 170 compatible = "toshiba,tmpv7708-pinctrl"; 171 reg = <0 0x24190000 0 0x10000>; 172 }; 173 174 uart0: serial@28200000 { 175 compatible = "arm,pl011", "arm,primecell"; 176 reg = <0 0x28200000 0 0x1000>; 177 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&uart0_pins>; 180 status = "disabled"; 181 }; 182 183 uart1: serial@28201000 { 184 compatible = "arm,pl011", "arm,primecell"; 185 reg = <0 0x28201000 0 0x1000>; 186 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&uart1_pins>; 189 status = "disabled"; 190 }; 191 192 uart2: serial@28202000 { 193 compatible = "arm,pl011", "arm,primecell"; 194 reg = <0 0x28202000 0 0x1000>; 195 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&uart2_pins>; 198 status = "disabled"; 199 }; 200 201 uart3: serial@28203000 { 202 compatible = "arm,pl011", "arm,primecell"; 203 reg = <0 0x28203000 0 0x1000>; 204 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&uart3_pins>; 207 status = "disabled"; 208 }; 209 210 i2c0: i2c@28030000 { 211 compatible = "snps,designware-i2c"; 212 reg = <0 0x28030000 0 0x1000>; 213 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&i2c0_pins>; 216 clock-frequency = <400000>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 status = "disabled"; 220 }; 221 222 i2c1: i2c@28031000 { 223 compatible = "snps,designware-i2c"; 224 reg = <0 0x28031000 0 0x1000>; 225 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&i2c1_pins>; 228 clock-frequency = <400000>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 status = "disabled"; 232 }; 233 234 i2c2: i2c@28032000 { 235 compatible = "snps,designware-i2c"; 236 reg = <0 0x28032000 0 0x1000>; 237 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&i2c2_pins>; 240 clock-frequency = <400000>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 246 i2c3: i2c@28033000 { 247 compatible = "snps,designware-i2c"; 248 reg = <0 0x28033000 0 0x1000>; 249 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&i2c3_pins>; 252 clock-frequency = <400000>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 i2c4: i2c@28034000 { 259 compatible = "snps,designware-i2c"; 260 reg = <0 0x28034000 0 0x1000>; 261 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&i2c4_pins>; 264 clock-frequency = <400000>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 status = "disabled"; 268 }; 269 270 i2c5: i2c@28035000 { 271 compatible = "snps,designware-i2c"; 272 reg = <0 0x28035000 0 0x1000>; 273 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&i2c5_pins>; 276 clock-frequency = <400000>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 i2c6: i2c@28036000 { 283 compatible = "snps,designware-i2c"; 284 reg = <0 0x28036000 0 0x1000>; 285 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&i2c6_pins>; 288 clock-frequency = <400000>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 status = "disabled"; 292 }; 293 294 i2c7: i2c@28037000 { 295 compatible = "snps,designware-i2c"; 296 reg = <0 0x28037000 0 0x1000>; 297 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&i2c7_pins>; 300 clock-frequency = <400000>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 i2c8: i2c@28038000 { 307 compatible = "snps,designware-i2c"; 308 reg = <0 0x28038000 0 0x1000>; 309 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2c8_pins>; 312 clock-frequency = <400000>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 spi0: spi@28140000 { 319 compatible = "arm,pl022", "arm,primecell"; 320 reg = <0 0x28140000 0 0x1000>; 321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&spi0_pins>; 324 num-cs = <1>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 spi1: spi@28141000 { 331 compatible = "arm,pl022", "arm,primecell"; 332 reg = <0 0x28141000 0 0x1000>; 333 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&spi1_pins>; 336 num-cs = <1>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 status = "disabled"; 340 }; 341 342 spi2: spi@28142000 { 343 compatible = "arm,pl022", "arm,primecell"; 344 reg = <0 0x28142000 0 0x1000>; 345 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&spi2_pins>; 348 num-cs = <1>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 }; 353 354 spi3: spi@28143000 { 355 compatible = "arm,pl022", "arm,primecell"; 356 reg = <0 0x28143000 0 0x1000>; 357 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&spi3_pins>; 360 num-cs = <1>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 spi4: spi@28144000 { 367 compatible = "arm,pl022", "arm,primecell"; 368 reg = <0 0x28144000 0 0x1000>; 369 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&spi4_pins>; 372 num-cs = <1>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 spi5: spi@28145000 { 379 compatible = "arm,pl022", "arm,primecell"; 380 reg = <0 0x28145000 0 0x1000>; 381 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&spi5_pins>; 384 num-cs = <1>; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 status = "disabled"; 388 }; 389 390 spi6: spi@28146000 { 391 compatible = "arm,pl022", "arm,primecell"; 392 reg = <0 0x28146000 0 0x1000>; 393 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&spi6_pins>; 396 num-cs = <1>; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 status = "disabled"; 400 }; 401 402 piether: ethernet@28000000 { 403 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 404 reg = <0 0x28000000 0 0x10000>; 405 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "macirq"; 407 snps,txpbl = <4>; 408 snps,rxpbl = <4>; 409 snps,tso; 410 status = "disabled"; 411 }; 412 }; 413}; 414 415#include "tmpv7708_pins.dtsi" 416