1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 14 15/ { 16 compatible = "toshiba,tmpv7708"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x81100000>; 61 reg = <0x00>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x0 0x81100000>; 69 reg = <0x01>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x0 0x81100000>; 77 reg = <0x02>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53"; 82 device_type = "cpu"; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0x0 0x81100000>; 85 reg = <0x03>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 cpu-release-addr = <0x0 0x81100000>; 93 reg = <0x100>; 94 }; 95 96 cpu5: cpu@101 { 97 compatible = "arm,cortex-a53"; 98 device_type = "cpu"; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0x0 0x81100000>; 101 reg = <0x101>; 102 }; 103 104 cpu6: cpu@102 { 105 compatible = "arm,cortex-a53"; 106 device_type = "cpu"; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0x0 0x81100000>; 109 reg = <0x102>; 110 }; 111 112 cpu7: cpu@103 { 113 compatible = "arm,cortex-a53"; 114 device_type = "cpu"; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0x0 0x81100000>; 117 reg = <0x103>; 118 }; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupt-parent = <&gic>; 124 interrupts = 125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 uart_clk: uart-clk { 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 #clock-cells = <0>; 135 }; 136 137 soc { 138 #address-cells = <2>; 139 #size-cells = <2>; 140 compatible = "simple-bus"; 141 interrupt-parent = <&gic>; 142 ranges; 143 144 gic: interrupt-controller@24001000 { 145 compatible = "arm,gic-400"; 146 interrupt-controller; 147 #interrupt-cells = <3>; 148 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 149 reg = <0 0x24001000 0 0x1000>, 150 <0 0x24002000 0 0x2000>, 151 <0 0x24004000 0 0x2000>, 152 <0 0x24006000 0 0x2000>; 153 }; 154 155 pmux: pmux@24190000 { 156 compatible = "toshiba,tmpv7708-pinctrl"; 157 reg = <0 0x24190000 0 0x10000>; 158 }; 159 160 gpio: gpio@28020000 { 161 compatible = "toshiba,gpio-tmpv7708"; 162 reg = <0 0x28020000 0 0x1000>; 163 #gpio-cells = <0x2>; 164 gpio-ranges = <&pmux 0 0 32>; 165 gpio-controller; 166 interrupt-controller; 167 #interrupt-cells = <2>; 168 interrupt-parent = <&gic>; 169 }; 170 171 uart0: serial@28200000 { 172 compatible = "arm,pl011", "arm,primecell"; 173 reg = <0 0x28200000 0 0x1000>; 174 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&uart0_pins>; 177 status = "disabled"; 178 }; 179 180 uart1: serial@28201000 { 181 compatible = "arm,pl011", "arm,primecell"; 182 reg = <0 0x28201000 0 0x1000>; 183 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&uart1_pins>; 186 status = "disabled"; 187 }; 188 189 uart2: serial@28202000 { 190 compatible = "arm,pl011", "arm,primecell"; 191 reg = <0 0x28202000 0 0x1000>; 192 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&uart2_pins>; 195 status = "disabled"; 196 }; 197 198 uart3: serial@28203000 { 199 compatible = "arm,pl011", "arm,primecell"; 200 reg = <0 0x28203000 0 0x1000>; 201 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&uart3_pins>; 204 status = "disabled"; 205 }; 206 207 i2c0: i2c@28030000 { 208 compatible = "snps,designware-i2c"; 209 reg = <0 0x28030000 0 0x1000>; 210 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&i2c0_pins>; 213 clock-frequency = <400000>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 status = "disabled"; 217 }; 218 219 i2c1: i2c@28031000 { 220 compatible = "snps,designware-i2c"; 221 reg = <0 0x28031000 0 0x1000>; 222 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&i2c1_pins>; 225 clock-frequency = <400000>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 status = "disabled"; 229 }; 230 231 i2c2: i2c@28032000 { 232 compatible = "snps,designware-i2c"; 233 reg = <0 0x28032000 0 0x1000>; 234 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&i2c2_pins>; 237 clock-frequency = <400000>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c3: i2c@28033000 { 244 compatible = "snps,designware-i2c"; 245 reg = <0 0x28033000 0 0x1000>; 246 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&i2c3_pins>; 249 clock-frequency = <400000>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 status = "disabled"; 253 }; 254 255 i2c4: i2c@28034000 { 256 compatible = "snps,designware-i2c"; 257 reg = <0 0x28034000 0 0x1000>; 258 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&i2c4_pins>; 261 clock-frequency = <400000>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 status = "disabled"; 265 }; 266 267 i2c5: i2c@28035000 { 268 compatible = "snps,designware-i2c"; 269 reg = <0 0x28035000 0 0x1000>; 270 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&i2c5_pins>; 273 clock-frequency = <400000>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 status = "disabled"; 277 }; 278 279 i2c6: i2c@28036000 { 280 compatible = "snps,designware-i2c"; 281 reg = <0 0x28036000 0 0x1000>; 282 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&i2c6_pins>; 285 clock-frequency = <400000>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 status = "disabled"; 289 }; 290 291 i2c7: i2c@28037000 { 292 compatible = "snps,designware-i2c"; 293 reg = <0 0x28037000 0 0x1000>; 294 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c7_pins>; 297 clock-frequency = <400000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 i2c8: i2c@28038000 { 304 compatible = "snps,designware-i2c"; 305 reg = <0 0x28038000 0 0x1000>; 306 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c8_pins>; 309 clock-frequency = <400000>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 spi0: spi@28140000 { 316 compatible = "arm,pl022", "arm,primecell"; 317 reg = <0 0x28140000 0 0x1000>; 318 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&spi0_pins>; 321 num-cs = <1>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 spi1: spi@28141000 { 328 compatible = "arm,pl022", "arm,primecell"; 329 reg = <0 0x28141000 0 0x1000>; 330 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&spi1_pins>; 333 num-cs = <1>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 spi2: spi@28142000 { 340 compatible = "arm,pl022", "arm,primecell"; 341 reg = <0 0x28142000 0 0x1000>; 342 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&spi2_pins>; 345 num-cs = <1>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 spi3: spi@28143000 { 352 compatible = "arm,pl022", "arm,primecell"; 353 reg = <0 0x28143000 0 0x1000>; 354 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&spi3_pins>; 357 num-cs = <1>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 spi4: spi@28144000 { 364 compatible = "arm,pl022", "arm,primecell"; 365 reg = <0 0x28144000 0 0x1000>; 366 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&spi4_pins>; 369 num-cs = <1>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 spi5: spi@28145000 { 376 compatible = "arm,pl022", "arm,primecell"; 377 reg = <0 0x28145000 0 0x1000>; 378 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&spi5_pins>; 381 num-cs = <1>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 status = "disabled"; 385 }; 386 387 spi6: spi@28146000 { 388 compatible = "arm,pl022", "arm,primecell"; 389 reg = <0 0x28146000 0 0x1000>; 390 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&spi6_pins>; 393 num-cs = <1>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 status = "disabled"; 397 }; 398 }; 399}; 400 401#include "tmpv7708_pins.dtsi" 402