1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/clock/toshiba,tmpv770x.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 15 16/ { 17 compatible = "toshiba,tmpv7708"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0x0 0x81100000>; 62 reg = <0x00>; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x0 0x81100000>; 70 reg = <0x01>; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x0 0x81100000>; 78 reg = <0x02>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0x0 0x81100000>; 86 reg = <0x03>; 87 }; 88 89 cpu4: cpu@100 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x0 0x81100000>; 94 reg = <0x100>; 95 }; 96 97 cpu5: cpu@101 { 98 compatible = "arm,cortex-a53"; 99 device_type = "cpu"; 100 enable-method = "spin-table"; 101 cpu-release-addr = <0x0 0x81100000>; 102 reg = <0x101>; 103 }; 104 105 cpu6: cpu@102 { 106 compatible = "arm,cortex-a53"; 107 device_type = "cpu"; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0x0 0x81100000>; 110 reg = <0x102>; 111 }; 112 113 cpu7: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 device_type = "cpu"; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0x0 0x81100000>; 118 reg = <0x103>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&gic>; 125 interrupts = 126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 clk25mhz: clk25mhz { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <25000000>; 136 clock-output-names = "clk25mhz"; 137 }; 138 139 clk600mhz: clk600mhz { 140 compatible = "fixed-clock"; 141 #clock-cells = <0>; 142 clock-frequency = <600000000>; 143 clock-output-names = "clk600mhz"; 144 }; 145 146 extclk100mhz: extclk100mhz { 147 compatible = "fixed-clock"; 148 #clock-cells = <0>; 149 clock-frequency = <100000000>; 150 clock-output-names = "extclk100mhz"; 151 }; 152 153 osc2_clk: osc2-clk { 154 compatible = "fixed-clock"; 155 clock-frequency = <20000000>; 156 #clock-cells = <0>; 157 }; 158 159 soc { 160 #address-cells = <2>; 161 #size-cells = <2>; 162 compatible = "simple-bus"; 163 interrupt-parent = <&gic>; 164 ranges; 165 166 gic: interrupt-controller@24001000 { 167 compatible = "arm,gic-400"; 168 interrupt-controller; 169 #interrupt-cells = <3>; 170 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 171 reg = <0 0x24001000 0 0x1000>, 172 <0 0x24002000 0 0x2000>, 173 <0 0x24004000 0 0x2000>, 174 <0 0x24006000 0 0x2000>; 175 }; 176 177 pmux: pmux@24190000 { 178 compatible = "toshiba,tmpv7708-pinctrl"; 179 reg = <0 0x24190000 0 0x10000>; 180 }; 181 182 gpio: gpio@28020000 { 183 compatible = "toshiba,gpio-tmpv7708"; 184 reg = <0 0x28020000 0 0x1000>; 185 #gpio-cells = <0x2>; 186 gpio-ranges = <&pmux 0 0 32>; 187 gpio-controller; 188 interrupt-controller; 189 #interrupt-cells = <2>; 190 interrupt-parent = <&gic>; 191 }; 192 193 pipllct: clock-controller@24220000 { 194 compatible = "toshiba,tmpv7708-pipllct"; 195 reg = <0 0x24220000 0 0x820>; 196 #clock-cells = <1>; 197 clocks = <&osc2_clk>; 198 }; 199 200 pismu: syscon@24200000 { 201 compatible = "toshiba,tmpv7708-pismu", "syscon"; 202 reg = <0 0x24200000 0 0x2140>; 203 #clock-cells = <1>; 204 #reset-cells = <1>; 205 }; 206 207 uart0: serial@28200000 { 208 compatible = "arm,pl011", "arm,primecell"; 209 reg = <0 0x28200000 0 0x1000>; 210 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&uart0_pins>; 213 clocks = <&pismu TMPV770X_CLK_PIUART0>; 214 clock-names = "apb_pclk"; 215 status = "disabled"; 216 }; 217 218 uart1: serial@28201000 { 219 compatible = "arm,pl011", "arm,primecell"; 220 reg = <0 0x28201000 0 0x1000>; 221 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&uart1_pins>; 224 clocks = <&pismu TMPV770X_CLK_PIUART1>; 225 clock-names = "apb_pclk"; 226 status = "disabled"; 227 }; 228 229 uart2: serial@28202000 { 230 compatible = "arm,pl011", "arm,primecell"; 231 reg = <0 0x28202000 0 0x1000>; 232 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&uart2_pins>; 235 clocks = <&pismu TMPV770X_CLK_PIUART2>; 236 clock-names = "apb_pclk"; 237 status = "disabled"; 238 }; 239 240 uart3: serial@28203000 { 241 compatible = "arm,pl011", "arm,primecell"; 242 reg = <0 0x28203000 0 0x1000>; 243 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&uart3_pins>; 246 clocks = <&pismu TMPV770X_CLK_PIUART2>; 247 clock-names = "apb_pclk"; 248 status = "disabled"; 249 }; 250 251 i2c0: i2c@28030000 { 252 compatible = "snps,designware-i2c"; 253 reg = <0 0x28030000 0 0x1000>; 254 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&i2c0_pins>; 257 clock-frequency = <400000>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 clocks = <&pismu TMPV770X_CLK_PII2C0>; 261 status = "disabled"; 262 }; 263 264 i2c1: i2c@28031000 { 265 compatible = "snps,designware-i2c"; 266 reg = <0 0x28031000 0 0x1000>; 267 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&i2c1_pins>; 270 clock-frequency = <400000>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 clocks = <&pismu TMPV770X_CLK_PII2C1>; 274 status = "disabled"; 275 }; 276 277 i2c2: i2c@28032000 { 278 compatible = "snps,designware-i2c"; 279 reg = <0 0x28032000 0 0x1000>; 280 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&i2c2_pins>; 283 clock-frequency = <400000>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&pismu TMPV770X_CLK_PII2C2>; 287 status = "disabled"; 288 }; 289 290 i2c3: i2c@28033000 { 291 compatible = "snps,designware-i2c"; 292 reg = <0 0x28033000 0 0x1000>; 293 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&i2c3_pins>; 296 clock-frequency = <400000>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 clocks = <&pismu TMPV770X_CLK_PII2C3>; 300 status = "disabled"; 301 }; 302 303 i2c4: i2c@28034000 { 304 compatible = "snps,designware-i2c"; 305 reg = <0 0x28034000 0 0x1000>; 306 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&i2c4_pins>; 309 clock-frequency = <400000>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 clocks = <&pismu TMPV770X_CLK_PII2C4>; 313 status = "disabled"; 314 }; 315 316 i2c5: i2c@28035000 { 317 compatible = "snps,designware-i2c"; 318 reg = <0 0x28035000 0 0x1000>; 319 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&i2c5_pins>; 322 clock-frequency = <400000>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clocks = <&pismu TMPV770X_CLK_PII2C5>; 326 status = "disabled"; 327 }; 328 329 i2c6: i2c@28036000 { 330 compatible = "snps,designware-i2c"; 331 reg = <0 0x28036000 0 0x1000>; 332 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&i2c6_pins>; 335 clock-frequency = <400000>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 clocks = <&pismu TMPV770X_CLK_PII2C6>; 339 status = "disabled"; 340 }; 341 342 i2c7: i2c@28037000 { 343 compatible = "snps,designware-i2c"; 344 reg = <0 0x28037000 0 0x1000>; 345 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&i2c7_pins>; 348 clock-frequency = <400000>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 clocks = <&pismu TMPV770X_CLK_PII2C7>; 352 status = "disabled"; 353 }; 354 355 i2c8: i2c@28038000 { 356 compatible = "snps,designware-i2c"; 357 reg = <0 0x28038000 0 0x1000>; 358 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&i2c8_pins>; 361 clock-frequency = <400000>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 clocks = <&pismu TMPV770X_CLK_PII2C8>; 365 status = "disabled"; 366 }; 367 368 spi0: spi@28140000 { 369 compatible = "arm,pl022", "arm,primecell"; 370 reg = <0 0x28140000 0 0x1000>; 371 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&spi0_pins>; 374 num-cs = <1>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clocks = <&pismu TMPV770X_CLK_PISPI1>; 378 clock-names = "apb_pclk"; 379 status = "disabled"; 380 }; 381 382 spi1: spi@28141000 { 383 compatible = "arm,pl022", "arm,primecell"; 384 reg = <0 0x28141000 0 0x1000>; 385 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&spi1_pins>; 388 num-cs = <1>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&pismu TMPV770X_CLK_PISPI1>; 392 clock-names = "apb_pclk"; 393 status = "disabled"; 394 }; 395 396 spi2: spi@28142000 { 397 compatible = "arm,pl022", "arm,primecell"; 398 reg = <0 0x28142000 0 0x1000>; 399 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&spi2_pins>; 402 num-cs = <1>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&pismu TMPV770X_CLK_PISPI2>; 406 clock-names = "apb_pclk"; 407 status = "disabled"; 408 }; 409 410 spi3: spi@28143000 { 411 compatible = "arm,pl022", "arm,primecell"; 412 reg = <0 0x28143000 0 0x1000>; 413 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&spi3_pins>; 416 num-cs = <1>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 clocks = <&pismu TMPV770X_CLK_PISPI3>; 420 clock-names = "apb_pclk"; 421 status = "disabled"; 422 }; 423 424 spi4: spi@28144000 { 425 compatible = "arm,pl022", "arm,primecell"; 426 reg = <0 0x28144000 0 0x1000>; 427 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&spi4_pins>; 430 num-cs = <1>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 clocks = <&pismu TMPV770X_CLK_PISPI4>; 434 clock-names = "apb_pclk"; 435 status = "disabled"; 436 }; 437 438 spi5: spi@28145000 { 439 compatible = "arm,pl022", "arm,primecell"; 440 reg = <0 0x28145000 0 0x1000>; 441 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&spi5_pins>; 444 num-cs = <1>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&pismu TMPV770X_CLK_PISPI5>; 448 clock-names = "apb_pclk"; 449 status = "disabled"; 450 }; 451 452 spi6: spi@28146000 { 453 compatible = "arm,pl022", "arm,primecell"; 454 reg = <0 0x28146000 0 0x1000>; 455 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&spi6_pins>; 458 num-cs = <1>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clocks = <&pismu TMPV770X_CLK_PISPI6>; 462 clock-names = "apb_pclk"; 463 status = "disabled"; 464 }; 465 466 piether: ethernet@28000000 { 467 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 468 reg = <0 0x28000000 0 0x10000>; 469 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 470 interrupt-names = "macirq"; 471 snps,txpbl = <4>; 472 snps,rxpbl = <4>; 473 snps,tso; 474 clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>; 475 clock-names = "stmmaceth", "phy_ref_clk"; 476 status = "disabled"; 477 }; 478 479 wdt: wdt@28330000 { 480 compatible = "toshiba,visconti-wdt"; 481 reg = <0 0x28330000 0 0x1000>; 482 clocks = <&pismu TMPV770X_CLK_WDTCLK>; 483 status = "disabled"; 484 }; 485 486 pwm: pwm@241c0000 { 487 compatible = "toshiba,visconti-pwm"; 488 reg = <0 0x241c0000 0 0x1000>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pwm_mux>; 491 #pwm-cells = <2>; 492 status = "disabled"; 493 }; 494 495 pcie: pcie@28400000 { 496 compatible = "toshiba,visconti-pcie"; 497 reg = <0x0 0x28400000 0x0 0x00400000>, 498 <0x0 0x70000000 0x0 0x10000000>, 499 <0x0 0x28050000 0x0 0x00010000>, 500 <0x0 0x24200000 0x0 0x00002000>, 501 <0x0 0x24162000 0x0 0x00001000>; 502 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 503 device_type = "pci"; 504 bus-range = <0x00 0xff>; 505 num-lanes = <2>; 506 num-viewport = <8>; 507 508 #address-cells = <3>; 509 #size-cells = <2>; 510 #interrupt-cells = <1>; 511 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 512 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 513 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 515 interrupt-names = "msi", "intr"; 516 interrupt-map-mask = <0 0 0 7>; 517 interrupt-map = 518 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 519 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 520 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 521 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 522 max-link-speed = <2>; 523 status = "disabled"; 524 }; 525 }; 526}; 527 528#include "tmpv7708_pins.dtsi" 529