1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 14 15/ { 16 compatible = "toshiba,tmpv7708"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x81100000>; 61 reg = <0x00>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x0 0x81100000>; 69 reg = <0x01>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x0 0x81100000>; 77 reg = <0x02>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53"; 82 device_type = "cpu"; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0x0 0x81100000>; 85 reg = <0x03>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 cpu-release-addr = <0x0 0x81100000>; 93 reg = <0x100>; 94 }; 95 96 cpu5: cpu@101 { 97 compatible = "arm,cortex-a53"; 98 device_type = "cpu"; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0x0 0x81100000>; 101 reg = <0x101>; 102 }; 103 104 cpu6: cpu@102 { 105 compatible = "arm,cortex-a53"; 106 device_type = "cpu"; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0x0 0x81100000>; 109 reg = <0x102>; 110 }; 111 112 cpu7: cpu@103 { 113 compatible = "arm,cortex-a53"; 114 device_type = "cpu"; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0x0 0x81100000>; 117 reg = <0x103>; 118 }; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupt-parent = <&gic>; 124 interrupts = 125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 uart_clk: uart-clk { 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 #clock-cells = <0>; 135 }; 136 137 wdt_clk: wdt-clk { 138 compatible = "fixed-clock"; 139 clock-frequency = <150000000>; 140 #clock-cells = <0>; 141 }; 142 143 soc { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 compatible = "simple-bus"; 147 interrupt-parent = <&gic>; 148 ranges; 149 150 gic: interrupt-controller@24001000 { 151 compatible = "arm,gic-400"; 152 interrupt-controller; 153 #interrupt-cells = <3>; 154 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 155 reg = <0 0x24001000 0 0x1000>, 156 <0 0x24002000 0 0x2000>, 157 <0 0x24004000 0 0x2000>, 158 <0 0x24006000 0 0x2000>; 159 }; 160 161 pmux: pmux@24190000 { 162 compatible = "toshiba,tmpv7708-pinctrl"; 163 reg = <0 0x24190000 0 0x10000>; 164 }; 165 166 uart0: serial@28200000 { 167 compatible = "arm,pl011", "arm,primecell"; 168 reg = <0 0x28200000 0 0x1000>; 169 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&uart0_pins>; 172 status = "disabled"; 173 }; 174 175 uart1: serial@28201000 { 176 compatible = "arm,pl011", "arm,primecell"; 177 reg = <0 0x28201000 0 0x1000>; 178 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&uart1_pins>; 181 status = "disabled"; 182 }; 183 184 uart2: serial@28202000 { 185 compatible = "arm,pl011", "arm,primecell"; 186 reg = <0 0x28202000 0 0x1000>; 187 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&uart2_pins>; 190 status = "disabled"; 191 }; 192 193 uart3: serial@28203000 { 194 compatible = "arm,pl011", "arm,primecell"; 195 reg = <0 0x28203000 0 0x1000>; 196 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&uart3_pins>; 199 status = "disabled"; 200 }; 201 202 i2c0: i2c@28030000 { 203 compatible = "snps,designware-i2c"; 204 reg = <0 0x28030000 0 0x1000>; 205 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&i2c0_pins>; 208 clock-frequency = <400000>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 status = "disabled"; 212 }; 213 214 i2c1: i2c@28031000 { 215 compatible = "snps,designware-i2c"; 216 reg = <0 0x28031000 0 0x1000>; 217 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&i2c1_pins>; 220 clock-frequency = <400000>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 226 i2c2: i2c@28032000 { 227 compatible = "snps,designware-i2c"; 228 reg = <0 0x28032000 0 0x1000>; 229 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&i2c2_pins>; 232 clock-frequency = <400000>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 status = "disabled"; 236 }; 237 238 i2c3: i2c@28033000 { 239 compatible = "snps,designware-i2c"; 240 reg = <0 0x28033000 0 0x1000>; 241 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&i2c3_pins>; 244 clock-frequency = <400000>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 status = "disabled"; 248 }; 249 250 i2c4: i2c@28034000 { 251 compatible = "snps,designware-i2c"; 252 reg = <0 0x28034000 0 0x1000>; 253 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&i2c4_pins>; 256 clock-frequency = <400000>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 status = "disabled"; 260 }; 261 262 i2c5: i2c@28035000 { 263 compatible = "snps,designware-i2c"; 264 reg = <0 0x28035000 0 0x1000>; 265 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&i2c5_pins>; 268 clock-frequency = <400000>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 status = "disabled"; 272 }; 273 274 i2c6: i2c@28036000 { 275 compatible = "snps,designware-i2c"; 276 reg = <0 0x28036000 0 0x1000>; 277 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&i2c6_pins>; 280 clock-frequency = <400000>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 status = "disabled"; 284 }; 285 286 i2c7: i2c@28037000 { 287 compatible = "snps,designware-i2c"; 288 reg = <0 0x28037000 0 0x1000>; 289 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&i2c7_pins>; 292 clock-frequency = <400000>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 status = "disabled"; 296 }; 297 298 i2c8: i2c@28038000 { 299 compatible = "snps,designware-i2c"; 300 reg = <0 0x28038000 0 0x1000>; 301 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c8_pins>; 304 clock-frequency = <400000>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 status = "disabled"; 308 }; 309 310 spi0: spi@28140000 { 311 compatible = "arm,pl022", "arm,primecell"; 312 reg = <0 0x28140000 0 0x1000>; 313 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&spi0_pins>; 316 num-cs = <1>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 status = "disabled"; 320 }; 321 322 spi1: spi@28141000 { 323 compatible = "arm,pl022", "arm,primecell"; 324 reg = <0 0x28141000 0 0x1000>; 325 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&spi1_pins>; 328 num-cs = <1>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 status = "disabled"; 332 }; 333 334 spi2: spi@28142000 { 335 compatible = "arm,pl022", "arm,primecell"; 336 reg = <0 0x28142000 0 0x1000>; 337 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&spi2_pins>; 340 num-cs = <1>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 }; 345 346 spi3: spi@28143000 { 347 compatible = "arm,pl022", "arm,primecell"; 348 reg = <0 0x28143000 0 0x1000>; 349 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&spi3_pins>; 352 num-cs = <1>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 spi4: spi@28144000 { 359 compatible = "arm,pl022", "arm,primecell"; 360 reg = <0 0x28144000 0 0x1000>; 361 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&spi4_pins>; 364 num-cs = <1>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 status = "disabled"; 368 }; 369 370 spi5: spi@28145000 { 371 compatible = "arm,pl022", "arm,primecell"; 372 reg = <0 0x28145000 0 0x1000>; 373 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&spi5_pins>; 376 num-cs = <1>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 status = "disabled"; 380 }; 381 382 spi6: spi@28146000 { 383 compatible = "arm,pl022", "arm,primecell"; 384 reg = <0 0x28146000 0 0x1000>; 385 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&spi6_pins>; 388 num-cs = <1>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 status = "disabled"; 392 }; 393 394 wdt: wdt@28330000 { 395 compatible = "toshiba,visconti-wdt"; 396 reg = <0 0x28330000 0 0x1000>; 397 status = "disabled"; 398 }; 399 }; 400}; 401 402#include "tmpv7708_pins.dtsi" 403