1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/clock/toshiba,tmpv770x.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 15 16/ { 17 compatible = "toshiba,tmpv7708"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0x0 0x81100000>; 62 reg = <0x00>; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x0 0x81100000>; 70 reg = <0x01>; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x0 0x81100000>; 78 reg = <0x02>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0x0 0x81100000>; 86 reg = <0x03>; 87 }; 88 89 cpu4: cpu@100 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x0 0x81100000>; 94 reg = <0x100>; 95 }; 96 97 cpu5: cpu@101 { 98 compatible = "arm,cortex-a53"; 99 device_type = "cpu"; 100 enable-method = "spin-table"; 101 cpu-release-addr = <0x0 0x81100000>; 102 reg = <0x101>; 103 }; 104 105 cpu6: cpu@102 { 106 compatible = "arm,cortex-a53"; 107 device_type = "cpu"; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0x0 0x81100000>; 110 reg = <0x102>; 111 }; 112 113 cpu7: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 device_type = "cpu"; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0x0 0x81100000>; 118 reg = <0x103>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&gic>; 125 interrupts = 126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 uart_clk: uart-clk { 133 compatible = "fixed-clock"; 134 clock-frequency = <150000000>; 135 #clock-cells = <0>; 136 }; 137 138 clk25mhz: clk25mhz { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <25000000>; 142 clock-output-names = "clk25mhz"; 143 }; 144 145 clk125mhz: clk125mhz { 146 compatible = "fixed-clock"; 147 clock-frequency = <125000000>; 148 #clock-cells = <0>; 149 clock-output-names = "clk125mhz"; 150 }; 151 152 clk150mhz: clk150mhz { 153 compatible = "fixed-clock"; 154 clock-frequency = <150000000>; 155 #clock-cells = <0>; 156 clock-output-names = "clk150mhz"; 157 }; 158 159 clk300mhz: clk300mhz { 160 compatible = "fixed-clock"; 161 clock-frequency = <300000000>; 162 #clock-cells = <0>; 163 clock-output-names = "clk300mhz"; 164 }; 165 166 clk600mhz: clk600mhz { 167 compatible = "fixed-clock"; 168 #clock-cells = <0>; 169 clock-frequency = <600000000>; 170 clock-output-names = "clk600mhz"; 171 }; 172 173 extclk100mhz: extclk100mhz { 174 compatible = "fixed-clock"; 175 #clock-cells = <0>; 176 clock-frequency = <100000000>; 177 clock-output-names = "extclk100mhz"; 178 }; 179 180 wdt_clk: wdt-clk { 181 compatible = "fixed-clock"; 182 clock-frequency = <150000000>; 183 #clock-cells = <0>; 184 }; 185 186 osc2_clk: osc2-clk { 187 compatible = "fixed-clock"; 188 clock-frequency = <20000000>; 189 #clock-cells = <0>; 190 }; 191 192 soc { 193 #address-cells = <2>; 194 #size-cells = <2>; 195 compatible = "simple-bus"; 196 interrupt-parent = <&gic>; 197 ranges; 198 199 gic: interrupt-controller@24001000 { 200 compatible = "arm,gic-400"; 201 interrupt-controller; 202 #interrupt-cells = <3>; 203 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 204 reg = <0 0x24001000 0 0x1000>, 205 <0 0x24002000 0 0x2000>, 206 <0 0x24004000 0 0x2000>, 207 <0 0x24006000 0 0x2000>; 208 }; 209 210 pmux: pmux@24190000 { 211 compatible = "toshiba,tmpv7708-pinctrl"; 212 reg = <0 0x24190000 0 0x10000>; 213 }; 214 215 gpio: gpio@28020000 { 216 compatible = "toshiba,gpio-tmpv7708"; 217 reg = <0 0x28020000 0 0x1000>; 218 #gpio-cells = <0x2>; 219 gpio-ranges = <&pmux 0 0 32>; 220 gpio-controller; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 interrupt-parent = <&gic>; 224 }; 225 226 pipllct: clock-controller@24220000 { 227 compatible = "toshiba,tmpv7708-pipllct"; 228 reg = <0 0x24220000 0 0x820>; 229 #clock-cells = <1>; 230 clocks = <&osc2_clk>; 231 }; 232 233 pismu: syscon@24200000 { 234 compatible = "toshiba,tmpv7708-pismu", "syscon"; 235 reg = <0 0x24200000 0 0x2140>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 uart0: serial@28200000 { 241 compatible = "arm,pl011", "arm,primecell"; 242 reg = <0 0x28200000 0 0x1000>; 243 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&uart0_pins>; 246 status = "disabled"; 247 }; 248 249 uart1: serial@28201000 { 250 compatible = "arm,pl011", "arm,primecell"; 251 reg = <0 0x28201000 0 0x1000>; 252 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&uart1_pins>; 255 status = "disabled"; 256 }; 257 258 uart2: serial@28202000 { 259 compatible = "arm,pl011", "arm,primecell"; 260 reg = <0 0x28202000 0 0x1000>; 261 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&uart2_pins>; 264 status = "disabled"; 265 }; 266 267 uart3: serial@28203000 { 268 compatible = "arm,pl011", "arm,primecell"; 269 reg = <0 0x28203000 0 0x1000>; 270 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&uart3_pins>; 273 status = "disabled"; 274 }; 275 276 i2c0: i2c@28030000 { 277 compatible = "snps,designware-i2c"; 278 reg = <0 0x28030000 0 0x1000>; 279 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&i2c0_pins>; 282 clock-frequency = <400000>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 status = "disabled"; 286 }; 287 288 i2c1: i2c@28031000 { 289 compatible = "snps,designware-i2c"; 290 reg = <0 0x28031000 0 0x1000>; 291 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&i2c1_pins>; 294 clock-frequency = <400000>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 i2c2: i2c@28032000 { 301 compatible = "snps,designware-i2c"; 302 reg = <0 0x28032000 0 0x1000>; 303 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&i2c2_pins>; 306 clock-frequency = <400000>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 status = "disabled"; 310 }; 311 312 i2c3: i2c@28033000 { 313 compatible = "snps,designware-i2c"; 314 reg = <0 0x28033000 0 0x1000>; 315 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&i2c3_pins>; 318 clock-frequency = <400000>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 status = "disabled"; 322 }; 323 324 i2c4: i2c@28034000 { 325 compatible = "snps,designware-i2c"; 326 reg = <0 0x28034000 0 0x1000>; 327 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2c4_pins>; 330 clock-frequency = <400000>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 status = "disabled"; 334 }; 335 336 i2c5: i2c@28035000 { 337 compatible = "snps,designware-i2c"; 338 reg = <0 0x28035000 0 0x1000>; 339 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&i2c5_pins>; 342 clock-frequency = <400000>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 status = "disabled"; 346 }; 347 348 i2c6: i2c@28036000 { 349 compatible = "snps,designware-i2c"; 350 reg = <0 0x28036000 0 0x1000>; 351 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&i2c6_pins>; 354 clock-frequency = <400000>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 status = "disabled"; 358 }; 359 360 i2c7: i2c@28037000 { 361 compatible = "snps,designware-i2c"; 362 reg = <0 0x28037000 0 0x1000>; 363 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&i2c7_pins>; 366 clock-frequency = <400000>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 status = "disabled"; 370 }; 371 372 i2c8: i2c@28038000 { 373 compatible = "snps,designware-i2c"; 374 reg = <0 0x28038000 0 0x1000>; 375 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&i2c8_pins>; 378 clock-frequency = <400000>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 status = "disabled"; 382 }; 383 384 spi0: spi@28140000 { 385 compatible = "arm,pl022", "arm,primecell"; 386 reg = <0 0x28140000 0 0x1000>; 387 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&spi0_pins>; 390 num-cs = <1>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 status = "disabled"; 394 }; 395 396 spi1: spi@28141000 { 397 compatible = "arm,pl022", "arm,primecell"; 398 reg = <0 0x28141000 0 0x1000>; 399 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&spi1_pins>; 402 num-cs = <1>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 spi2: spi@28142000 { 409 compatible = "arm,pl022", "arm,primecell"; 410 reg = <0 0x28142000 0 0x1000>; 411 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 412 pinctrl-names = "default"; 413 pinctrl-0 = <&spi2_pins>; 414 num-cs = <1>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 status = "disabled"; 418 }; 419 420 spi3: spi@28143000 { 421 compatible = "arm,pl022", "arm,primecell"; 422 reg = <0 0x28143000 0 0x1000>; 423 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&spi3_pins>; 426 num-cs = <1>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 spi4: spi@28144000 { 433 compatible = "arm,pl022", "arm,primecell"; 434 reg = <0 0x28144000 0 0x1000>; 435 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&spi4_pins>; 438 num-cs = <1>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 spi5: spi@28145000 { 445 compatible = "arm,pl022", "arm,primecell"; 446 reg = <0 0x28145000 0 0x1000>; 447 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&spi5_pins>; 450 num-cs = <1>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 status = "disabled"; 454 }; 455 456 spi6: spi@28146000 { 457 compatible = "arm,pl022", "arm,primecell"; 458 reg = <0 0x28146000 0 0x1000>; 459 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&spi6_pins>; 462 num-cs = <1>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 piether: ethernet@28000000 { 469 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 470 reg = <0 0x28000000 0 0x10000>; 471 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 472 interrupt-names = "macirq"; 473 snps,txpbl = <4>; 474 snps,rxpbl = <4>; 475 snps,tso; 476 status = "disabled"; 477 }; 478 479 wdt: wdt@28330000 { 480 compatible = "toshiba,visconti-wdt"; 481 reg = <0 0x28330000 0 0x1000>; 482 status = "disabled"; 483 }; 484 485 pwm: pwm@241c0000 { 486 compatible = "toshiba,visconti-pwm"; 487 reg = <0 0x241c0000 0 0x1000>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pwm_mux>; 490 #pwm-cells = <2>; 491 status = "disabled"; 492 }; 493 494 pcie: pcie@28400000 { 495 compatible = "toshiba,visconti-pcie"; 496 reg = <0x0 0x28400000 0x0 0x00400000>, 497 <0x0 0x70000000 0x0 0x10000000>, 498 <0x0 0x28050000 0x0 0x00010000>, 499 <0x0 0x24200000 0x0 0x00002000>, 500 <0x0 0x24162000 0x0 0x00001000>; 501 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 502 device_type = "pci"; 503 bus-range = <0x00 0xff>; 504 num-lanes = <2>; 505 num-viewport = <8>; 506 507 #address-cells = <3>; 508 #size-cells = <2>; 509 #interrupt-cells = <1>; 510 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 511 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 512 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 514 interrupt-names = "msi", "intr"; 515 interrupt-map-mask = <0 0 0 7>; 516 interrupt-map = 517 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 518 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 519 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 520 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 521 max-link-speed = <2>; 522 status = "disabled"; 523 }; 524 }; 525}; 526 527#include "tmpv7708_pins.dtsi" 528