1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/clock/toshiba,tmpv770x.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 15 16/ { 17 compatible = "toshiba,tmpv7708"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0x0 0x81100000>; 62 reg = <0x00>; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x0 0x81100000>; 70 reg = <0x01>; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x0 0x81100000>; 78 reg = <0x02>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0x0 0x81100000>; 86 reg = <0x03>; 87 }; 88 89 cpu4: cpu@100 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x0 0x81100000>; 94 reg = <0x100>; 95 }; 96 97 cpu5: cpu@101 { 98 compatible = "arm,cortex-a53"; 99 device_type = "cpu"; 100 enable-method = "spin-table"; 101 cpu-release-addr = <0x0 0x81100000>; 102 reg = <0x101>; 103 }; 104 105 cpu6: cpu@102 { 106 compatible = "arm,cortex-a53"; 107 device_type = "cpu"; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0x0 0x81100000>; 110 reg = <0x102>; 111 }; 112 113 cpu7: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 device_type = "cpu"; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0x0 0x81100000>; 118 reg = <0x103>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&gic>; 125 interrupts = 126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 clk25mhz: clk25mhz { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <25000000>; 136 clock-output-names = "clk25mhz"; 137 }; 138 139 clk125mhz: clk125mhz { 140 compatible = "fixed-clock"; 141 clock-frequency = <125000000>; 142 #clock-cells = <0>; 143 clock-output-names = "clk125mhz"; 144 }; 145 146 clk300mhz: clk300mhz { 147 compatible = "fixed-clock"; 148 clock-frequency = <300000000>; 149 #clock-cells = <0>; 150 clock-output-names = "clk300mhz"; 151 }; 152 153 clk600mhz: clk600mhz { 154 compatible = "fixed-clock"; 155 #clock-cells = <0>; 156 clock-frequency = <600000000>; 157 clock-output-names = "clk600mhz"; 158 }; 159 160 extclk100mhz: extclk100mhz { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <100000000>; 164 clock-output-names = "extclk100mhz"; 165 }; 166 167 osc2_clk: osc2-clk { 168 compatible = "fixed-clock"; 169 clock-frequency = <20000000>; 170 #clock-cells = <0>; 171 }; 172 173 soc { 174 #address-cells = <2>; 175 #size-cells = <2>; 176 compatible = "simple-bus"; 177 interrupt-parent = <&gic>; 178 ranges; 179 180 gic: interrupt-controller@24001000 { 181 compatible = "arm,gic-400"; 182 interrupt-controller; 183 #interrupt-cells = <3>; 184 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 185 reg = <0 0x24001000 0 0x1000>, 186 <0 0x24002000 0 0x2000>, 187 <0 0x24004000 0 0x2000>, 188 <0 0x24006000 0 0x2000>; 189 }; 190 191 pmux: pmux@24190000 { 192 compatible = "toshiba,tmpv7708-pinctrl"; 193 reg = <0 0x24190000 0 0x10000>; 194 }; 195 196 gpio: gpio@28020000 { 197 compatible = "toshiba,gpio-tmpv7708"; 198 reg = <0 0x28020000 0 0x1000>; 199 #gpio-cells = <0x2>; 200 gpio-ranges = <&pmux 0 0 32>; 201 gpio-controller; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 interrupt-parent = <&gic>; 205 }; 206 207 pipllct: clock-controller@24220000 { 208 compatible = "toshiba,tmpv7708-pipllct"; 209 reg = <0 0x24220000 0 0x820>; 210 #clock-cells = <1>; 211 clocks = <&osc2_clk>; 212 }; 213 214 pismu: syscon@24200000 { 215 compatible = "toshiba,tmpv7708-pismu", "syscon"; 216 reg = <0 0x24200000 0 0x2140>; 217 #clock-cells = <1>; 218 #reset-cells = <1>; 219 }; 220 221 uart0: serial@28200000 { 222 compatible = "arm,pl011", "arm,primecell"; 223 reg = <0 0x28200000 0 0x1000>; 224 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&uart0_pins>; 227 clocks = <&pismu TMPV770X_CLK_PIUART0>; 228 clock-names = "apb_pclk"; 229 status = "disabled"; 230 }; 231 232 uart1: serial@28201000 { 233 compatible = "arm,pl011", "arm,primecell"; 234 reg = <0 0x28201000 0 0x1000>; 235 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&uart1_pins>; 238 clocks = <&pismu TMPV770X_CLK_PIUART1>; 239 clock-names = "apb_pclk"; 240 status = "disabled"; 241 }; 242 243 uart2: serial@28202000 { 244 compatible = "arm,pl011", "arm,primecell"; 245 reg = <0 0x28202000 0 0x1000>; 246 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&uart2_pins>; 249 clocks = <&pismu TMPV770X_CLK_PIUART2>; 250 clock-names = "apb_pclk"; 251 status = "disabled"; 252 }; 253 254 uart3: serial@28203000 { 255 compatible = "arm,pl011", "arm,primecell"; 256 reg = <0 0x28203000 0 0x1000>; 257 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&uart3_pins>; 260 clocks = <&pismu TMPV770X_CLK_PIUART2>; 261 clock-names = "apb_pclk"; 262 status = "disabled"; 263 }; 264 265 i2c0: i2c@28030000 { 266 compatible = "snps,designware-i2c"; 267 reg = <0 0x28030000 0 0x1000>; 268 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&i2c0_pins>; 271 clock-frequency = <400000>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 clocks = <&pismu TMPV770X_CLK_PII2C0>; 275 status = "disabled"; 276 }; 277 278 i2c1: i2c@28031000 { 279 compatible = "snps,designware-i2c"; 280 reg = <0 0x28031000 0 0x1000>; 281 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c1_pins>; 284 clock-frequency = <400000>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 clocks = <&pismu TMPV770X_CLK_PII2C1>; 288 status = "disabled"; 289 }; 290 291 i2c2: i2c@28032000 { 292 compatible = "snps,designware-i2c"; 293 reg = <0 0x28032000 0 0x1000>; 294 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c2_pins>; 297 clock-frequency = <400000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&pismu TMPV770X_CLK_PII2C2>; 301 status = "disabled"; 302 }; 303 304 i2c3: i2c@28033000 { 305 compatible = "snps,designware-i2c"; 306 reg = <0 0x28033000 0 0x1000>; 307 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&i2c3_pins>; 310 clock-frequency = <400000>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clocks = <&pismu TMPV770X_CLK_PII2C3>; 314 status = "disabled"; 315 }; 316 317 i2c4: i2c@28034000 { 318 compatible = "snps,designware-i2c"; 319 reg = <0 0x28034000 0 0x1000>; 320 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c4_pins>; 323 clock-frequency = <400000>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 clocks = <&pismu TMPV770X_CLK_PII2C4>; 327 status = "disabled"; 328 }; 329 330 i2c5: i2c@28035000 { 331 compatible = "snps,designware-i2c"; 332 reg = <0 0x28035000 0 0x1000>; 333 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c5_pins>; 336 clock-frequency = <400000>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 clocks = <&pismu TMPV770X_CLK_PII2C5>; 340 status = "disabled"; 341 }; 342 343 i2c6: i2c@28036000 { 344 compatible = "snps,designware-i2c"; 345 reg = <0 0x28036000 0 0x1000>; 346 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c6_pins>; 349 clock-frequency = <400000>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clocks = <&pismu TMPV770X_CLK_PII2C6>; 353 status = "disabled"; 354 }; 355 356 i2c7: i2c@28037000 { 357 compatible = "snps,designware-i2c"; 358 reg = <0 0x28037000 0 0x1000>; 359 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&i2c7_pins>; 362 clock-frequency = <400000>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 clocks = <&pismu TMPV770X_CLK_PII2C7>; 366 status = "disabled"; 367 }; 368 369 i2c8: i2c@28038000 { 370 compatible = "snps,designware-i2c"; 371 reg = <0 0x28038000 0 0x1000>; 372 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&i2c8_pins>; 375 clock-frequency = <400000>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&pismu TMPV770X_CLK_PII2C8>; 379 status = "disabled"; 380 }; 381 382 spi0: spi@28140000 { 383 compatible = "arm,pl022", "arm,primecell"; 384 reg = <0 0x28140000 0 0x1000>; 385 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&spi0_pins>; 388 num-cs = <1>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&pismu TMPV770X_CLK_PISPI1>; 392 clock-names = "apb_pclk"; 393 status = "disabled"; 394 }; 395 396 spi1: spi@28141000 { 397 compatible = "arm,pl022", "arm,primecell"; 398 reg = <0 0x28141000 0 0x1000>; 399 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&spi1_pins>; 402 num-cs = <1>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&pismu TMPV770X_CLK_PISPI1>; 406 clock-names = "apb_pclk"; 407 status = "disabled"; 408 }; 409 410 spi2: spi@28142000 { 411 compatible = "arm,pl022", "arm,primecell"; 412 reg = <0 0x28142000 0 0x1000>; 413 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&spi2_pins>; 416 num-cs = <1>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 clocks = <&pismu TMPV770X_CLK_PISPI2>; 420 clock-names = "apb_pclk"; 421 status = "disabled"; 422 }; 423 424 spi3: spi@28143000 { 425 compatible = "arm,pl022", "arm,primecell"; 426 reg = <0 0x28143000 0 0x1000>; 427 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&spi3_pins>; 430 num-cs = <1>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 clocks = <&pismu TMPV770X_CLK_PISPI3>; 434 clock-names = "apb_pclk"; 435 status = "disabled"; 436 }; 437 438 spi4: spi@28144000 { 439 compatible = "arm,pl022", "arm,primecell"; 440 reg = <0 0x28144000 0 0x1000>; 441 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&spi4_pins>; 444 num-cs = <1>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&pismu TMPV770X_CLK_PISPI4>; 448 clock-names = "apb_pclk"; 449 status = "disabled"; 450 }; 451 452 spi5: spi@28145000 { 453 compatible = "arm,pl022", "arm,primecell"; 454 reg = <0 0x28145000 0 0x1000>; 455 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&spi5_pins>; 458 num-cs = <1>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clocks = <&pismu TMPV770X_CLK_PISPI5>; 462 clock-names = "apb_pclk"; 463 status = "disabled"; 464 }; 465 466 spi6: spi@28146000 { 467 compatible = "arm,pl022", "arm,primecell"; 468 reg = <0 0x28146000 0 0x1000>; 469 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&spi6_pins>; 472 num-cs = <1>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clocks = <&pismu TMPV770X_CLK_PISPI6>; 476 clock-names = "apb_pclk"; 477 status = "disabled"; 478 }; 479 480 piether: ethernet@28000000 { 481 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 482 reg = <0 0x28000000 0 0x10000>; 483 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "macirq"; 485 snps,txpbl = <4>; 486 snps,rxpbl = <4>; 487 snps,tso; 488 status = "disabled"; 489 }; 490 491 wdt: wdt@28330000 { 492 compatible = "toshiba,visconti-wdt"; 493 reg = <0 0x28330000 0 0x1000>; 494 clocks = <&pismu TMPV770X_CLK_WDTCLK>; 495 status = "disabled"; 496 }; 497 498 pwm: pwm@241c0000 { 499 compatible = "toshiba,visconti-pwm"; 500 reg = <0 0x241c0000 0 0x1000>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&pwm_mux>; 503 #pwm-cells = <2>; 504 status = "disabled"; 505 }; 506 507 pcie: pcie@28400000 { 508 compatible = "toshiba,visconti-pcie"; 509 reg = <0x0 0x28400000 0x0 0x00400000>, 510 <0x0 0x70000000 0x0 0x10000000>, 511 <0x0 0x28050000 0x0 0x00010000>, 512 <0x0 0x24200000 0x0 0x00002000>, 513 <0x0 0x24162000 0x0 0x00001000>; 514 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 515 device_type = "pci"; 516 bus-range = <0x00 0xff>; 517 num-lanes = <2>; 518 num-viewport = <8>; 519 520 #address-cells = <3>; 521 #size-cells = <2>; 522 #interrupt-cells = <1>; 523 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 524 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 525 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 527 interrupt-names = "msi", "intr"; 528 interrupt-map-mask = <0 0 0 7>; 529 interrupt-map = 530 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 531 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 532 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 533 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 534 max-link-speed = <2>; 535 status = "disabled"; 536 }; 537 }; 538}; 539 540#include "tmpv7708_pins.dtsi" 541