1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/clock/toshiba,tmpv770x.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 15 16/ { 17 compatible = "toshiba,tmpv7708"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0x0 0x81100000>; 62 reg = <0x00>; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x0 0x81100000>; 70 reg = <0x01>; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x0 0x81100000>; 78 reg = <0x02>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0x0 0x81100000>; 86 reg = <0x03>; 87 }; 88 89 cpu4: cpu@100 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x0 0x81100000>; 94 reg = <0x100>; 95 }; 96 97 cpu5: cpu@101 { 98 compatible = "arm,cortex-a53"; 99 device_type = "cpu"; 100 enable-method = "spin-table"; 101 cpu-release-addr = <0x0 0x81100000>; 102 reg = <0x101>; 103 }; 104 105 cpu6: cpu@102 { 106 compatible = "arm,cortex-a53"; 107 device_type = "cpu"; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0x0 0x81100000>; 110 reg = <0x102>; 111 }; 112 113 cpu7: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 device_type = "cpu"; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0x0 0x81100000>; 118 reg = <0x103>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&gic>; 125 interrupts = 126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 clk25mhz: clk25mhz { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <25000000>; 136 clock-output-names = "clk25mhz"; 137 }; 138 139 clk125mhz: clk125mhz { 140 compatible = "fixed-clock"; 141 clock-frequency = <125000000>; 142 #clock-cells = <0>; 143 clock-output-names = "clk125mhz"; 144 }; 145 146 clk150mhz: clk150mhz { 147 compatible = "fixed-clock"; 148 clock-frequency = <150000000>; 149 #clock-cells = <0>; 150 clock-output-names = "clk150mhz"; 151 }; 152 153 clk300mhz: clk300mhz { 154 compatible = "fixed-clock"; 155 clock-frequency = <300000000>; 156 #clock-cells = <0>; 157 clock-output-names = "clk300mhz"; 158 }; 159 160 clk600mhz: clk600mhz { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <600000000>; 164 clock-output-names = "clk600mhz"; 165 }; 166 167 extclk100mhz: extclk100mhz { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 clock-frequency = <100000000>; 171 clock-output-names = "extclk100mhz"; 172 }; 173 174 osc2_clk: osc2-clk { 175 compatible = "fixed-clock"; 176 clock-frequency = <20000000>; 177 #clock-cells = <0>; 178 }; 179 180 soc { 181 #address-cells = <2>; 182 #size-cells = <2>; 183 compatible = "simple-bus"; 184 interrupt-parent = <&gic>; 185 ranges; 186 187 gic: interrupt-controller@24001000 { 188 compatible = "arm,gic-400"; 189 interrupt-controller; 190 #interrupt-cells = <3>; 191 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 192 reg = <0 0x24001000 0 0x1000>, 193 <0 0x24002000 0 0x2000>, 194 <0 0x24004000 0 0x2000>, 195 <0 0x24006000 0 0x2000>; 196 }; 197 198 pmux: pmux@24190000 { 199 compatible = "toshiba,tmpv7708-pinctrl"; 200 reg = <0 0x24190000 0 0x10000>; 201 }; 202 203 gpio: gpio@28020000 { 204 compatible = "toshiba,gpio-tmpv7708"; 205 reg = <0 0x28020000 0 0x1000>; 206 #gpio-cells = <0x2>; 207 gpio-ranges = <&pmux 0 0 32>; 208 gpio-controller; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 interrupt-parent = <&gic>; 212 }; 213 214 pipllct: clock-controller@24220000 { 215 compatible = "toshiba,tmpv7708-pipllct"; 216 reg = <0 0x24220000 0 0x820>; 217 #clock-cells = <1>; 218 clocks = <&osc2_clk>; 219 }; 220 221 pismu: syscon@24200000 { 222 compatible = "toshiba,tmpv7708-pismu", "syscon"; 223 reg = <0 0x24200000 0 0x2140>; 224 #clock-cells = <1>; 225 #reset-cells = <1>; 226 }; 227 228 uart0: serial@28200000 { 229 compatible = "arm,pl011", "arm,primecell"; 230 reg = <0 0x28200000 0 0x1000>; 231 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&uart0_pins>; 234 clocks = <&pismu TMPV770X_CLK_PIUART0>; 235 clock-names = "apb_pclk"; 236 status = "disabled"; 237 }; 238 239 uart1: serial@28201000 { 240 compatible = "arm,pl011", "arm,primecell"; 241 reg = <0 0x28201000 0 0x1000>; 242 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&uart1_pins>; 245 clocks = <&pismu TMPV770X_CLK_PIUART1>; 246 clock-names = "apb_pclk"; 247 status = "disabled"; 248 }; 249 250 uart2: serial@28202000 { 251 compatible = "arm,pl011", "arm,primecell"; 252 reg = <0 0x28202000 0 0x1000>; 253 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&uart2_pins>; 256 clocks = <&pismu TMPV770X_CLK_PIUART2>; 257 clock-names = "apb_pclk"; 258 status = "disabled"; 259 }; 260 261 uart3: serial@28203000 { 262 compatible = "arm,pl011", "arm,primecell"; 263 reg = <0 0x28203000 0 0x1000>; 264 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&uart3_pins>; 267 clocks = <&pismu TMPV770X_CLK_PIUART2>; 268 clock-names = "apb_pclk"; 269 status = "disabled"; 270 }; 271 272 i2c0: i2c@28030000 { 273 compatible = "snps,designware-i2c"; 274 reg = <0 0x28030000 0 0x1000>; 275 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&i2c0_pins>; 278 clock-frequency = <400000>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 clocks = <&pismu TMPV770X_CLK_PII2C0>; 282 status = "disabled"; 283 }; 284 285 i2c1: i2c@28031000 { 286 compatible = "snps,designware-i2c"; 287 reg = <0 0x28031000 0 0x1000>; 288 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&i2c1_pins>; 291 clock-frequency = <400000>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clocks = <&pismu TMPV770X_CLK_PII2C1>; 295 status = "disabled"; 296 }; 297 298 i2c2: i2c@28032000 { 299 compatible = "snps,designware-i2c"; 300 reg = <0 0x28032000 0 0x1000>; 301 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&i2c2_pins>; 304 clock-frequency = <400000>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 clocks = <&pismu TMPV770X_CLK_PII2C2>; 308 status = "disabled"; 309 }; 310 311 i2c3: i2c@28033000 { 312 compatible = "snps,designware-i2c"; 313 reg = <0 0x28033000 0 0x1000>; 314 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&i2c3_pins>; 317 clock-frequency = <400000>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 clocks = <&pismu TMPV770X_CLK_PII2C3>; 321 status = "disabled"; 322 }; 323 324 i2c4: i2c@28034000 { 325 compatible = "snps,designware-i2c"; 326 reg = <0 0x28034000 0 0x1000>; 327 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&i2c4_pins>; 330 clock-frequency = <400000>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 clocks = <&pismu TMPV770X_CLK_PII2C4>; 334 status = "disabled"; 335 }; 336 337 i2c5: i2c@28035000 { 338 compatible = "snps,designware-i2c"; 339 reg = <0 0x28035000 0 0x1000>; 340 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&i2c5_pins>; 343 clock-frequency = <400000>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clocks = <&pismu TMPV770X_CLK_PII2C5>; 347 status = "disabled"; 348 }; 349 350 i2c6: i2c@28036000 { 351 compatible = "snps,designware-i2c"; 352 reg = <0 0x28036000 0 0x1000>; 353 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&i2c6_pins>; 356 clock-frequency = <400000>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clocks = <&pismu TMPV770X_CLK_PII2C6>; 360 status = "disabled"; 361 }; 362 363 i2c7: i2c@28037000 { 364 compatible = "snps,designware-i2c"; 365 reg = <0 0x28037000 0 0x1000>; 366 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&i2c7_pins>; 369 clock-frequency = <400000>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 clocks = <&pismu TMPV770X_CLK_PII2C7>; 373 status = "disabled"; 374 }; 375 376 i2c8: i2c@28038000 { 377 compatible = "snps,designware-i2c"; 378 reg = <0 0x28038000 0 0x1000>; 379 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 380 pinctrl-names = "default"; 381 pinctrl-0 = <&i2c8_pins>; 382 clock-frequency = <400000>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&pismu TMPV770X_CLK_PII2C8>; 386 status = "disabled"; 387 }; 388 389 spi0: spi@28140000 { 390 compatible = "arm,pl022", "arm,primecell"; 391 reg = <0 0x28140000 0 0x1000>; 392 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&spi0_pins>; 395 num-cs = <1>; 396 #address-cells = <1>; 397 #size-cells = <0>; 398 status = "disabled"; 399 }; 400 401 spi1: spi@28141000 { 402 compatible = "arm,pl022", "arm,primecell"; 403 reg = <0 0x28141000 0 0x1000>; 404 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&spi1_pins>; 407 num-cs = <1>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 status = "disabled"; 411 }; 412 413 spi2: spi@28142000 { 414 compatible = "arm,pl022", "arm,primecell"; 415 reg = <0 0x28142000 0 0x1000>; 416 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&spi2_pins>; 419 num-cs = <1>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 status = "disabled"; 423 }; 424 425 spi3: spi@28143000 { 426 compatible = "arm,pl022", "arm,primecell"; 427 reg = <0 0x28143000 0 0x1000>; 428 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&spi3_pins>; 431 num-cs = <1>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 status = "disabled"; 435 }; 436 437 spi4: spi@28144000 { 438 compatible = "arm,pl022", "arm,primecell"; 439 reg = <0 0x28144000 0 0x1000>; 440 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&spi4_pins>; 443 num-cs = <1>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 status = "disabled"; 447 }; 448 449 spi5: spi@28145000 { 450 compatible = "arm,pl022", "arm,primecell"; 451 reg = <0 0x28145000 0 0x1000>; 452 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&spi5_pins>; 455 num-cs = <1>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 status = "disabled"; 459 }; 460 461 spi6: spi@28146000 { 462 compatible = "arm,pl022", "arm,primecell"; 463 reg = <0 0x28146000 0 0x1000>; 464 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&spi6_pins>; 467 num-cs = <1>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 piether: ethernet@28000000 { 474 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 475 reg = <0 0x28000000 0 0x10000>; 476 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-names = "macirq"; 478 snps,txpbl = <4>; 479 snps,rxpbl = <4>; 480 snps,tso; 481 status = "disabled"; 482 }; 483 484 wdt: wdt@28330000 { 485 compatible = "toshiba,visconti-wdt"; 486 reg = <0 0x28330000 0 0x1000>; 487 clocks = <&pismu TMPV770X_CLK_WDTCLK>; 488 status = "disabled"; 489 }; 490 491 pwm: pwm@241c0000 { 492 compatible = "toshiba,visconti-pwm"; 493 reg = <0 0x241c0000 0 0x1000>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pwm_mux>; 496 #pwm-cells = <2>; 497 status = "disabled"; 498 }; 499 500 pcie: pcie@28400000 { 501 compatible = "toshiba,visconti-pcie"; 502 reg = <0x0 0x28400000 0x0 0x00400000>, 503 <0x0 0x70000000 0x0 0x10000000>, 504 <0x0 0x28050000 0x0 0x00010000>, 505 <0x0 0x24200000 0x0 0x00002000>, 506 <0x0 0x24162000 0x0 0x00001000>; 507 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 508 device_type = "pci"; 509 bus-range = <0x00 0xff>; 510 num-lanes = <2>; 511 num-viewport = <8>; 512 513 #address-cells = <3>; 514 #size-cells = <2>; 515 #interrupt-cells = <1>; 516 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 517 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 518 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 520 interrupt-names = "msi", "intr"; 521 interrupt-map-mask = <0 0 0 7>; 522 interrupt-map = 523 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 524 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 525 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 526 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 527 max-link-speed = <2>; 528 status = "disabled"; 529 }; 530 }; 531}; 532 533#include "tmpv7708_pins.dtsi" 534