1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/clock/toshiba,tmpv770x.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 15 16/ { 17 compatible = "toshiba,tmpv7708"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 core2 { 34 cpu = <&cpu2>; 35 }; 36 core3 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 41 cluster1 { 42 core0 { 43 cpu = <&cpu4>; 44 }; 45 core1 { 46 cpu = <&cpu5>; 47 }; 48 core2 { 49 cpu = <&cpu6>; 50 }; 51 core3 { 52 cpu = <&cpu7>; 53 }; 54 }; 55 }; 56 57 cpu0: cpu@0 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0x0 0x81100000>; 62 reg = <0x00>; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x0 0x81100000>; 70 reg = <0x01>; 71 }; 72 73 cpu2: cpu@2 { 74 compatible = "arm,cortex-a53"; 75 device_type = "cpu"; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x0 0x81100000>; 78 reg = <0x02>; 79 }; 80 81 cpu3: cpu@3 { 82 compatible = "arm,cortex-a53"; 83 device_type = "cpu"; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0x0 0x81100000>; 86 reg = <0x03>; 87 }; 88 89 cpu4: cpu@100 { 90 compatible = "arm,cortex-a53"; 91 device_type = "cpu"; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x0 0x81100000>; 94 reg = <0x100>; 95 }; 96 97 cpu5: cpu@101 { 98 compatible = "arm,cortex-a53"; 99 device_type = "cpu"; 100 enable-method = "spin-table"; 101 cpu-release-addr = <0x0 0x81100000>; 102 reg = <0x101>; 103 }; 104 105 cpu6: cpu@102 { 106 compatible = "arm,cortex-a53"; 107 device_type = "cpu"; 108 enable-method = "spin-table"; 109 cpu-release-addr = <0x0 0x81100000>; 110 reg = <0x102>; 111 }; 112 113 cpu7: cpu@103 { 114 compatible = "arm,cortex-a53"; 115 device_type = "cpu"; 116 enable-method = "spin-table"; 117 cpu-release-addr = <0x0 0x81100000>; 118 reg = <0x103>; 119 }; 120 }; 121 122 timer { 123 compatible = "arm,armv8-timer"; 124 interrupt-parent = <&gic>; 125 interrupts = 126 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 130 }; 131 132 clk25mhz: clk25mhz { 133 compatible = "fixed-clock"; 134 #clock-cells = <0>; 135 clock-frequency = <25000000>; 136 clock-output-names = "clk25mhz"; 137 }; 138 139 clk125mhz: clk125mhz { 140 compatible = "fixed-clock"; 141 clock-frequency = <125000000>; 142 #clock-cells = <0>; 143 clock-output-names = "clk125mhz"; 144 }; 145 146 clk150mhz: clk150mhz { 147 compatible = "fixed-clock"; 148 clock-frequency = <150000000>; 149 #clock-cells = <0>; 150 clock-output-names = "clk150mhz"; 151 }; 152 153 clk300mhz: clk300mhz { 154 compatible = "fixed-clock"; 155 clock-frequency = <300000000>; 156 #clock-cells = <0>; 157 clock-output-names = "clk300mhz"; 158 }; 159 160 clk600mhz: clk600mhz { 161 compatible = "fixed-clock"; 162 #clock-cells = <0>; 163 clock-frequency = <600000000>; 164 clock-output-names = "clk600mhz"; 165 }; 166 167 extclk100mhz: extclk100mhz { 168 compatible = "fixed-clock"; 169 #clock-cells = <0>; 170 clock-frequency = <100000000>; 171 clock-output-names = "extclk100mhz"; 172 }; 173 174 wdt_clk: wdt-clk { 175 compatible = "fixed-clock"; 176 clock-frequency = <150000000>; 177 #clock-cells = <0>; 178 }; 179 180 osc2_clk: osc2-clk { 181 compatible = "fixed-clock"; 182 clock-frequency = <20000000>; 183 #clock-cells = <0>; 184 }; 185 186 soc { 187 #address-cells = <2>; 188 #size-cells = <2>; 189 compatible = "simple-bus"; 190 interrupt-parent = <&gic>; 191 ranges; 192 193 gic: interrupt-controller@24001000 { 194 compatible = "arm,gic-400"; 195 interrupt-controller; 196 #interrupt-cells = <3>; 197 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 198 reg = <0 0x24001000 0 0x1000>, 199 <0 0x24002000 0 0x2000>, 200 <0 0x24004000 0 0x2000>, 201 <0 0x24006000 0 0x2000>; 202 }; 203 204 pmux: pmux@24190000 { 205 compatible = "toshiba,tmpv7708-pinctrl"; 206 reg = <0 0x24190000 0 0x10000>; 207 }; 208 209 gpio: gpio@28020000 { 210 compatible = "toshiba,gpio-tmpv7708"; 211 reg = <0 0x28020000 0 0x1000>; 212 #gpio-cells = <0x2>; 213 gpio-ranges = <&pmux 0 0 32>; 214 gpio-controller; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 interrupt-parent = <&gic>; 218 }; 219 220 pipllct: clock-controller@24220000 { 221 compatible = "toshiba,tmpv7708-pipllct"; 222 reg = <0 0x24220000 0 0x820>; 223 #clock-cells = <1>; 224 clocks = <&osc2_clk>; 225 }; 226 227 pismu: syscon@24200000 { 228 compatible = "toshiba,tmpv7708-pismu", "syscon"; 229 reg = <0 0x24200000 0 0x2140>; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 }; 233 234 uart0: serial@28200000 { 235 compatible = "arm,pl011", "arm,primecell"; 236 reg = <0 0x28200000 0 0x1000>; 237 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&uart0_pins>; 240 clocks = <&pismu TMPV770X_CLK_PIUART0>; 241 clock-names = "apb_pclk"; 242 status = "disabled"; 243 }; 244 245 uart1: serial@28201000 { 246 compatible = "arm,pl011", "arm,primecell"; 247 reg = <0 0x28201000 0 0x1000>; 248 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&uart1_pins>; 251 clocks = <&pismu TMPV770X_CLK_PIUART1>; 252 clock-names = "apb_pclk"; 253 status = "disabled"; 254 }; 255 256 uart2: serial@28202000 { 257 compatible = "arm,pl011", "arm,primecell"; 258 reg = <0 0x28202000 0 0x1000>; 259 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&uart2_pins>; 262 clocks = <&pismu TMPV770X_CLK_PIUART2>; 263 clock-names = "apb_pclk"; 264 status = "disabled"; 265 }; 266 267 uart3: serial@28203000 { 268 compatible = "arm,pl011", "arm,primecell"; 269 reg = <0 0x28203000 0 0x1000>; 270 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&uart3_pins>; 273 clocks = <&pismu TMPV770X_CLK_PIUART2>; 274 clock-names = "apb_pclk"; 275 status = "disabled"; 276 }; 277 278 i2c0: i2c@28030000 { 279 compatible = "snps,designware-i2c"; 280 reg = <0 0x28030000 0 0x1000>; 281 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&i2c0_pins>; 284 clock-frequency = <400000>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 clocks = <&pismu TMPV770X_CLK_PII2C0>; 288 status = "disabled"; 289 }; 290 291 i2c1: i2c@28031000 { 292 compatible = "snps,designware-i2c"; 293 reg = <0 0x28031000 0 0x1000>; 294 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&i2c1_pins>; 297 clock-frequency = <400000>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&pismu TMPV770X_CLK_PII2C1>; 301 status = "disabled"; 302 }; 303 304 i2c2: i2c@28032000 { 305 compatible = "snps,designware-i2c"; 306 reg = <0 0x28032000 0 0x1000>; 307 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&i2c2_pins>; 310 clock-frequency = <400000>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clocks = <&pismu TMPV770X_CLK_PII2C2>; 314 status = "disabled"; 315 }; 316 317 i2c3: i2c@28033000 { 318 compatible = "snps,designware-i2c"; 319 reg = <0 0x28033000 0 0x1000>; 320 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&i2c3_pins>; 323 clock-frequency = <400000>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 clocks = <&pismu TMPV770X_CLK_PII2C3>; 327 status = "disabled"; 328 }; 329 330 i2c4: i2c@28034000 { 331 compatible = "snps,designware-i2c"; 332 reg = <0 0x28034000 0 0x1000>; 333 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&i2c4_pins>; 336 clock-frequency = <400000>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 clocks = <&pismu TMPV770X_CLK_PII2C4>; 340 status = "disabled"; 341 }; 342 343 i2c5: i2c@28035000 { 344 compatible = "snps,designware-i2c"; 345 reg = <0 0x28035000 0 0x1000>; 346 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 347 pinctrl-names = "default"; 348 pinctrl-0 = <&i2c5_pins>; 349 clock-frequency = <400000>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 clocks = <&pismu TMPV770X_CLK_PII2C5>; 353 status = "disabled"; 354 }; 355 356 i2c6: i2c@28036000 { 357 compatible = "snps,designware-i2c"; 358 reg = <0 0x28036000 0 0x1000>; 359 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&i2c6_pins>; 362 clock-frequency = <400000>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 clocks = <&pismu TMPV770X_CLK_PII2C6>; 366 status = "disabled"; 367 }; 368 369 i2c7: i2c@28037000 { 370 compatible = "snps,designware-i2c"; 371 reg = <0 0x28037000 0 0x1000>; 372 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&i2c7_pins>; 375 clock-frequency = <400000>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&pismu TMPV770X_CLK_PII2C7>; 379 status = "disabled"; 380 }; 381 382 i2c8: i2c@28038000 { 383 compatible = "snps,designware-i2c"; 384 reg = <0 0x28038000 0 0x1000>; 385 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&i2c8_pins>; 388 clock-frequency = <400000>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&pismu TMPV770X_CLK_PII2C8>; 392 status = "disabled"; 393 }; 394 395 spi0: spi@28140000 { 396 compatible = "arm,pl022", "arm,primecell"; 397 reg = <0 0x28140000 0 0x1000>; 398 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&spi0_pins>; 401 num-cs = <1>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 }; 406 407 spi1: spi@28141000 { 408 compatible = "arm,pl022", "arm,primecell"; 409 reg = <0 0x28141000 0 0x1000>; 410 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&spi1_pins>; 413 num-cs = <1>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 }; 418 419 spi2: spi@28142000 { 420 compatible = "arm,pl022", "arm,primecell"; 421 reg = <0 0x28142000 0 0x1000>; 422 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&spi2_pins>; 425 num-cs = <1>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 spi3: spi@28143000 { 432 compatible = "arm,pl022", "arm,primecell"; 433 reg = <0 0x28143000 0 0x1000>; 434 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&spi3_pins>; 437 num-cs = <1>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 spi4: spi@28144000 { 444 compatible = "arm,pl022", "arm,primecell"; 445 reg = <0 0x28144000 0 0x1000>; 446 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&spi4_pins>; 449 num-cs = <1>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 455 spi5: spi@28145000 { 456 compatible = "arm,pl022", "arm,primecell"; 457 reg = <0 0x28145000 0 0x1000>; 458 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&spi5_pins>; 461 num-cs = <1>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 spi6: spi@28146000 { 468 compatible = "arm,pl022", "arm,primecell"; 469 reg = <0 0x28146000 0 0x1000>; 470 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&spi6_pins>; 473 num-cs = <1>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 status = "disabled"; 477 }; 478 479 piether: ethernet@28000000 { 480 compatible = "toshiba,visconti-dwmac", "snps,dwmac-4.20a"; 481 reg = <0 0x28000000 0 0x10000>; 482 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "macirq"; 484 snps,txpbl = <4>; 485 snps,rxpbl = <4>; 486 snps,tso; 487 status = "disabled"; 488 }; 489 490 wdt: wdt@28330000 { 491 compatible = "toshiba,visconti-wdt"; 492 reg = <0 0x28330000 0 0x1000>; 493 status = "disabled"; 494 }; 495 496 pwm: pwm@241c0000 { 497 compatible = "toshiba,visconti-pwm"; 498 reg = <0 0x241c0000 0 0x1000>; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&pwm_mux>; 501 #pwm-cells = <2>; 502 status = "disabled"; 503 }; 504 505 pcie: pcie@28400000 { 506 compatible = "toshiba,visconti-pcie"; 507 reg = <0x0 0x28400000 0x0 0x00400000>, 508 <0x0 0x70000000 0x0 0x10000000>, 509 <0x0 0x28050000 0x0 0x00010000>, 510 <0x0 0x24200000 0x0 0x00002000>, 511 <0x0 0x24162000 0x0 0x00001000>; 512 reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 513 device_type = "pci"; 514 bus-range = <0x00 0xff>; 515 num-lanes = <2>; 516 num-viewport = <8>; 517 518 #address-cells = <3>; 519 #size-cells = <2>; 520 #interrupt-cells = <1>; 521 ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000 522 0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 523 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 525 interrupt-names = "msi", "intr"; 526 interrupt-map-mask = <0 0 0 7>; 527 interrupt-map = 528 <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 529 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 530 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 531 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 532 max-link-speed = <2>; 533 status = "disabled"; 534 }; 535 }; 536}; 537 538#include "tmpv7708_pins.dtsi" 539