1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the TMPV7708 4 * 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 6 * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7 * 8 */ 9 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12 13/memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 14 15/ { 16 compatible = "toshiba,tmpv7708"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu-map { 25 cluster0 { 26 core0 { 27 cpu = <&cpu0>; 28 }; 29 core1 { 30 cpu = <&cpu1>; 31 }; 32 core2 { 33 cpu = <&cpu2>; 34 }; 35 core3 { 36 cpu = <&cpu3>; 37 }; 38 }; 39 40 cluster1 { 41 core0 { 42 cpu = <&cpu4>; 43 }; 44 core1 { 45 cpu = <&cpu5>; 46 }; 47 core2 { 48 cpu = <&cpu6>; 49 }; 50 core3 { 51 cpu = <&cpu7>; 52 }; 53 }; 54 }; 55 56 cpu0: cpu@0 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0x81100000>; 61 reg = <0x00>; 62 }; 63 64 cpu1: cpu@1 { 65 compatible = "arm,cortex-a53"; 66 device_type = "cpu"; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x0 0x81100000>; 69 reg = <0x01>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x0 0x81100000>; 77 reg = <0x02>; 78 }; 79 80 cpu3: cpu@3 { 81 compatible = "arm,cortex-a53"; 82 device_type = "cpu"; 83 enable-method = "spin-table"; 84 cpu-release-addr = <0x0 0x81100000>; 85 reg = <0x03>; 86 }; 87 88 cpu4: cpu@100 { 89 compatible = "arm,cortex-a53"; 90 device_type = "cpu"; 91 enable-method = "spin-table"; 92 cpu-release-addr = <0x0 0x81100000>; 93 reg = <0x100>; 94 }; 95 96 cpu5: cpu@101 { 97 compatible = "arm,cortex-a53"; 98 device_type = "cpu"; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0x0 0x81100000>; 101 reg = <0x101>; 102 }; 103 104 cpu6: cpu@102 { 105 compatible = "arm,cortex-a53"; 106 device_type = "cpu"; 107 enable-method = "spin-table"; 108 cpu-release-addr = <0x0 0x81100000>; 109 reg = <0x102>; 110 }; 111 112 cpu7: cpu@103 { 113 compatible = "arm,cortex-a53"; 114 device_type = "cpu"; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0x0 0x81100000>; 117 reg = <0x103>; 118 }; 119 }; 120 121 timer { 122 compatible = "arm,armv8-timer"; 123 interrupt-parent = <&gic>; 124 interrupts = 125 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 127 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 128 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 129 }; 130 131 uart_clk: uart-clk { 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 #clock-cells = <0>; 135 }; 136 137 wdt_clk: wdt-clk { 138 compatible = "fixed-clock"; 139 clock-frequency = <150000000>; 140 #clock-cells = <0>; 141 }; 142 143 soc { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 compatible = "simple-bus"; 147 interrupt-parent = <&gic>; 148 ranges; 149 150 gic: interrupt-controller@24001000 { 151 compatible = "arm,gic-400"; 152 interrupt-controller; 153 #interrupt-cells = <3>; 154 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 155 reg = <0 0x24001000 0 0x1000>, 156 <0 0x24002000 0 0x2000>, 157 <0 0x24004000 0 0x2000>, 158 <0 0x24006000 0 0x2000>; 159 }; 160 161 pmux: pmux@24190000 { 162 compatible = "toshiba,tmpv7708-pinctrl"; 163 reg = <0 0x24190000 0 0x10000>; 164 }; 165 166 gpio: gpio@28020000 { 167 compatible = "toshiba,gpio-tmpv7708"; 168 reg = <0 0x28020000 0 0x1000>; 169 #gpio-cells = <0x2>; 170 gpio-ranges = <&pmux 0 0 32>; 171 gpio-controller; 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 interrupt-parent = <&gic>; 175 }; 176 177 uart0: serial@28200000 { 178 compatible = "arm,pl011", "arm,primecell"; 179 reg = <0 0x28200000 0 0x1000>; 180 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&uart0_pins>; 183 status = "disabled"; 184 }; 185 186 uart1: serial@28201000 { 187 compatible = "arm,pl011", "arm,primecell"; 188 reg = <0 0x28201000 0 0x1000>; 189 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&uart1_pins>; 192 status = "disabled"; 193 }; 194 195 uart2: serial@28202000 { 196 compatible = "arm,pl011", "arm,primecell"; 197 reg = <0 0x28202000 0 0x1000>; 198 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&uart2_pins>; 201 status = "disabled"; 202 }; 203 204 uart3: serial@28203000 { 205 compatible = "arm,pl011", "arm,primecell"; 206 reg = <0 0x28203000 0 0x1000>; 207 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&uart3_pins>; 210 status = "disabled"; 211 }; 212 213 i2c0: i2c@28030000 { 214 compatible = "snps,designware-i2c"; 215 reg = <0 0x28030000 0 0x1000>; 216 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&i2c0_pins>; 219 clock-frequency = <400000>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 status = "disabled"; 223 }; 224 225 i2c1: i2c@28031000 { 226 compatible = "snps,designware-i2c"; 227 reg = <0 0x28031000 0 0x1000>; 228 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&i2c1_pins>; 231 clock-frequency = <400000>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 status = "disabled"; 235 }; 236 237 i2c2: i2c@28032000 { 238 compatible = "snps,designware-i2c"; 239 reg = <0 0x28032000 0 0x1000>; 240 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&i2c2_pins>; 243 clock-frequency = <400000>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 status = "disabled"; 247 }; 248 249 i2c3: i2c@28033000 { 250 compatible = "snps,designware-i2c"; 251 reg = <0 0x28033000 0 0x1000>; 252 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&i2c3_pins>; 255 clock-frequency = <400000>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 status = "disabled"; 259 }; 260 261 i2c4: i2c@28034000 { 262 compatible = "snps,designware-i2c"; 263 reg = <0 0x28034000 0 0x1000>; 264 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&i2c4_pins>; 267 clock-frequency = <400000>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 i2c5: i2c@28035000 { 274 compatible = "snps,designware-i2c"; 275 reg = <0 0x28035000 0 0x1000>; 276 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&i2c5_pins>; 279 clock-frequency = <400000>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 status = "disabled"; 283 }; 284 285 i2c6: i2c@28036000 { 286 compatible = "snps,designware-i2c"; 287 reg = <0 0x28036000 0 0x1000>; 288 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&i2c6_pins>; 291 clock-frequency = <400000>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 i2c7: i2c@28037000 { 298 compatible = "snps,designware-i2c"; 299 reg = <0 0x28037000 0 0x1000>; 300 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&i2c7_pins>; 303 clock-frequency = <400000>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 i2c8: i2c@28038000 { 310 compatible = "snps,designware-i2c"; 311 reg = <0 0x28038000 0 0x1000>; 312 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&i2c8_pins>; 315 clock-frequency = <400000>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 status = "disabled"; 319 }; 320 321 spi0: spi@28140000 { 322 compatible = "arm,pl022", "arm,primecell"; 323 reg = <0 0x28140000 0 0x1000>; 324 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&spi0_pins>; 327 num-cs = <1>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 status = "disabled"; 331 }; 332 333 spi1: spi@28141000 { 334 compatible = "arm,pl022", "arm,primecell"; 335 reg = <0 0x28141000 0 0x1000>; 336 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&spi1_pins>; 339 num-cs = <1>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 spi2: spi@28142000 { 346 compatible = "arm,pl022", "arm,primecell"; 347 reg = <0 0x28142000 0 0x1000>; 348 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&spi2_pins>; 351 num-cs = <1>; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 status = "disabled"; 355 }; 356 357 spi3: spi@28143000 { 358 compatible = "arm,pl022", "arm,primecell"; 359 reg = <0 0x28143000 0 0x1000>; 360 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&spi3_pins>; 363 num-cs = <1>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 status = "disabled"; 367 }; 368 369 spi4: spi@28144000 { 370 compatible = "arm,pl022", "arm,primecell"; 371 reg = <0 0x28144000 0 0x1000>; 372 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&spi4_pins>; 375 num-cs = <1>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 status = "disabled"; 379 }; 380 381 spi5: spi@28145000 { 382 compatible = "arm,pl022", "arm,primecell"; 383 reg = <0 0x28145000 0 0x1000>; 384 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&spi5_pins>; 387 num-cs = <1>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 spi6: spi@28146000 { 394 compatible = "arm,pl022", "arm,primecell"; 395 reg = <0 0x28146000 0 0x1000>; 396 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&spi6_pins>; 399 num-cs = <1>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 }; 404 405 wdt: wdt@28330000 { 406 compatible = "toshiba,visconti-wdt"; 407 reg = <0 0x28330000 0 0x1000>; 408 status = "disabled"; 409 }; 410 }; 411}; 412 413#include "tmpv7708_pins.dtsi" 414