1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721S2 SoC Family
4 *
5 * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28
6 *
7 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/soc/ti,sci_pm_domain.h>
14
15#include "k3-pinctrl.h"
16
17/ {
18
19	model = "Texas Instruments K3 J721S2 SoC";
20	compatible = "ti,j721s2";
21	interrupt-parent = <&gic500>;
22	#address-cells = <2>;
23	#size-cells = <2>;
24
25	chosen { };
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30		cpu-map {
31			cluster0: cluster0 {
32				core0 {
33					cpu = <&cpu0>;
34				};
35
36				core1 {
37					cpu = <&cpu1>;
38				};
39			};
40		};
41
42		cpu0: cpu@0 {
43			compatible = "arm,cortex-a72";
44			reg = <0x000>;
45			device_type = "cpu";
46			enable-method = "psci";
47			i-cache-size = <0xc000>;
48			i-cache-line-size = <64>;
49			i-cache-sets = <256>;
50			d-cache-size = <0x8000>;
51			d-cache-line-size = <64>;
52			d-cache-sets = <256>;
53			next-level-cache = <&L2_0>;
54		};
55
56		cpu1: cpu@1 {
57			compatible = "arm,cortex-a72";
58			reg = <0x001>;
59			device_type = "cpu";
60			enable-method = "psci";
61			i-cache-size = <0xc000>;
62			i-cache-line-size = <64>;
63			i-cache-sets = <256>;
64			d-cache-size = <0x8000>;
65			d-cache-line-size = <64>;
66			d-cache-sets = <256>;
67			next-level-cache = <&L2_0>;
68		};
69	};
70
71	L2_0: l2-cache0 {
72		compatible = "cache";
73		cache-unified;
74		cache-level = <2>;
75		cache-size = <0x100000>;
76		cache-line-size = <64>;
77		cache-sets = <1024>;
78		next-level-cache = <&msmc_l3>;
79	};
80
81	msmc_l3: l3-cache0 {
82		compatible = "cache";
83		cache-level = <3>;
84	};
85
86	firmware {
87		optee {
88			compatible = "linaro,optee-tz";
89			method = "smc";
90		};
91
92		psci: psci {
93			compatible = "arm,psci-1.0";
94			method = "smc";
95		};
96	};
97
98	a72_timer0: timer-cl0-cpu0 {
99		compatible = "arm,armv8-timer";
100		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
101			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
102			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
103			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
104
105	};
106
107	pmu: pmu {
108		compatible = "arm,cortex-a72-pmu";
109		/* Recommendation from GIC500 TRM Table A.3 */
110		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
111	};
112
113	cbass_main: bus@100000 {
114		compatible = "simple-bus";
115		#address-cells = <2>;
116		#size-cells = <2>;
117		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
118			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
119			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
120			 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/
121			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
122			 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
123			 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
124			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
125			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
126			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
127			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
128			 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
129
130			 /* MCUSS_WKUP Range */
131			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
132			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
133			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
134			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
135			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
136			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
137			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
138			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
139			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
140			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
141			 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
142			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
143			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
144
145		cbass_mcu_wakeup: bus@28380000 {
146			compatible = "simple-bus";
147			#address-cells = <2>;
148			#size-cells = <2>;
149			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
150				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
151				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
152				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
153				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
154				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
155				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
156				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
157				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
158				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
159				 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
160				 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
161				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
162
163		};
164
165	};
166};
167
168/* Now include peripherals from each bus segment */
169#include "k3-j721s2-main.dtsi"
170#include "k3-j721s2-mcu-wakeup.dtsi"
171