1b8545f9dSAswath Govindraju// SPDX-License-Identifier: GPL-2.0 2b8545f9dSAswath Govindraju/* 3b8545f9dSAswath Govindraju * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4b8545f9dSAswath Govindraju * 5b8545f9dSAswath Govindraju * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6b8545f9dSAswath Govindraju */ 7b8545f9dSAswath Govindraju 8393eee04SMatt Ranostay#include <dt-bindings/phy/phy-cadence.h> 9393eee04SMatt Ranostay#include <dt-bindings/phy/phy-ti.h> 10393eee04SMatt Ranostay 11393eee04SMatt Ranostay/ { 12393eee04SMatt Ranostay serdes_refclk: clock-cmnrefclk { 13393eee04SMatt Ranostay #clock-cells = <0>; 14393eee04SMatt Ranostay compatible = "fixed-clock"; 15393eee04SMatt Ranostay clock-frequency = <0>; 16393eee04SMatt Ranostay }; 17393eee04SMatt Ranostay}; 18393eee04SMatt Ranostay 19b8545f9dSAswath Govindraju&cbass_main { 20b8545f9dSAswath Govindraju msmc_ram: sram@70000000 { 21b8545f9dSAswath Govindraju compatible = "mmio-sram"; 22b8545f9dSAswath Govindraju reg = <0x0 0x70000000 0x0 0x400000>; 23b8545f9dSAswath Govindraju #address-cells = <1>; 24b8545f9dSAswath Govindraju #size-cells = <1>; 25b8545f9dSAswath Govindraju ranges = <0x0 0x0 0x70000000 0x400000>; 26b8545f9dSAswath Govindraju 27b8545f9dSAswath Govindraju atf-sram@0 { 28b8545f9dSAswath Govindraju reg = <0x0 0x20000>; 29b8545f9dSAswath Govindraju }; 30b8545f9dSAswath Govindraju 31b8545f9dSAswath Govindraju tifs-sram@1f0000 { 32b8545f9dSAswath Govindraju reg = <0x1f0000 0x10000>; 33b8545f9dSAswath Govindraju }; 34b8545f9dSAswath Govindraju 35b8545f9dSAswath Govindraju l3cache-sram@200000 { 36b8545f9dSAswath Govindraju reg = <0x200000 0x200000>; 37b8545f9dSAswath Govindraju }; 38b8545f9dSAswath Govindraju }; 39b8545f9dSAswath Govindraju 4020fcf9d6SAswath Govindraju scm_conf: syscon@104000 { 4120fcf9d6SAswath Govindraju compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 4220fcf9d6SAswath Govindraju reg = <0x00 0x00104000 0x00 0x18000>; 4320fcf9d6SAswath Govindraju #address-cells = <1>; 4420fcf9d6SAswath Govindraju #size-cells = <1>; 4520fcf9d6SAswath Govindraju ranges = <0x00 0x00 0x00104000 0x18000>; 4620fcf9d6SAswath Govindraju 4720fcf9d6SAswath Govindraju usb_serdes_mux: mux-controller@0 { 4820fcf9d6SAswath Govindraju compatible = "mmio-mux"; 4920fcf9d6SAswath Govindraju reg = <0x0 0x4>; 5020fcf9d6SAswath Govindraju #mux-control-cells = <1>; 5120fcf9d6SAswath Govindraju mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 5220fcf9d6SAswath Govindraju }; 53393eee04SMatt Ranostay 54393eee04SMatt Ranostay serdes_ln_ctrl: mux-controller@80 { 55393eee04SMatt Ranostay compatible = "mmio-mux"; 56393eee04SMatt Ranostay reg = <0x80 0x10>; 57393eee04SMatt Ranostay #mux-control-cells = <1>; 58393eee04SMatt Ranostay mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ 59393eee04SMatt Ranostay <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ 60393eee04SMatt Ranostay }; 6120fcf9d6SAswath Govindraju }; 6220fcf9d6SAswath Govindraju 63b8545f9dSAswath Govindraju gic500: interrupt-controller@1800000 { 64b8545f9dSAswath Govindraju compatible = "arm,gic-v3"; 65b8545f9dSAswath Govindraju #address-cells = <2>; 66b8545f9dSAswath Govindraju #size-cells = <2>; 67b8545f9dSAswath Govindraju ranges; 68b8545f9dSAswath Govindraju #interrupt-cells = <3>; 69b8545f9dSAswath Govindraju interrupt-controller; 70856216b7SMatt Ranostay reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 71a9668037SNishanth Menon <0x00 0x01900000 0x00 0x100000>, /* GICR */ 72a9668037SNishanth Menon <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 73a9668037SNishanth Menon <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 74a9668037SNishanth Menon <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 75b8545f9dSAswath Govindraju 76b8545f9dSAswath Govindraju /* vcpumntirq: virtual CPU interface maintenance interrupt */ 77b8545f9dSAswath Govindraju interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 78b8545f9dSAswath Govindraju 79b8545f9dSAswath Govindraju gic_its: msi-controller@1820000 { 80b8545f9dSAswath Govindraju compatible = "arm,gic-v3-its"; 81b8545f9dSAswath Govindraju reg = <0x00 0x01820000 0x00 0x10000>; 82b8545f9dSAswath Govindraju socionext,synquacer-pre-its = <0x1000000 0x400000>; 83b8545f9dSAswath Govindraju msi-controller; 84b8545f9dSAswath Govindraju #msi-cells = <1>; 85b8545f9dSAswath Govindraju }; 86b8545f9dSAswath Govindraju }; 87b8545f9dSAswath Govindraju 88b8545f9dSAswath Govindraju main_gpio_intr: interrupt-controller@a00000 { 89b8545f9dSAswath Govindraju compatible = "ti,sci-intr"; 90b8545f9dSAswath Govindraju reg = <0x00 0x00a00000 0x00 0x800>; 91b8545f9dSAswath Govindraju ti,intr-trigger-type = <1>; 92b8545f9dSAswath Govindraju interrupt-controller; 93b8545f9dSAswath Govindraju interrupt-parent = <&gic500>; 94b8545f9dSAswath Govindraju #interrupt-cells = <1>; 95b8545f9dSAswath Govindraju ti,sci = <&sms>; 96b8545f9dSAswath Govindraju ti,sci-dev-id = <148>; 97b8aa36c2SKeerthy ti,interrupt-ranges = <8 392 56>; 98b8545f9dSAswath Govindraju }; 99b8545f9dSAswath Govindraju 100b8545f9dSAswath Govindraju main_pmx0: pinctrl@11c000 { 101b8545f9dSAswath Govindraju compatible = "pinctrl-single"; 102b8545f9dSAswath Govindraju /* Proxy 0 addressing */ 103b8545f9dSAswath Govindraju reg = <0x0 0x11c000 0x0 0x120>; 104b8545f9dSAswath Govindraju #pinctrl-cells = <1>; 105b8545f9dSAswath Govindraju pinctrl-single,register-width = <32>; 106b8545f9dSAswath Govindraju pinctrl-single,function-mask = <0xffffffff>; 107b8545f9dSAswath Govindraju }; 108b8545f9dSAswath Govindraju 109027b85caSJayesh Choudhary main_crypto: crypto@4e00000 { 110027b85caSJayesh Choudhary compatible = "ti,j721e-sa2ul"; 111027b85caSJayesh Choudhary reg = <0x00 0x04e00000 0x00 0x1200>; 112027b85caSJayesh Choudhary power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 113027b85caSJayesh Choudhary #address-cells = <2>; 114027b85caSJayesh Choudhary #size-cells = <2>; 115027b85caSJayesh Choudhary ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 116027b85caSJayesh Choudhary 117027b85caSJayesh Choudhary dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 118027b85caSJayesh Choudhary <&main_udmap 0x4a41>; 119027b85caSJayesh Choudhary dma-names = "tx", "rx1", "rx2"; 120027b85caSJayesh Choudhary 121027b85caSJayesh Choudhary rng: rng@4e10000 { 122027b85caSJayesh Choudhary compatible = "inside-secure,safexcel-eip76"; 123027b85caSJayesh Choudhary reg = <0x00 0x04e10000 0x00 0x7d>; 124027b85caSJayesh Choudhary interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 125027b85caSJayesh Choudhary }; 126027b85caSJayesh Choudhary }; 127027b85caSJayesh Choudhary 128*835d0442SNishanth Menon main_timer0: timer@2400000 { 129*835d0442SNishanth Menon compatible = "ti,am654-timer"; 130*835d0442SNishanth Menon reg = <0x00 0x2400000 0x00 0x400>; 131*835d0442SNishanth Menon interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 132*835d0442SNishanth Menon clocks = <&k3_clks 63 1>; 133*835d0442SNishanth Menon clock-names = "fck"; 134*835d0442SNishanth Menon assigned-clocks = <&k3_clks 63 1>; 135*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 63 2>; 136*835d0442SNishanth Menon power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 137*835d0442SNishanth Menon ti,timer-pwm; 138*835d0442SNishanth Menon }; 139*835d0442SNishanth Menon 140*835d0442SNishanth Menon main_timer1: timer@2410000 { 141*835d0442SNishanth Menon compatible = "ti,am654-timer"; 142*835d0442SNishanth Menon reg = <0x00 0x2410000 0x00 0x400>; 143*835d0442SNishanth Menon interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 144*835d0442SNishanth Menon clocks = <&k3_clks 64 1>; 145*835d0442SNishanth Menon clock-names = "fck"; 146*835d0442SNishanth Menon assigned-clocks = <&k3_clks 64 1>; 147*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 64 2>; 148*835d0442SNishanth Menon power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 149*835d0442SNishanth Menon ti,timer-pwm; 150*835d0442SNishanth Menon }; 151*835d0442SNishanth Menon 152*835d0442SNishanth Menon main_timer2: timer@2420000 { 153*835d0442SNishanth Menon compatible = "ti,am654-timer"; 154*835d0442SNishanth Menon reg = <0x00 0x2420000 0x00 0x400>; 155*835d0442SNishanth Menon interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 156*835d0442SNishanth Menon clocks = <&k3_clks 65 1>; 157*835d0442SNishanth Menon clock-names = "fck"; 158*835d0442SNishanth Menon assigned-clocks = <&k3_clks 65 1>; 159*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 65 2>; 160*835d0442SNishanth Menon power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 161*835d0442SNishanth Menon ti,timer-pwm; 162*835d0442SNishanth Menon }; 163*835d0442SNishanth Menon 164*835d0442SNishanth Menon main_timer3: timer@2430000 { 165*835d0442SNishanth Menon compatible = "ti,am654-timer"; 166*835d0442SNishanth Menon reg = <0x00 0x2430000 0x00 0x400>; 167*835d0442SNishanth Menon interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 168*835d0442SNishanth Menon clocks = <&k3_clks 66 1>; 169*835d0442SNishanth Menon clock-names = "fck"; 170*835d0442SNishanth Menon assigned-clocks = <&k3_clks 66 1>; 171*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 66 2>; 172*835d0442SNishanth Menon power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 173*835d0442SNishanth Menon ti,timer-pwm; 174*835d0442SNishanth Menon }; 175*835d0442SNishanth Menon 176*835d0442SNishanth Menon main_timer4: timer@2440000 { 177*835d0442SNishanth Menon compatible = "ti,am654-timer"; 178*835d0442SNishanth Menon reg = <0x00 0x2440000 0x00 0x400>; 179*835d0442SNishanth Menon interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 180*835d0442SNishanth Menon clocks = <&k3_clks 67 1>; 181*835d0442SNishanth Menon clock-names = "fck"; 182*835d0442SNishanth Menon assigned-clocks = <&k3_clks 67 1>; 183*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 67 2>; 184*835d0442SNishanth Menon power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 185*835d0442SNishanth Menon ti,timer-pwm; 186*835d0442SNishanth Menon }; 187*835d0442SNishanth Menon 188*835d0442SNishanth Menon main_timer5: timer@2450000 { 189*835d0442SNishanth Menon compatible = "ti,am654-timer"; 190*835d0442SNishanth Menon reg = <0x00 0x2450000 0x00 0x400>; 191*835d0442SNishanth Menon interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 192*835d0442SNishanth Menon clocks = <&k3_clks 68 1>; 193*835d0442SNishanth Menon clock-names = "fck"; 194*835d0442SNishanth Menon assigned-clocks = <&k3_clks 68 1>; 195*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 68 2>; 196*835d0442SNishanth Menon power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 197*835d0442SNishanth Menon ti,timer-pwm; 198*835d0442SNishanth Menon }; 199*835d0442SNishanth Menon 200*835d0442SNishanth Menon main_timer6: timer@2460000 { 201*835d0442SNishanth Menon compatible = "ti,am654-timer"; 202*835d0442SNishanth Menon reg = <0x00 0x2460000 0x00 0x400>; 203*835d0442SNishanth Menon interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 204*835d0442SNishanth Menon clocks = <&k3_clks 69 1>; 205*835d0442SNishanth Menon clock-names = "fck"; 206*835d0442SNishanth Menon assigned-clocks = <&k3_clks 69 1>; 207*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 69 2>; 208*835d0442SNishanth Menon power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 209*835d0442SNishanth Menon ti,timer-pwm; 210*835d0442SNishanth Menon }; 211*835d0442SNishanth Menon 212*835d0442SNishanth Menon main_timer7: timer@2470000 { 213*835d0442SNishanth Menon compatible = "ti,am654-timer"; 214*835d0442SNishanth Menon reg = <0x00 0x2470000 0x00 0x400>; 215*835d0442SNishanth Menon interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 216*835d0442SNishanth Menon clocks = <&k3_clks 70 1>; 217*835d0442SNishanth Menon clock-names = "fck"; 218*835d0442SNishanth Menon assigned-clocks = <&k3_clks 70 1>; 219*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 70 2>; 220*835d0442SNishanth Menon power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 221*835d0442SNishanth Menon ti,timer-pwm; 222*835d0442SNishanth Menon }; 223*835d0442SNishanth Menon 224*835d0442SNishanth Menon main_timer8: timer@2480000 { 225*835d0442SNishanth Menon compatible = "ti,am654-timer"; 226*835d0442SNishanth Menon reg = <0x00 0x2480000 0x00 0x400>; 227*835d0442SNishanth Menon interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 228*835d0442SNishanth Menon clocks = <&k3_clks 71 1>; 229*835d0442SNishanth Menon clock-names = "fck"; 230*835d0442SNishanth Menon assigned-clocks = <&k3_clks 71 1>; 231*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 71 2>; 232*835d0442SNishanth Menon power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 233*835d0442SNishanth Menon ti,timer-pwm; 234*835d0442SNishanth Menon }; 235*835d0442SNishanth Menon 236*835d0442SNishanth Menon main_timer9: timer@2490000 { 237*835d0442SNishanth Menon compatible = "ti,am654-timer"; 238*835d0442SNishanth Menon reg = <0x00 0x2490000 0x00 0x400>; 239*835d0442SNishanth Menon interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 240*835d0442SNishanth Menon clocks = <&k3_clks 72 1>; 241*835d0442SNishanth Menon clock-names = "fck"; 242*835d0442SNishanth Menon assigned-clocks = <&k3_clks 72 1>; 243*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 72 2>; 244*835d0442SNishanth Menon power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 245*835d0442SNishanth Menon ti,timer-pwm; 246*835d0442SNishanth Menon }; 247*835d0442SNishanth Menon 248*835d0442SNishanth Menon main_timer10: timer@24a0000 { 249*835d0442SNishanth Menon compatible = "ti,am654-timer"; 250*835d0442SNishanth Menon reg = <0x00 0x24a0000 0x00 0x400>; 251*835d0442SNishanth Menon interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 252*835d0442SNishanth Menon clocks = <&k3_clks 73 1>; 253*835d0442SNishanth Menon clock-names = "fck"; 254*835d0442SNishanth Menon assigned-clocks = <&k3_clks 73 1>; 255*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 73 2>; 256*835d0442SNishanth Menon power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 257*835d0442SNishanth Menon ti,timer-pwm; 258*835d0442SNishanth Menon }; 259*835d0442SNishanth Menon 260*835d0442SNishanth Menon main_timer11: timer@24b0000 { 261*835d0442SNishanth Menon compatible = "ti,am654-timer"; 262*835d0442SNishanth Menon reg = <0x00 0x24b0000 0x00 0x400>; 263*835d0442SNishanth Menon interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 264*835d0442SNishanth Menon clocks = <&k3_clks 74 1>; 265*835d0442SNishanth Menon clock-names = "fck"; 266*835d0442SNishanth Menon assigned-clocks = <&k3_clks 74 1>; 267*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 74 2>; 268*835d0442SNishanth Menon power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 269*835d0442SNishanth Menon ti,timer-pwm; 270*835d0442SNishanth Menon }; 271*835d0442SNishanth Menon 272*835d0442SNishanth Menon main_timer12: timer@24c0000 { 273*835d0442SNishanth Menon compatible = "ti,am654-timer"; 274*835d0442SNishanth Menon reg = <0x00 0x24c0000 0x00 0x400>; 275*835d0442SNishanth Menon interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 276*835d0442SNishanth Menon clocks = <&k3_clks 75 1>; 277*835d0442SNishanth Menon clock-names = "fck"; 278*835d0442SNishanth Menon assigned-clocks = <&k3_clks 75 1>; 279*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 75 2>; 280*835d0442SNishanth Menon power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 281*835d0442SNishanth Menon ti,timer-pwm; 282*835d0442SNishanth Menon }; 283*835d0442SNishanth Menon 284*835d0442SNishanth Menon main_timer13: timer@24d0000 { 285*835d0442SNishanth Menon compatible = "ti,am654-timer"; 286*835d0442SNishanth Menon reg = <0x00 0x24d0000 0x00 0x400>; 287*835d0442SNishanth Menon interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 288*835d0442SNishanth Menon clocks = <&k3_clks 76 1>; 289*835d0442SNishanth Menon clock-names = "fck"; 290*835d0442SNishanth Menon assigned-clocks = <&k3_clks 76 1>; 291*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 76 2>; 292*835d0442SNishanth Menon power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 293*835d0442SNishanth Menon ti,timer-pwm; 294*835d0442SNishanth Menon }; 295*835d0442SNishanth Menon 296*835d0442SNishanth Menon main_timer14: timer@24e0000 { 297*835d0442SNishanth Menon compatible = "ti,am654-timer"; 298*835d0442SNishanth Menon reg = <0x00 0x24e0000 0x00 0x400>; 299*835d0442SNishanth Menon interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 300*835d0442SNishanth Menon clocks = <&k3_clks 77 1>; 301*835d0442SNishanth Menon clock-names = "fck"; 302*835d0442SNishanth Menon assigned-clocks = <&k3_clks 77 1>; 303*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 77 2>; 304*835d0442SNishanth Menon power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 305*835d0442SNishanth Menon ti,timer-pwm; 306*835d0442SNishanth Menon }; 307*835d0442SNishanth Menon 308*835d0442SNishanth Menon main_timer15: timer@24f0000 { 309*835d0442SNishanth Menon compatible = "ti,am654-timer"; 310*835d0442SNishanth Menon reg = <0x00 0x24f0000 0x00 0x400>; 311*835d0442SNishanth Menon interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 312*835d0442SNishanth Menon clocks = <&k3_clks 78 1>; 313*835d0442SNishanth Menon clock-names = "fck"; 314*835d0442SNishanth Menon assigned-clocks = <&k3_clks 78 1>; 315*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 78 2>; 316*835d0442SNishanth Menon power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 317*835d0442SNishanth Menon ti,timer-pwm; 318*835d0442SNishanth Menon }; 319*835d0442SNishanth Menon 320*835d0442SNishanth Menon main_timer16: timer@2500000 { 321*835d0442SNishanth Menon compatible = "ti,am654-timer"; 322*835d0442SNishanth Menon reg = <0x00 0x2500000 0x00 0x400>; 323*835d0442SNishanth Menon interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 324*835d0442SNishanth Menon clocks = <&k3_clks 79 1>; 325*835d0442SNishanth Menon clock-names = "fck"; 326*835d0442SNishanth Menon assigned-clocks = <&k3_clks 79 1>; 327*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 79 2>; 328*835d0442SNishanth Menon power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 329*835d0442SNishanth Menon ti,timer-pwm; 330*835d0442SNishanth Menon }; 331*835d0442SNishanth Menon 332*835d0442SNishanth Menon main_timer17: timer@2510000 { 333*835d0442SNishanth Menon compatible = "ti,am654-timer"; 334*835d0442SNishanth Menon reg = <0x00 0x2510000 0x00 0x400>; 335*835d0442SNishanth Menon interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 336*835d0442SNishanth Menon clocks = <&k3_clks 80 1>; 337*835d0442SNishanth Menon clock-names = "fck"; 338*835d0442SNishanth Menon assigned-clocks = <&k3_clks 80 1>; 339*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 80 2>; 340*835d0442SNishanth Menon power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 341*835d0442SNishanth Menon ti,timer-pwm; 342*835d0442SNishanth Menon }; 343*835d0442SNishanth Menon 344*835d0442SNishanth Menon main_timer18: timer@2520000 { 345*835d0442SNishanth Menon compatible = "ti,am654-timer"; 346*835d0442SNishanth Menon reg = <0x00 0x2520000 0x00 0x400>; 347*835d0442SNishanth Menon interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 348*835d0442SNishanth Menon clocks = <&k3_clks 81 1>; 349*835d0442SNishanth Menon clock-names = "fck"; 350*835d0442SNishanth Menon assigned-clocks = <&k3_clks 81 1>; 351*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 81 2>; 352*835d0442SNishanth Menon power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 353*835d0442SNishanth Menon ti,timer-pwm; 354*835d0442SNishanth Menon }; 355*835d0442SNishanth Menon 356*835d0442SNishanth Menon main_timer19: timer@2530000 { 357*835d0442SNishanth Menon compatible = "ti,am654-timer"; 358*835d0442SNishanth Menon reg = <0x00 0x2530000 0x00 0x400>; 359*835d0442SNishanth Menon interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 360*835d0442SNishanth Menon clocks = <&k3_clks 82 1>; 361*835d0442SNishanth Menon clock-names = "fck"; 362*835d0442SNishanth Menon assigned-clocks = <&k3_clks 82 1>; 363*835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 82 2>; 364*835d0442SNishanth Menon power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 365*835d0442SNishanth Menon ti,timer-pwm; 366*835d0442SNishanth Menon }; 367*835d0442SNishanth Menon 368b8545f9dSAswath Govindraju main_uart0: serial@2800000 { 369b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 370b8545f9dSAswath Govindraju reg = <0x00 0x02800000 0x00 0x200>; 371b8545f9dSAswath Govindraju interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 372b8545f9dSAswath Govindraju current-speed = <115200>; 373b8545f9dSAswath Govindraju clocks = <&k3_clks 146 3>; 374b8545f9dSAswath Govindraju clock-names = "fclk"; 375b8545f9dSAswath Govindraju power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 3760e63f35aSAndrew Davis status = "disabled"; 377b8545f9dSAswath Govindraju }; 378b8545f9dSAswath Govindraju 379b8545f9dSAswath Govindraju main_uart1: serial@2810000 { 380b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 381b8545f9dSAswath Govindraju reg = <0x00 0x02810000 0x00 0x200>; 382b8545f9dSAswath Govindraju interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 383b8545f9dSAswath Govindraju current-speed = <115200>; 384b8545f9dSAswath Govindraju clocks = <&k3_clks 350 3>; 385b8545f9dSAswath Govindraju clock-names = "fclk"; 386b8545f9dSAswath Govindraju power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 3870e63f35aSAndrew Davis status = "disabled"; 388b8545f9dSAswath Govindraju }; 389b8545f9dSAswath Govindraju 390b8545f9dSAswath Govindraju main_uart2: serial@2820000 { 391b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 392b8545f9dSAswath Govindraju reg = <0x00 0x02820000 0x00 0x200>; 393b8545f9dSAswath Govindraju interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 394b8545f9dSAswath Govindraju current-speed = <115200>; 395b8545f9dSAswath Govindraju clocks = <&k3_clks 351 3>; 396b8545f9dSAswath Govindraju clock-names = "fclk"; 397b8545f9dSAswath Govindraju power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 3980e63f35aSAndrew Davis status = "disabled"; 399b8545f9dSAswath Govindraju }; 400b8545f9dSAswath Govindraju 401b8545f9dSAswath Govindraju main_uart3: serial@2830000 { 402b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 403b8545f9dSAswath Govindraju reg = <0x00 0x02830000 0x00 0x200>; 404b8545f9dSAswath Govindraju interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 405b8545f9dSAswath Govindraju current-speed = <115200>; 406b8545f9dSAswath Govindraju clocks = <&k3_clks 352 3>; 407b8545f9dSAswath Govindraju clock-names = "fclk"; 408b8545f9dSAswath Govindraju power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 4090e63f35aSAndrew Davis status = "disabled"; 410b8545f9dSAswath Govindraju }; 411b8545f9dSAswath Govindraju 412b8545f9dSAswath Govindraju main_uart4: serial@2840000 { 413b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 414b8545f9dSAswath Govindraju reg = <0x00 0x02840000 0x00 0x200>; 415b8545f9dSAswath Govindraju interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 416b8545f9dSAswath Govindraju current-speed = <115200>; 417b8545f9dSAswath Govindraju clocks = <&k3_clks 353 3>; 418b8545f9dSAswath Govindraju clock-names = "fclk"; 419b8545f9dSAswath Govindraju power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 4200e63f35aSAndrew Davis status = "disabled"; 421b8545f9dSAswath Govindraju }; 422b8545f9dSAswath Govindraju 423b8545f9dSAswath Govindraju main_uart5: serial@2850000 { 424b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 425b8545f9dSAswath Govindraju reg = <0x00 0x02850000 0x00 0x200>; 426b8545f9dSAswath Govindraju interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 427b8545f9dSAswath Govindraju current-speed = <115200>; 428b8545f9dSAswath Govindraju clocks = <&k3_clks 354 3>; 429b8545f9dSAswath Govindraju clock-names = "fclk"; 430b8545f9dSAswath Govindraju power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 4310e63f35aSAndrew Davis status = "disabled"; 432b8545f9dSAswath Govindraju }; 433b8545f9dSAswath Govindraju 434b8545f9dSAswath Govindraju main_uart6: serial@2860000 { 435b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 436b8545f9dSAswath Govindraju reg = <0x00 0x02860000 0x00 0x200>; 437b8545f9dSAswath Govindraju interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 438b8545f9dSAswath Govindraju current-speed = <115200>; 439b8545f9dSAswath Govindraju clocks = <&k3_clks 355 3>; 440b8545f9dSAswath Govindraju clock-names = "fclk"; 441b8545f9dSAswath Govindraju power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 4420e63f35aSAndrew Davis status = "disabled"; 443b8545f9dSAswath Govindraju }; 444b8545f9dSAswath Govindraju 445b8545f9dSAswath Govindraju main_uart7: serial@2870000 { 446b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 447b8545f9dSAswath Govindraju reg = <0x00 0x02870000 0x00 0x200>; 448b8545f9dSAswath Govindraju interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 449b8545f9dSAswath Govindraju current-speed = <115200>; 450b8545f9dSAswath Govindraju clocks = <&k3_clks 356 3>; 451b8545f9dSAswath Govindraju clock-names = "fclk"; 452b8545f9dSAswath Govindraju power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 4530e63f35aSAndrew Davis status = "disabled"; 454b8545f9dSAswath Govindraju }; 455b8545f9dSAswath Govindraju 456b8545f9dSAswath Govindraju main_uart8: serial@2880000 { 457b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 458b8545f9dSAswath Govindraju reg = <0x00 0x02880000 0x00 0x200>; 459b8545f9dSAswath Govindraju interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 460b8545f9dSAswath Govindraju current-speed = <115200>; 461b8545f9dSAswath Govindraju clocks = <&k3_clks 357 3>; 462b8545f9dSAswath Govindraju clock-names = "fclk"; 463b8545f9dSAswath Govindraju power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 4640e63f35aSAndrew Davis status = "disabled"; 465b8545f9dSAswath Govindraju }; 466b8545f9dSAswath Govindraju 467b8545f9dSAswath Govindraju main_uart9: serial@2890000 { 468b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 469b8545f9dSAswath Govindraju reg = <0x00 0x02890000 0x00 0x200>; 470b8545f9dSAswath Govindraju interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 471b8545f9dSAswath Govindraju current-speed = <115200>; 472b8545f9dSAswath Govindraju clocks = <&k3_clks 358 3>; 473b8545f9dSAswath Govindraju clock-names = "fclk"; 474b8545f9dSAswath Govindraju power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 4750e63f35aSAndrew Davis status = "disabled"; 476b8545f9dSAswath Govindraju }; 477b8545f9dSAswath Govindraju 478b8545f9dSAswath Govindraju main_gpio0: gpio@600000 { 479b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 480b8545f9dSAswath Govindraju reg = <0x00 0x00600000 0x00 0x100>; 481b8545f9dSAswath Govindraju gpio-controller; 482b8545f9dSAswath Govindraju #gpio-cells = <2>; 483b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 484b8545f9dSAswath Govindraju interrupts = <145>, <146>, <147>, <148>, <149>; 485b8545f9dSAswath Govindraju interrupt-controller; 486b8545f9dSAswath Govindraju #interrupt-cells = <2>; 487b8545f9dSAswath Govindraju ti,ngpio = <66>; 488b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 489b8545f9dSAswath Govindraju power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 490b8545f9dSAswath Govindraju clocks = <&k3_clks 111 0>; 491b8545f9dSAswath Govindraju clock-names = "gpio"; 492b8545f9dSAswath Govindraju }; 493b8545f9dSAswath Govindraju 494b8545f9dSAswath Govindraju main_gpio2: gpio@610000 { 495b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 496b8545f9dSAswath Govindraju reg = <0x00 0x00610000 0x00 0x100>; 497b8545f9dSAswath Govindraju gpio-controller; 498b8545f9dSAswath Govindraju #gpio-cells = <2>; 499b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 500b8545f9dSAswath Govindraju interrupts = <154>, <155>, <156>, <157>, <158>; 501b8545f9dSAswath Govindraju interrupt-controller; 502b8545f9dSAswath Govindraju #interrupt-cells = <2>; 503b8545f9dSAswath Govindraju ti,ngpio = <66>; 504b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 505b8545f9dSAswath Govindraju power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 506b8545f9dSAswath Govindraju clocks = <&k3_clks 112 0>; 507b8545f9dSAswath Govindraju clock-names = "gpio"; 508b8545f9dSAswath Govindraju }; 509b8545f9dSAswath Govindraju 510b8545f9dSAswath Govindraju main_gpio4: gpio@620000 { 511b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 512b8545f9dSAswath Govindraju reg = <0x00 0x00620000 0x00 0x100>; 513b8545f9dSAswath Govindraju gpio-controller; 514b8545f9dSAswath Govindraju #gpio-cells = <2>; 515b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 516b8545f9dSAswath Govindraju interrupts = <163>, <164>, <165>, <166>, <167>; 517b8545f9dSAswath Govindraju interrupt-controller; 518b8545f9dSAswath Govindraju #interrupt-cells = <2>; 519b8545f9dSAswath Govindraju ti,ngpio = <66>; 520b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 521b8545f9dSAswath Govindraju power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 522b8545f9dSAswath Govindraju clocks = <&k3_clks 113 0>; 523b8545f9dSAswath Govindraju clock-names = "gpio"; 524b8545f9dSAswath Govindraju }; 525b8545f9dSAswath Govindraju 526b8545f9dSAswath Govindraju main_gpio6: gpio@630000 { 527b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 528b8545f9dSAswath Govindraju reg = <0x00 0x00630000 0x00 0x100>; 529b8545f9dSAswath Govindraju gpio-controller; 530b8545f9dSAswath Govindraju #gpio-cells = <2>; 531b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 532b8545f9dSAswath Govindraju interrupts = <172>, <173>, <174>, <175>, <176>; 533b8545f9dSAswath Govindraju interrupt-controller; 534b8545f9dSAswath Govindraju #interrupt-cells = <2>; 535b8545f9dSAswath Govindraju ti,ngpio = <66>; 536b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 537b8545f9dSAswath Govindraju power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 538b8545f9dSAswath Govindraju clocks = <&k3_clks 114 0>; 539b8545f9dSAswath Govindraju clock-names = "gpio"; 540b8545f9dSAswath Govindraju }; 541b8545f9dSAswath Govindraju 542b8545f9dSAswath Govindraju main_i2c0: i2c@2000000 { 543b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 544b8545f9dSAswath Govindraju reg = <0x00 0x02000000 0x00 0x100>; 545b8545f9dSAswath Govindraju interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 546b8545f9dSAswath Govindraju #address-cells = <1>; 547b8545f9dSAswath Govindraju #size-cells = <0>; 548b8545f9dSAswath Govindraju clocks = <&k3_clks 214 1>; 549b8545f9dSAswath Govindraju clock-names = "fck"; 550b8545f9dSAswath Govindraju power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 551b8545f9dSAswath Govindraju }; 552b8545f9dSAswath Govindraju 553b8545f9dSAswath Govindraju main_i2c1: i2c@2010000 { 554b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 555b8545f9dSAswath Govindraju reg = <0x00 0x02010000 0x00 0x100>; 556b8545f9dSAswath Govindraju interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 557b8545f9dSAswath Govindraju #address-cells = <1>; 558b8545f9dSAswath Govindraju #size-cells = <0>; 559b8545f9dSAswath Govindraju clocks = <&k3_clks 215 1>; 560b8545f9dSAswath Govindraju clock-names = "fck"; 561b8545f9dSAswath Govindraju power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 5620aef5131SAndrew Davis status = "disabled"; 563b8545f9dSAswath Govindraju }; 564b8545f9dSAswath Govindraju 565b8545f9dSAswath Govindraju main_i2c2: i2c@2020000 { 566b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 567b8545f9dSAswath Govindraju reg = <0x00 0x02020000 0x00 0x100>; 568b8545f9dSAswath Govindraju interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 569b8545f9dSAswath Govindraju #address-cells = <1>; 570b8545f9dSAswath Govindraju #size-cells = <0>; 571b8545f9dSAswath Govindraju clocks = <&k3_clks 216 1>; 572b8545f9dSAswath Govindraju clock-names = "fck"; 573b8545f9dSAswath Govindraju power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 5740aef5131SAndrew Davis status = "disabled"; 575b8545f9dSAswath Govindraju }; 576b8545f9dSAswath Govindraju 577b8545f9dSAswath Govindraju main_i2c3: i2c@2030000 { 578b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 579b8545f9dSAswath Govindraju reg = <0x00 0x02030000 0x00 0x100>; 580b8545f9dSAswath Govindraju interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 581b8545f9dSAswath Govindraju #address-cells = <1>; 582b8545f9dSAswath Govindraju #size-cells = <0>; 583b8545f9dSAswath Govindraju clocks = <&k3_clks 217 1>; 584b8545f9dSAswath Govindraju clock-names = "fck"; 585b8545f9dSAswath Govindraju power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 5860aef5131SAndrew Davis status = "disabled"; 587b8545f9dSAswath Govindraju }; 588b8545f9dSAswath Govindraju 589b8545f9dSAswath Govindraju main_i2c4: i2c@2040000 { 590b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 591b8545f9dSAswath Govindraju reg = <0x00 0x02040000 0x00 0x100>; 592b8545f9dSAswath Govindraju interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 593b8545f9dSAswath Govindraju #address-cells = <1>; 594b8545f9dSAswath Govindraju #size-cells = <0>; 595b8545f9dSAswath Govindraju clocks = <&k3_clks 218 1>; 596b8545f9dSAswath Govindraju clock-names = "fck"; 597b8545f9dSAswath Govindraju power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 5980aef5131SAndrew Davis status = "disabled"; 599b8545f9dSAswath Govindraju }; 600b8545f9dSAswath Govindraju 601b8545f9dSAswath Govindraju main_i2c5: i2c@2050000 { 602b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 603b8545f9dSAswath Govindraju reg = <0x00 0x02050000 0x00 0x100>; 604b8545f9dSAswath Govindraju interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 605b8545f9dSAswath Govindraju #address-cells = <1>; 606b8545f9dSAswath Govindraju #size-cells = <0>; 607b8545f9dSAswath Govindraju clocks = <&k3_clks 219 1>; 608b8545f9dSAswath Govindraju clock-names = "fck"; 609b8545f9dSAswath Govindraju power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 6100aef5131SAndrew Davis status = "disabled"; 611b8545f9dSAswath Govindraju }; 612b8545f9dSAswath Govindraju 613b8545f9dSAswath Govindraju main_i2c6: i2c@2060000 { 614b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 615b8545f9dSAswath Govindraju reg = <0x00 0x02060000 0x00 0x100>; 616b8545f9dSAswath Govindraju interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 617b8545f9dSAswath Govindraju #address-cells = <1>; 618b8545f9dSAswath Govindraju #size-cells = <0>; 619b8545f9dSAswath Govindraju clocks = <&k3_clks 220 1>; 620b8545f9dSAswath Govindraju clock-names = "fck"; 621b8545f9dSAswath Govindraju power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 6220aef5131SAndrew Davis status = "disabled"; 623b8545f9dSAswath Govindraju }; 624b8545f9dSAswath Govindraju 625b8545f9dSAswath Govindraju main_sdhci0: mmc@4f80000 { 626b8545f9dSAswath Govindraju compatible = "ti,j721e-sdhci-8bit"; 627b8545f9dSAswath Govindraju reg = <0x00 0x04f80000 0x00 0x1000>, 628b8545f9dSAswath Govindraju <0x00 0x04f88000 0x00 0x400>; 629b8545f9dSAswath Govindraju interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 630b8545f9dSAswath Govindraju power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 631b8545f9dSAswath Govindraju clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 632b8545f9dSAswath Govindraju clock-names = "clk_ahb", "clk_xin"; 633b8545f9dSAswath Govindraju assigned-clocks = <&k3_clks 98 1>; 634b8545f9dSAswath Govindraju assigned-clock-parents = <&k3_clks 98 2>; 635b8545f9dSAswath Govindraju bus-width = <8>; 636b8545f9dSAswath Govindraju ti,otap-del-sel-legacy = <0x0>; 637b8545f9dSAswath Govindraju ti,otap-del-sel-mmc-hs = <0x0>; 638b8545f9dSAswath Govindraju ti,otap-del-sel-ddr52 = <0x6>; 639b8545f9dSAswath Govindraju ti,otap-del-sel-hs200 = <0x8>; 640b8545f9dSAswath Govindraju ti,otap-del-sel-hs400 = <0x5>; 641b8545f9dSAswath Govindraju ti,itap-del-sel-legacy = <0x10>; 642b8545f9dSAswath Govindraju ti,itap-del-sel-mmc-hs = <0xa>; 643b8545f9dSAswath Govindraju ti,strobe-sel = <0x77>; 644b8545f9dSAswath Govindraju ti,clkbuf-sel = <0x7>; 645b8545f9dSAswath Govindraju ti,trm-icp = <0x8>; 646b8545f9dSAswath Govindraju mmc-ddr-1_8v; 647b8545f9dSAswath Govindraju mmc-hs200-1_8v; 648b8545f9dSAswath Govindraju mmc-hs400-1_8v; 649b8545f9dSAswath Govindraju dma-coherent; 650b8545f9dSAswath Govindraju }; 651b8545f9dSAswath Govindraju 652b8545f9dSAswath Govindraju main_sdhci1: mmc@4fb0000 { 653b8545f9dSAswath Govindraju compatible = "ti,j721e-sdhci-4bit"; 654b8545f9dSAswath Govindraju reg = <0x00 0x04fb0000 0x00 0x1000>, 655b8545f9dSAswath Govindraju <0x00 0x04fb8000 0x00 0x400>; 656b8545f9dSAswath Govindraju interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 657b8545f9dSAswath Govindraju power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 658b8545f9dSAswath Govindraju clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 659b8545f9dSAswath Govindraju clock-names = "clk_ahb", "clk_xin"; 660b8545f9dSAswath Govindraju assigned-clocks = <&k3_clks 99 1>; 661b8545f9dSAswath Govindraju assigned-clock-parents = <&k3_clks 99 2>; 662b8545f9dSAswath Govindraju bus-width = <4>; 663b8545f9dSAswath Govindraju ti,otap-del-sel-legacy = <0x0>; 664b8545f9dSAswath Govindraju ti,otap-del-sel-sd-hs = <0x0>; 665b8545f9dSAswath Govindraju ti,otap-del-sel-sdr12 = <0xf>; 666b8545f9dSAswath Govindraju ti,otap-del-sel-sdr25 = <0xf>; 667b8545f9dSAswath Govindraju ti,otap-del-sel-sdr50 = <0xc>; 668b8545f9dSAswath Govindraju ti,otap-del-sel-sdr104 = <0x5>; 669b8545f9dSAswath Govindraju ti,otap-del-sel-ddr50 = <0xc>; 670b8545f9dSAswath Govindraju ti,itap-del-sel-legacy = <0x0>; 671b8545f9dSAswath Govindraju ti,itap-del-sel-sd-hs = <0x0>; 672b8545f9dSAswath Govindraju ti,itap-del-sel-sdr12 = <0x0>; 673b8545f9dSAswath Govindraju ti,itap-del-sel-sdr25 = <0x0>; 674b8545f9dSAswath Govindraju ti,clkbuf-sel = <0x7>; 675b8545f9dSAswath Govindraju ti,trm-icp = <0x8>; 676b8545f9dSAswath Govindraju dma-coherent; 677b8545f9dSAswath Govindraju /* Masking support for SDR104 capability */ 678b8545f9dSAswath Govindraju sdhci-caps-mask = <0x00000003 0x00000000>; 679b8545f9dSAswath Govindraju }; 680b8545f9dSAswath Govindraju 681b8545f9dSAswath Govindraju main_navss: bus@30000000 { 682b8545f9dSAswath Govindraju compatible = "simple-mfd"; 683b8545f9dSAswath Govindraju #address-cells = <2>; 684b8545f9dSAswath Govindraju #size-cells = <2>; 685b8545f9dSAswath Govindraju ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 686b8545f9dSAswath Govindraju ti,sci-dev-id = <224>; 687b8545f9dSAswath Govindraju dma-coherent; 688b8545f9dSAswath Govindraju dma-ranges; 689b8545f9dSAswath Govindraju 690b8545f9dSAswath Govindraju main_navss_intr: interrupt-controller@310e0000 { 691b8545f9dSAswath Govindraju compatible = "ti,sci-intr"; 692b8545f9dSAswath Govindraju reg = <0x00 0x310e0000 0x00 0x4000>; 693b8545f9dSAswath Govindraju ti,intr-trigger-type = <4>; 694b8545f9dSAswath Govindraju interrupt-controller; 695b8545f9dSAswath Govindraju interrupt-parent = <&gic500>; 696b8545f9dSAswath Govindraju #interrupt-cells = <1>; 697b8545f9dSAswath Govindraju ti,sci = <&sms>; 698b8545f9dSAswath Govindraju ti,sci-dev-id = <227>; 699b8545f9dSAswath Govindraju ti,interrupt-ranges = <0 64 64>, 700b8545f9dSAswath Govindraju <64 448 64>, 701b8545f9dSAswath Govindraju <128 672 64>; 702b8545f9dSAswath Govindraju }; 703b8545f9dSAswath Govindraju 704b8545f9dSAswath Govindraju main_udmass_inta: msi-controller@33d00000 { 705b8545f9dSAswath Govindraju compatible = "ti,sci-inta"; 706b8545f9dSAswath Govindraju reg = <0x00 0x33d00000 0x00 0x100000>; 707b8545f9dSAswath Govindraju interrupt-controller; 708b8545f9dSAswath Govindraju #interrupt-cells = <0>; 709b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 710b8545f9dSAswath Govindraju msi-controller; 711b8545f9dSAswath Govindraju ti,sci = <&sms>; 712b8545f9dSAswath Govindraju ti,sci-dev-id = <265>; 713b8545f9dSAswath Govindraju ti,interrupt-ranges = <0 0 256>; 714b8545f9dSAswath Govindraju }; 715b8545f9dSAswath Govindraju 716b8545f9dSAswath Govindraju secure_proxy_main: mailbox@32c00000 { 717b8545f9dSAswath Govindraju compatible = "ti,am654-secure-proxy"; 718b8545f9dSAswath Govindraju #mbox-cells = <1>; 719b8545f9dSAswath Govindraju reg-names = "target_data", "rt", "scfg"; 720b8545f9dSAswath Govindraju reg = <0x00 0x32c00000 0x00 0x100000>, 721b8545f9dSAswath Govindraju <0x00 0x32400000 0x00 0x100000>, 722b8545f9dSAswath Govindraju <0x00 0x32800000 0x00 0x100000>; 723b8545f9dSAswath Govindraju interrupt-names = "rx_011"; 724b8545f9dSAswath Govindraju interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 725b8545f9dSAswath Govindraju }; 726b8545f9dSAswath Govindraju 727b8545f9dSAswath Govindraju hwspinlock: spinlock@30e00000 { 728b8545f9dSAswath Govindraju compatible = "ti,am654-hwspinlock"; 729b8545f9dSAswath Govindraju reg = <0x00 0x30e00000 0x00 0x1000>; 730b8545f9dSAswath Govindraju #hwlock-cells = <1>; 731b8545f9dSAswath Govindraju }; 732b8545f9dSAswath Govindraju 733b8545f9dSAswath Govindraju mailbox0_cluster0: mailbox@31f80000 { 734b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 735b8545f9dSAswath Govindraju reg = <0x00 0x31f80000 0x00 0x200>; 736b8545f9dSAswath Govindraju #mbox-cells = <1>; 737b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 738b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 739b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7403fb0402fSAndrew Davis status = "disabled"; 741b8545f9dSAswath Govindraju }; 742b8545f9dSAswath Govindraju 743b8545f9dSAswath Govindraju mailbox0_cluster1: mailbox@31f81000 { 744b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 745b8545f9dSAswath Govindraju reg = <0x00 0x31f81000 0x00 0x200>; 746b8545f9dSAswath Govindraju #mbox-cells = <1>; 747b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 748b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 749b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7503fb0402fSAndrew Davis status = "disabled"; 751b8545f9dSAswath Govindraju }; 752b8545f9dSAswath Govindraju 753b8545f9dSAswath Govindraju mailbox0_cluster2: mailbox@31f82000 { 754b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 755b8545f9dSAswath Govindraju reg = <0x00 0x31f82000 0x00 0x200>; 756b8545f9dSAswath Govindraju #mbox-cells = <1>; 757b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 758b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 759b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7603fb0402fSAndrew Davis status = "disabled"; 761b8545f9dSAswath Govindraju }; 762b8545f9dSAswath Govindraju 763b8545f9dSAswath Govindraju mailbox0_cluster3: mailbox@31f83000 { 764b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 765b8545f9dSAswath Govindraju reg = <0x00 0x31f83000 0x00 0x200>; 766b8545f9dSAswath Govindraju #mbox-cells = <1>; 767b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 768b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 769b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7703fb0402fSAndrew Davis status = "disabled"; 771b8545f9dSAswath Govindraju }; 772b8545f9dSAswath Govindraju 773b8545f9dSAswath Govindraju mailbox0_cluster4: mailbox@31f84000 { 774b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 775b8545f9dSAswath Govindraju reg = <0x00 0x31f84000 0x00 0x200>; 776b8545f9dSAswath Govindraju #mbox-cells = <1>; 777b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 778b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 779b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7803fb0402fSAndrew Davis status = "disabled"; 781b8545f9dSAswath Govindraju }; 782b8545f9dSAswath Govindraju 783b8545f9dSAswath Govindraju mailbox0_cluster5: mailbox@31f85000 { 784b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 785b8545f9dSAswath Govindraju reg = <0x00 0x31f85000 0x00 0x200>; 786b8545f9dSAswath Govindraju #mbox-cells = <1>; 787b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 788b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 789b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7903fb0402fSAndrew Davis status = "disabled"; 791b8545f9dSAswath Govindraju }; 792b8545f9dSAswath Govindraju 793b8545f9dSAswath Govindraju mailbox0_cluster6: mailbox@31f86000 { 794b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 795b8545f9dSAswath Govindraju reg = <0x00 0x31f86000 0x00 0x200>; 796b8545f9dSAswath Govindraju #mbox-cells = <1>; 797b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 798b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 799b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8003fb0402fSAndrew Davis status = "disabled"; 801b8545f9dSAswath Govindraju }; 802b8545f9dSAswath Govindraju 803b8545f9dSAswath Govindraju mailbox0_cluster7: mailbox@31f87000 { 804b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 805b8545f9dSAswath Govindraju reg = <0x00 0x31f87000 0x00 0x200>; 806b8545f9dSAswath Govindraju #mbox-cells = <1>; 807b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 808b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 809b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8103fb0402fSAndrew Davis status = "disabled"; 811b8545f9dSAswath Govindraju }; 812b8545f9dSAswath Govindraju 813b8545f9dSAswath Govindraju mailbox0_cluster8: mailbox@31f88000 { 814b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 815b8545f9dSAswath Govindraju reg = <0x00 0x31f88000 0x00 0x200>; 816b8545f9dSAswath Govindraju #mbox-cells = <1>; 817b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 818b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 819b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8203fb0402fSAndrew Davis status = "disabled"; 821b8545f9dSAswath Govindraju }; 822b8545f9dSAswath Govindraju 823b8545f9dSAswath Govindraju mailbox0_cluster9: mailbox@31f89000 { 824b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 825b8545f9dSAswath Govindraju reg = <0x00 0x31f89000 0x00 0x200>; 826b8545f9dSAswath Govindraju #mbox-cells = <1>; 827b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 828b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 829b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8303fb0402fSAndrew Davis status = "disabled"; 831b8545f9dSAswath Govindraju }; 832b8545f9dSAswath Govindraju 833b8545f9dSAswath Govindraju mailbox0_cluster10: mailbox@31f8a000 { 834b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 835b8545f9dSAswath Govindraju reg = <0x00 0x31f8a000 0x00 0x200>; 836b8545f9dSAswath Govindraju #mbox-cells = <1>; 837b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 838b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 839b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8403fb0402fSAndrew Davis status = "disabled"; 841b8545f9dSAswath Govindraju }; 842b8545f9dSAswath Govindraju 843b8545f9dSAswath Govindraju mailbox0_cluster11: mailbox@31f8b000 { 844b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 845b8545f9dSAswath Govindraju reg = <0x00 0x31f8b000 0x00 0x200>; 846b8545f9dSAswath Govindraju #mbox-cells = <1>; 847b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 848b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 849b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8503fb0402fSAndrew Davis status = "disabled"; 851b8545f9dSAswath Govindraju }; 852b8545f9dSAswath Govindraju 853b8545f9dSAswath Govindraju mailbox1_cluster0: mailbox@31f90000 { 854b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 855b8545f9dSAswath Govindraju reg = <0x00 0x31f90000 0x00 0x200>; 856b8545f9dSAswath Govindraju #mbox-cells = <1>; 857b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 858b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 859b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8603fb0402fSAndrew Davis status = "disabled"; 861b8545f9dSAswath Govindraju }; 862b8545f9dSAswath Govindraju 863b8545f9dSAswath Govindraju mailbox1_cluster1: mailbox@31f91000 { 864b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 865b8545f9dSAswath Govindraju reg = <0x00 0x31f91000 0x00 0x200>; 866b8545f9dSAswath Govindraju #mbox-cells = <1>; 867b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 868b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 869b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8703fb0402fSAndrew Davis status = "disabled"; 871b8545f9dSAswath Govindraju }; 872b8545f9dSAswath Govindraju 873b8545f9dSAswath Govindraju mailbox1_cluster2: mailbox@31f92000 { 874b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 875b8545f9dSAswath Govindraju reg = <0x00 0x31f92000 0x00 0x200>; 876b8545f9dSAswath Govindraju #mbox-cells = <1>; 877b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 878b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 879b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8803fb0402fSAndrew Davis status = "disabled"; 881b8545f9dSAswath Govindraju }; 882b8545f9dSAswath Govindraju 883b8545f9dSAswath Govindraju mailbox1_cluster3: mailbox@31f93000 { 884b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 885b8545f9dSAswath Govindraju reg = <0x00 0x31f93000 0x00 0x200>; 886b8545f9dSAswath Govindraju #mbox-cells = <1>; 887b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 888b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 889b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8903fb0402fSAndrew Davis status = "disabled"; 891b8545f9dSAswath Govindraju }; 892b8545f9dSAswath Govindraju 893b8545f9dSAswath Govindraju mailbox1_cluster4: mailbox@31f94000 { 894b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 895b8545f9dSAswath Govindraju reg = <0x00 0x31f94000 0x00 0x200>; 896b8545f9dSAswath Govindraju #mbox-cells = <1>; 897b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 898b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 899b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9003fb0402fSAndrew Davis status = "disabled"; 901b8545f9dSAswath Govindraju }; 902b8545f9dSAswath Govindraju 903b8545f9dSAswath Govindraju mailbox1_cluster5: mailbox@31f95000 { 904b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 905b8545f9dSAswath Govindraju reg = <0x00 0x31f95000 0x00 0x200>; 906b8545f9dSAswath Govindraju #mbox-cells = <1>; 907b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 908b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 909b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9103fb0402fSAndrew Davis status = "disabled"; 911b8545f9dSAswath Govindraju }; 912b8545f9dSAswath Govindraju 913b8545f9dSAswath Govindraju mailbox1_cluster6: mailbox@31f96000 { 914b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 915b8545f9dSAswath Govindraju reg = <0x00 0x31f96000 0x00 0x200>; 916b8545f9dSAswath Govindraju #mbox-cells = <1>; 917b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 918b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 919b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9203fb0402fSAndrew Davis status = "disabled"; 921b8545f9dSAswath Govindraju }; 922b8545f9dSAswath Govindraju 923b8545f9dSAswath Govindraju mailbox1_cluster7: mailbox@31f97000 { 924b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 925b8545f9dSAswath Govindraju reg = <0x00 0x31f97000 0x00 0x200>; 926b8545f9dSAswath Govindraju #mbox-cells = <1>; 927b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 928b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 929b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9303fb0402fSAndrew Davis status = "disabled"; 931b8545f9dSAswath Govindraju }; 932b8545f9dSAswath Govindraju 933b8545f9dSAswath Govindraju mailbox1_cluster8: mailbox@31f98000 { 934b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 935b8545f9dSAswath Govindraju reg = <0x00 0x31f98000 0x00 0x200>; 936b8545f9dSAswath Govindraju #mbox-cells = <1>; 937b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 938b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 939b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9403fb0402fSAndrew Davis status = "disabled"; 941b8545f9dSAswath Govindraju }; 942b8545f9dSAswath Govindraju 943b8545f9dSAswath Govindraju mailbox1_cluster9: mailbox@31f99000 { 944b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 945b8545f9dSAswath Govindraju reg = <0x00 0x31f99000 0x00 0x200>; 946b8545f9dSAswath Govindraju #mbox-cells = <1>; 947b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 948b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 949b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9503fb0402fSAndrew Davis status = "disabled"; 951b8545f9dSAswath Govindraju }; 952b8545f9dSAswath Govindraju 953b8545f9dSAswath Govindraju mailbox1_cluster10: mailbox@31f9a000 { 954b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 955b8545f9dSAswath Govindraju reg = <0x00 0x31f9a000 0x00 0x200>; 956b8545f9dSAswath Govindraju #mbox-cells = <1>; 957b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 958b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 959b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9603fb0402fSAndrew Davis status = "disabled"; 961b8545f9dSAswath Govindraju }; 962b8545f9dSAswath Govindraju 963b8545f9dSAswath Govindraju mailbox1_cluster11: mailbox@31f9b000 { 964b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 965b8545f9dSAswath Govindraju reg = <0x00 0x31f9b000 0x00 0x200>; 966b8545f9dSAswath Govindraju #mbox-cells = <1>; 967b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 968b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 969b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9703fb0402fSAndrew Davis status = "disabled"; 971b8545f9dSAswath Govindraju }; 972b8545f9dSAswath Govindraju 973b8545f9dSAswath Govindraju main_ringacc: ringacc@3c000000 { 974b8545f9dSAswath Govindraju compatible = "ti,am654-navss-ringacc"; 975b8545f9dSAswath Govindraju reg = <0x0 0x3c000000 0x0 0x400000>, 976b8545f9dSAswath Govindraju <0x0 0x38000000 0x0 0x400000>, 977b8545f9dSAswath Govindraju <0x0 0x31120000 0x0 0x100>, 978b8545f9dSAswath Govindraju <0x0 0x33000000 0x0 0x40000>; 979b8545f9dSAswath Govindraju reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 980b8545f9dSAswath Govindraju ti,num-rings = <1024>; 981b8545f9dSAswath Govindraju ti,sci-rm-range-gp-rings = <0x1>; 982b8545f9dSAswath Govindraju ti,sci = <&sms>; 983b8545f9dSAswath Govindraju ti,sci-dev-id = <259>; 984b8545f9dSAswath Govindraju msi-parent = <&main_udmass_inta>; 985b8545f9dSAswath Govindraju }; 986b8545f9dSAswath Govindraju 987b8545f9dSAswath Govindraju main_udmap: dma-controller@31150000 { 988b8545f9dSAswath Govindraju compatible = "ti,j721e-navss-main-udmap"; 989b8545f9dSAswath Govindraju reg = <0x0 0x31150000 0x0 0x100>, 990b8545f9dSAswath Govindraju <0x0 0x34000000 0x0 0x80000>, 991b8545f9dSAswath Govindraju <0x0 0x35000000 0x0 0x200000>; 992b8545f9dSAswath Govindraju reg-names = "gcfg", "rchanrt", "tchanrt"; 993b8545f9dSAswath Govindraju msi-parent = <&main_udmass_inta>; 994b8545f9dSAswath Govindraju #dma-cells = <1>; 995b8545f9dSAswath Govindraju 996b8545f9dSAswath Govindraju ti,sci = <&sms>; 997b8545f9dSAswath Govindraju ti,sci-dev-id = <263>; 998b8545f9dSAswath Govindraju ti,ringacc = <&main_ringacc>; 999b8545f9dSAswath Govindraju 1000b8545f9dSAswath Govindraju ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1001b8545f9dSAswath Govindraju <0x0f>, /* TX_HCHAN */ 1002b8545f9dSAswath Govindraju <0x10>; /* TX_UHCHAN */ 1003b8545f9dSAswath Govindraju ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1004b8545f9dSAswath Govindraju <0x0b>, /* RX_HCHAN */ 1005b8545f9dSAswath Govindraju <0x0c>; /* RX_UHCHAN */ 1006b8545f9dSAswath Govindraju ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1007b8545f9dSAswath Govindraju }; 1008b8545f9dSAswath Govindraju 1009b8545f9dSAswath Govindraju cpts@310d0000 { 1010b8545f9dSAswath Govindraju compatible = "ti,j721e-cpts"; 1011b8545f9dSAswath Govindraju reg = <0x0 0x310d0000 0x0 0x400>; 1012b8545f9dSAswath Govindraju reg-names = "cpts"; 1013b8545f9dSAswath Govindraju clocks = <&k3_clks 226 5>; 1014b8545f9dSAswath Govindraju clock-names = "cpts"; 1015b8545f9dSAswath Govindraju interrupts-extended = <&main_navss_intr 391>; 1016b8545f9dSAswath Govindraju interrupt-names = "cpts"; 1017b8545f9dSAswath Govindraju ti,cpts-periodic-outputs = <6>; 1018b8545f9dSAswath Govindraju ti,cpts-ext-ts-inputs = <8>; 1019b8545f9dSAswath Govindraju }; 1020b8545f9dSAswath Govindraju }; 1021b8545f9dSAswath Govindraju 102220fcf9d6SAswath Govindraju usbss0: cdns-usb@4104000 { 102320fcf9d6SAswath Govindraju compatible = "ti,j721e-usb"; 102420fcf9d6SAswath Govindraju reg = <0x00 0x04104000 0x00 0x100>; 102520fcf9d6SAswath Govindraju clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 102620fcf9d6SAswath Govindraju clock-names = "ref", "lpm"; 102720fcf9d6SAswath Govindraju assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 102820fcf9d6SAswath Govindraju assigned-clock-parents = <&k3_clks 360 17>; 102920fcf9d6SAswath Govindraju power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 103020fcf9d6SAswath Govindraju #address-cells = <2>; 103120fcf9d6SAswath Govindraju #size-cells = <2>; 103220fcf9d6SAswath Govindraju ranges; 103320fcf9d6SAswath Govindraju dma-coherent; 103420fcf9d6SAswath Govindraju 103520fcf9d6SAswath Govindraju status = "disabled"; /* Needs pinmux */ 103620fcf9d6SAswath Govindraju 103720fcf9d6SAswath Govindraju usb0: usb@6000000 { 103820fcf9d6SAswath Govindraju compatible = "cdns,usb3"; 103920fcf9d6SAswath Govindraju reg = <0x00 0x06000000 0x00 0x10000>, 104020fcf9d6SAswath Govindraju <0x00 0x06010000 0x00 0x10000>, 104120fcf9d6SAswath Govindraju <0x00 0x06020000 0x00 0x10000>; 104220fcf9d6SAswath Govindraju reg-names = "otg", "xhci", "dev"; 104320fcf9d6SAswath Govindraju interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 104420fcf9d6SAswath Govindraju <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 104520fcf9d6SAswath Govindraju <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 104620fcf9d6SAswath Govindraju interrupt-names = "host", "peripheral", "otg"; 104720fcf9d6SAswath Govindraju maximum-speed = "super-speed"; 104820fcf9d6SAswath Govindraju dr_mode = "otg"; 104920fcf9d6SAswath Govindraju }; 105020fcf9d6SAswath Govindraju }; 105120fcf9d6SAswath Govindraju 1052393eee04SMatt Ranostay serdes_wiz0: wiz@5060000 { 1053393eee04SMatt Ranostay compatible = "ti,j721s2-wiz-10g"; 1054393eee04SMatt Ranostay #address-cells = <1>; 1055393eee04SMatt Ranostay #size-cells = <1>; 1056393eee04SMatt Ranostay power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1057393eee04SMatt Ranostay clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1058393eee04SMatt Ranostay clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1059393eee04SMatt Ranostay num-lanes = <4>; 1060393eee04SMatt Ranostay #reset-cells = <1>; 1061393eee04SMatt Ranostay #clock-cells = <1>; 1062393eee04SMatt Ranostay ranges = <0x5060000 0x0 0x5060000 0x10000>; 1063393eee04SMatt Ranostay 1064393eee04SMatt Ranostay assigned-clocks = <&k3_clks 365 3>; 1065393eee04SMatt Ranostay assigned-clock-parents = <&k3_clks 365 7>; 1066393eee04SMatt Ranostay 1067393eee04SMatt Ranostay serdes0: serdes@5060000 { 1068393eee04SMatt Ranostay compatible = "ti,j721e-serdes-10g"; 1069393eee04SMatt Ranostay reg = <0x05060000 0x00010000>; 1070393eee04SMatt Ranostay reg-names = "torrent_phy"; 1071393eee04SMatt Ranostay resets = <&serdes_wiz0 0>; 1072393eee04SMatt Ranostay reset-names = "torrent_reset"; 1073393eee04SMatt Ranostay clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1074393eee04SMatt Ranostay <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1075393eee04SMatt Ranostay clock-names = "refclk", "phy_en_refclk"; 1076393eee04SMatt Ranostay assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1077393eee04SMatt Ranostay <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1078393eee04SMatt Ranostay <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1079393eee04SMatt Ranostay assigned-clock-parents = <&k3_clks 365 3>, 1080393eee04SMatt Ranostay <&k3_clks 365 3>, 1081393eee04SMatt Ranostay <&k3_clks 365 3>; 1082393eee04SMatt Ranostay #address-cells = <1>; 1083393eee04SMatt Ranostay #size-cells = <0>; 1084393eee04SMatt Ranostay #clock-cells = <1>; 1085393eee04SMatt Ranostay 1086393eee04SMatt Ranostay status = "disabled"; /* Needs lane config */ 1087393eee04SMatt Ranostay }; 1088393eee04SMatt Ranostay }; 1089393eee04SMatt Ranostay 1090b6f18aa8SAswath Govindraju pcie1_rc: pcie@2910000 { 1091b6f18aa8SAswath Govindraju compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1092b6f18aa8SAswath Govindraju reg = <0x00 0x02910000 0x00 0x1000>, 1093b6f18aa8SAswath Govindraju <0x00 0x02917000 0x00 0x400>, 1094b6f18aa8SAswath Govindraju <0x00 0x0d800000 0x00 0x800000>, 1095b6f18aa8SAswath Govindraju <0x00 0x18000000 0x00 0x1000>; 1096b6f18aa8SAswath Govindraju reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1097b6f18aa8SAswath Govindraju interrupt-names = "link_state"; 1098b6f18aa8SAswath Govindraju interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1099b6f18aa8SAswath Govindraju device_type = "pci"; 1100b6f18aa8SAswath Govindraju ti,syscon-pcie-ctrl = <&scm_conf 0x074>; 1101b6f18aa8SAswath Govindraju max-link-speed = <3>; 1102b6f18aa8SAswath Govindraju num-lanes = <4>; 1103b6f18aa8SAswath Govindraju power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1104b6f18aa8SAswath Govindraju clocks = <&k3_clks 276 41>; 1105b6f18aa8SAswath Govindraju clock-names = "fck"; 1106b6f18aa8SAswath Govindraju #address-cells = <3>; 1107b6f18aa8SAswath Govindraju #size-cells = <2>; 1108b6f18aa8SAswath Govindraju bus-range = <0x0 0xff>; 1109b6f18aa8SAswath Govindraju vendor-id = <0x104c>; 1110b6f18aa8SAswath Govindraju device-id = <0xb013>; 1111b6f18aa8SAswath Govindraju msi-map = <0x0 &gic_its 0x0 0x10000>; 1112b6f18aa8SAswath Govindraju dma-coherent; 1113b6f18aa8SAswath Govindraju ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1114b6f18aa8SAswath Govindraju <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1115b6f18aa8SAswath Govindraju dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1116b6f18aa8SAswath Govindraju #interrupt-cells = <1>; 1117b6f18aa8SAswath Govindraju interrupt-map-mask = <0 0 0 7>; 1118b6f18aa8SAswath Govindraju interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1119b6f18aa8SAswath Govindraju <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1120b6f18aa8SAswath Govindraju <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1121b6f18aa8SAswath Govindraju <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1122b6f18aa8SAswath Govindraju 1123b6f18aa8SAswath Govindraju status = "disabled"; /* Needs gpio and serdes info */ 1124b6f18aa8SAswath Govindraju 1125b6f18aa8SAswath Govindraju pcie1_intc: interrupt-controller { 1126b6f18aa8SAswath Govindraju interrupt-controller; 1127b6f18aa8SAswath Govindraju #interrupt-cells = <1>; 1128b6f18aa8SAswath Govindraju interrupt-parent = <&gic500>; 1129b6f18aa8SAswath Govindraju interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1130b6f18aa8SAswath Govindraju }; 1131b6f18aa8SAswath Govindraju }; 1132b6f18aa8SAswath Govindraju 1133b8545f9dSAswath Govindraju main_mcan0: can@2701000 { 1134b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1135b8545f9dSAswath Govindraju reg = <0x00 0x02701000 0x00 0x200>, 1136b8545f9dSAswath Govindraju <0x00 0x02708000 0x00 0x8000>; 1137b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1138b8545f9dSAswath Govindraju power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1139b8545f9dSAswath Govindraju clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1140b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1141b8545f9dSAswath Govindraju interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1142b8545f9dSAswath Govindraju <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1143b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1144b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 114506639b8aSAndrew Davis status = "disabled"; 1146b8545f9dSAswath Govindraju }; 1147b8545f9dSAswath Govindraju 1148b8545f9dSAswath Govindraju main_mcan1: can@2711000 { 1149b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1150b8545f9dSAswath Govindraju reg = <0x00 0x02711000 0x00 0x200>, 1151b8545f9dSAswath Govindraju <0x00 0x02718000 0x00 0x8000>; 1152b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1153b8545f9dSAswath Govindraju power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1154b8545f9dSAswath Govindraju clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1155b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1156b8545f9dSAswath Govindraju interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1157b8545f9dSAswath Govindraju <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1158b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1159b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 116006639b8aSAndrew Davis status = "disabled"; 1161b8545f9dSAswath Govindraju }; 1162b8545f9dSAswath Govindraju 1163b8545f9dSAswath Govindraju main_mcan2: can@2721000 { 1164b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1165b8545f9dSAswath Govindraju reg = <0x00 0x02721000 0x00 0x200>, 1166b8545f9dSAswath Govindraju <0x00 0x02728000 0x00 0x8000>; 1167b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1168b8545f9dSAswath Govindraju power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1169b8545f9dSAswath Govindraju clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1170b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1171b8545f9dSAswath Govindraju interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1172b8545f9dSAswath Govindraju <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1173b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1174b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 117506639b8aSAndrew Davis status = "disabled"; 1176b8545f9dSAswath Govindraju }; 1177b8545f9dSAswath Govindraju 1178b8545f9dSAswath Govindraju main_mcan3: can@2731000 { 1179b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1180b8545f9dSAswath Govindraju reg = <0x00 0x02731000 0x00 0x200>, 1181b8545f9dSAswath Govindraju <0x00 0x02738000 0x00 0x8000>; 1182b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1183b8545f9dSAswath Govindraju power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1184b8545f9dSAswath Govindraju clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1185b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1186b8545f9dSAswath Govindraju interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1187b8545f9dSAswath Govindraju <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1188b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1189b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 119006639b8aSAndrew Davis status = "disabled"; 1191b8545f9dSAswath Govindraju }; 1192b8545f9dSAswath Govindraju 1193b8545f9dSAswath Govindraju main_mcan4: can@2741000 { 1194b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1195b8545f9dSAswath Govindraju reg = <0x00 0x02741000 0x00 0x200>, 1196b8545f9dSAswath Govindraju <0x00 0x02748000 0x00 0x8000>; 1197b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1198b8545f9dSAswath Govindraju power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1199b8545f9dSAswath Govindraju clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1200b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1201b8545f9dSAswath Govindraju interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1202b8545f9dSAswath Govindraju <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1203b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1204b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 120506639b8aSAndrew Davis status = "disabled"; 1206b8545f9dSAswath Govindraju }; 1207b8545f9dSAswath Govindraju 1208b8545f9dSAswath Govindraju main_mcan5: can@2751000 { 1209b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1210b8545f9dSAswath Govindraju reg = <0x00 0x02751000 0x00 0x200>, 1211b8545f9dSAswath Govindraju <0x00 0x02758000 0x00 0x8000>; 1212b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1213b8545f9dSAswath Govindraju power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1214b8545f9dSAswath Govindraju clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1215b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1216b8545f9dSAswath Govindraju interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1217b8545f9dSAswath Govindraju <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1218b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1219b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 122006639b8aSAndrew Davis status = "disabled"; 1221b8545f9dSAswath Govindraju }; 1222b8545f9dSAswath Govindraju 1223b8545f9dSAswath Govindraju main_mcan6: can@2761000 { 1224b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1225b8545f9dSAswath Govindraju reg = <0x00 0x02761000 0x00 0x200>, 1226b8545f9dSAswath Govindraju <0x00 0x02768000 0x00 0x8000>; 1227b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1228b8545f9dSAswath Govindraju power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1229b8545f9dSAswath Govindraju clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1230b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1231b8545f9dSAswath Govindraju interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1232b8545f9dSAswath Govindraju <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1233b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1234b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 123506639b8aSAndrew Davis status = "disabled"; 1236b8545f9dSAswath Govindraju }; 1237b8545f9dSAswath Govindraju 1238b8545f9dSAswath Govindraju main_mcan7: can@2771000 { 1239b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1240b8545f9dSAswath Govindraju reg = <0x00 0x02771000 0x00 0x200>, 1241b8545f9dSAswath Govindraju <0x00 0x02778000 0x00 0x8000>; 1242b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1243b8545f9dSAswath Govindraju power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1244b8545f9dSAswath Govindraju clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1245b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1246b8545f9dSAswath Govindraju interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1247b8545f9dSAswath Govindraju <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1248b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1249b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 125006639b8aSAndrew Davis status = "disabled"; 1251b8545f9dSAswath Govindraju }; 1252b8545f9dSAswath Govindraju 1253b8545f9dSAswath Govindraju main_mcan8: can@2781000 { 1254b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1255b8545f9dSAswath Govindraju reg = <0x00 0x02781000 0x00 0x200>, 1256b8545f9dSAswath Govindraju <0x00 0x02788000 0x00 0x8000>; 1257b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1258b8545f9dSAswath Govindraju power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1259b8545f9dSAswath Govindraju clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1260b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1261b8545f9dSAswath Govindraju interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1262b8545f9dSAswath Govindraju <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1263b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1264b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 126506639b8aSAndrew Davis status = "disabled"; 1266b8545f9dSAswath Govindraju }; 1267b8545f9dSAswath Govindraju 1268b8545f9dSAswath Govindraju main_mcan9: can@2791000 { 1269b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1270b8545f9dSAswath Govindraju reg = <0x00 0x02791000 0x00 0x200>, 1271b8545f9dSAswath Govindraju <0x00 0x02798000 0x00 0x8000>; 1272b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1273b8545f9dSAswath Govindraju power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1274b8545f9dSAswath Govindraju clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1275b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1276b8545f9dSAswath Govindraju interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1277b8545f9dSAswath Govindraju <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1278b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1279b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 128006639b8aSAndrew Davis status = "disabled"; 1281b8545f9dSAswath Govindraju }; 1282b8545f9dSAswath Govindraju 1283b8545f9dSAswath Govindraju main_mcan10: can@27a1000 { 1284b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1285b8545f9dSAswath Govindraju reg = <0x00 0x027a1000 0x00 0x200>, 1286b8545f9dSAswath Govindraju <0x00 0x027a8000 0x00 0x8000>; 1287b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1288b8545f9dSAswath Govindraju power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1289b8545f9dSAswath Govindraju clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1290b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1291b8545f9dSAswath Govindraju interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1292b8545f9dSAswath Govindraju <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1293b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1294b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 129506639b8aSAndrew Davis status = "disabled"; 1296b8545f9dSAswath Govindraju }; 1297b8545f9dSAswath Govindraju 1298b8545f9dSAswath Govindraju main_mcan11: can@27b1000 { 1299b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1300b8545f9dSAswath Govindraju reg = <0x00 0x027b1000 0x00 0x200>, 1301b8545f9dSAswath Govindraju <0x00 0x027b8000 0x00 0x8000>; 1302b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1303b8545f9dSAswath Govindraju power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1304b8545f9dSAswath Govindraju clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1305b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1306b8545f9dSAswath Govindraju interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1307b8545f9dSAswath Govindraju <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1308b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1309b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 131006639b8aSAndrew Davis status = "disabled"; 1311b8545f9dSAswath Govindraju }; 1312b8545f9dSAswath Govindraju 1313b8545f9dSAswath Govindraju main_mcan12: can@27c1000 { 1314b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1315b8545f9dSAswath Govindraju reg = <0x00 0x027c1000 0x00 0x200>, 1316b8545f9dSAswath Govindraju <0x00 0x027c8000 0x00 0x8000>; 1317b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1318b8545f9dSAswath Govindraju power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1319b8545f9dSAswath Govindraju clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1320b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1321b8545f9dSAswath Govindraju interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1322b8545f9dSAswath Govindraju <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1323b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1324b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 132506639b8aSAndrew Davis status = "disabled"; 1326b8545f9dSAswath Govindraju }; 1327b8545f9dSAswath Govindraju 1328b8545f9dSAswath Govindraju main_mcan13: can@27d1000 { 1329b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1330b8545f9dSAswath Govindraju reg = <0x00 0x027d1000 0x00 0x200>, 1331b8545f9dSAswath Govindraju <0x00 0x027d8000 0x00 0x8000>; 1332b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1333b8545f9dSAswath Govindraju power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1334b8545f9dSAswath Govindraju clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1335b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1336b8545f9dSAswath Govindraju interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1337b8545f9dSAswath Govindraju <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1338b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1339b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 134006639b8aSAndrew Davis status = "disabled"; 1341b8545f9dSAswath Govindraju }; 1342b8545f9dSAswath Govindraju 1343b8545f9dSAswath Govindraju main_mcan14: can@2681000 { 1344b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1345b8545f9dSAswath Govindraju reg = <0x00 0x02681000 0x00 0x200>, 1346b8545f9dSAswath Govindraju <0x00 0x02688000 0x00 0x8000>; 1347b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1348b8545f9dSAswath Govindraju power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1349b8545f9dSAswath Govindraju clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1350b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1351b8545f9dSAswath Govindraju interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1352b8545f9dSAswath Govindraju <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1353b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1354b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 135506639b8aSAndrew Davis status = "disabled"; 1356b8545f9dSAswath Govindraju }; 1357b8545f9dSAswath Govindraju 1358b8545f9dSAswath Govindraju main_mcan15: can@2691000 { 1359b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1360b8545f9dSAswath Govindraju reg = <0x00 0x02691000 0x00 0x200>, 1361b8545f9dSAswath Govindraju <0x00 0x02698000 0x00 0x8000>; 1362b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1363b8545f9dSAswath Govindraju power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1364b8545f9dSAswath Govindraju clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1365b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1366b8545f9dSAswath Govindraju interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1367b8545f9dSAswath Govindraju <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1368b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1369b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 137006639b8aSAndrew Davis status = "disabled"; 1371b8545f9dSAswath Govindraju }; 1372b8545f9dSAswath Govindraju 1373b8545f9dSAswath Govindraju main_mcan16: can@26a1000 { 1374b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1375b8545f9dSAswath Govindraju reg = <0x00 0x026a1000 0x00 0x200>, 1376b8545f9dSAswath Govindraju <0x00 0x026a8000 0x00 0x8000>; 1377b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1378b8545f9dSAswath Govindraju power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1379b8545f9dSAswath Govindraju clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1380b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1381b8545f9dSAswath Govindraju interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1382b8545f9dSAswath Govindraju <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1383b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1384b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 138506639b8aSAndrew Davis status = "disabled"; 1386b8545f9dSAswath Govindraju }; 1387b8545f9dSAswath Govindraju 1388b8545f9dSAswath Govindraju main_mcan17: can@26b1000 { 1389b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1390b8545f9dSAswath Govindraju reg = <0x00 0x026b1000 0x00 0x200>, 1391b8545f9dSAswath Govindraju <0x00 0x026b8000 0x00 0x8000>; 1392b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1393b8545f9dSAswath Govindraju power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1394b8545f9dSAswath Govindraju clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1395b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1396b8545f9dSAswath Govindraju interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1397b8545f9dSAswath Govindraju <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1398b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1399b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 140006639b8aSAndrew Davis status = "disabled"; 1401b8545f9dSAswath Govindraju }; 140204d7cb64SVaishnav Achath 140304d7cb64SVaishnav Achath main_spi0: spi@2100000 { 140404d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 140504d7cb64SVaishnav Achath reg = <0x00 0x02100000 0x00 0x400>; 140604d7cb64SVaishnav Achath interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 140704d7cb64SVaishnav Achath #address-cells = <1>; 140804d7cb64SVaishnav Achath #size-cells = <0>; 140904d7cb64SVaishnav Achath power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 141004d7cb64SVaishnav Achath clocks = <&k3_clks 339 1>; 141104d7cb64SVaishnav Achath status = "disabled"; 141204d7cb64SVaishnav Achath }; 141304d7cb64SVaishnav Achath 141404d7cb64SVaishnav Achath main_spi1: spi@2110000 { 141504d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 141604d7cb64SVaishnav Achath reg = <0x00 0x02110000 0x00 0x400>; 141704d7cb64SVaishnav Achath interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 141804d7cb64SVaishnav Achath #address-cells = <1>; 141904d7cb64SVaishnav Achath #size-cells = <0>; 142004d7cb64SVaishnav Achath power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 142104d7cb64SVaishnav Achath clocks = <&k3_clks 340 1>; 142204d7cb64SVaishnav Achath status = "disabled"; 142304d7cb64SVaishnav Achath }; 142404d7cb64SVaishnav Achath 142504d7cb64SVaishnav Achath main_spi2: spi@2120000 { 142604d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 142704d7cb64SVaishnav Achath reg = <0x00 0x02120000 0x00 0x400>; 142804d7cb64SVaishnav Achath interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 142904d7cb64SVaishnav Achath #address-cells = <1>; 143004d7cb64SVaishnav Achath #size-cells = <0>; 143104d7cb64SVaishnav Achath power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 143204d7cb64SVaishnav Achath clocks = <&k3_clks 341 1>; 143304d7cb64SVaishnav Achath status = "disabled"; 143404d7cb64SVaishnav Achath }; 143504d7cb64SVaishnav Achath 143604d7cb64SVaishnav Achath main_spi3: spi@2130000 { 143704d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 143804d7cb64SVaishnav Achath reg = <0x00 0x02130000 0x00 0x400>; 143904d7cb64SVaishnav Achath interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 144004d7cb64SVaishnav Achath #address-cells = <1>; 144104d7cb64SVaishnav Achath #size-cells = <0>; 144204d7cb64SVaishnav Achath power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 144304d7cb64SVaishnav Achath clocks = <&k3_clks 342 1>; 144404d7cb64SVaishnav Achath status = "disabled"; 144504d7cb64SVaishnav Achath }; 144604d7cb64SVaishnav Achath 144704d7cb64SVaishnav Achath main_spi4: spi@2140000 { 144804d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 144904d7cb64SVaishnav Achath reg = <0x00 0x02140000 0x00 0x400>; 145004d7cb64SVaishnav Achath interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 145104d7cb64SVaishnav Achath #address-cells = <1>; 145204d7cb64SVaishnav Achath #size-cells = <0>; 145304d7cb64SVaishnav Achath power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 145404d7cb64SVaishnav Achath clocks = <&k3_clks 343 1>; 145504d7cb64SVaishnav Achath status = "disabled"; 145604d7cb64SVaishnav Achath }; 145704d7cb64SVaishnav Achath 145804d7cb64SVaishnav Achath main_spi5: spi@2150000 { 145904d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 146004d7cb64SVaishnav Achath reg = <0x00 0x02150000 0x00 0x400>; 146104d7cb64SVaishnav Achath interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 146204d7cb64SVaishnav Achath #address-cells = <1>; 146304d7cb64SVaishnav Achath #size-cells = <0>; 146404d7cb64SVaishnav Achath power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 146504d7cb64SVaishnav Achath clocks = <&k3_clks 344 1>; 146604d7cb64SVaishnav Achath status = "disabled"; 146704d7cb64SVaishnav Achath }; 146804d7cb64SVaishnav Achath 146904d7cb64SVaishnav Achath main_spi6: spi@2160000 { 147004d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 147104d7cb64SVaishnav Achath reg = <0x00 0x02160000 0x00 0x400>; 147204d7cb64SVaishnav Achath interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 147304d7cb64SVaishnav Achath #address-cells = <1>; 147404d7cb64SVaishnav Achath #size-cells = <0>; 147504d7cb64SVaishnav Achath power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 147604d7cb64SVaishnav Achath clocks = <&k3_clks 345 1>; 147704d7cb64SVaishnav Achath status = "disabled"; 147804d7cb64SVaishnav Achath }; 147904d7cb64SVaishnav Achath 148004d7cb64SVaishnav Achath main_spi7: spi@2170000 { 148104d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 148204d7cb64SVaishnav Achath reg = <0x00 0x02170000 0x00 0x400>; 148304d7cb64SVaishnav Achath interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 148404d7cb64SVaishnav Achath #address-cells = <1>; 148504d7cb64SVaishnav Achath #size-cells = <0>; 148604d7cb64SVaishnav Achath power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 148704d7cb64SVaishnav Achath clocks = <&k3_clks 346 1>; 148804d7cb64SVaishnav Achath status = "disabled"; 148904d7cb64SVaishnav Achath }; 1490b8545f9dSAswath Govindraju}; 1491