1b8545f9dSAswath Govindraju// SPDX-License-Identifier: GPL-2.0 2b8545f9dSAswath Govindraju/* 3b8545f9dSAswath Govindraju * Device Tree Source for J721S2 SoC Family Main Domain peripherals 4b8545f9dSAswath Govindraju * 5b8545f9dSAswath Govindraju * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 6b8545f9dSAswath Govindraju */ 7b8545f9dSAswath Govindraju 8393eee04SMatt Ranostay#include <dt-bindings/phy/phy-cadence.h> 9393eee04SMatt Ranostay#include <dt-bindings/phy/phy-ti.h> 10393eee04SMatt Ranostay 11393eee04SMatt Ranostay/ { 12393eee04SMatt Ranostay serdes_refclk: clock-cmnrefclk { 13393eee04SMatt Ranostay #clock-cells = <0>; 14393eee04SMatt Ranostay compatible = "fixed-clock"; 15393eee04SMatt Ranostay clock-frequency = <0>; 16393eee04SMatt Ranostay }; 17393eee04SMatt Ranostay}; 18393eee04SMatt Ranostay 19b8545f9dSAswath Govindraju&cbass_main { 20b8545f9dSAswath Govindraju msmc_ram: sram@70000000 { 21b8545f9dSAswath Govindraju compatible = "mmio-sram"; 22b8545f9dSAswath Govindraju reg = <0x0 0x70000000 0x0 0x400000>; 23b8545f9dSAswath Govindraju #address-cells = <1>; 24b8545f9dSAswath Govindraju #size-cells = <1>; 25b8545f9dSAswath Govindraju ranges = <0x0 0x0 0x70000000 0x400000>; 26b8545f9dSAswath Govindraju 27b8545f9dSAswath Govindraju atf-sram@0 { 28b8545f9dSAswath Govindraju reg = <0x0 0x20000>; 29b8545f9dSAswath Govindraju }; 30b8545f9dSAswath Govindraju 31b8545f9dSAswath Govindraju tifs-sram@1f0000 { 32b8545f9dSAswath Govindraju reg = <0x1f0000 0x10000>; 33b8545f9dSAswath Govindraju }; 34b8545f9dSAswath Govindraju 35b8545f9dSAswath Govindraju l3cache-sram@200000 { 36b8545f9dSAswath Govindraju reg = <0x200000 0x200000>; 37b8545f9dSAswath Govindraju }; 38b8545f9dSAswath Govindraju }; 39b8545f9dSAswath Govindraju 4020fcf9d6SAswath Govindraju scm_conf: syscon@104000 { 4120fcf9d6SAswath Govindraju compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 4220fcf9d6SAswath Govindraju reg = <0x00 0x00104000 0x00 0x18000>; 4320fcf9d6SAswath Govindraju #address-cells = <1>; 4420fcf9d6SAswath Govindraju #size-cells = <1>; 4520fcf9d6SAswath Govindraju ranges = <0x00 0x00 0x00104000 0x18000>; 4620fcf9d6SAswath Govindraju 4720fcf9d6SAswath Govindraju usb_serdes_mux: mux-controller@0 { 4820fcf9d6SAswath Govindraju compatible = "mmio-mux"; 4920fcf9d6SAswath Govindraju reg = <0x0 0x4>; 5020fcf9d6SAswath Govindraju #mux-control-cells = <1>; 5120fcf9d6SAswath Govindraju mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 5220fcf9d6SAswath Govindraju }; 53393eee04SMatt Ranostay 54393eee04SMatt Ranostay serdes_ln_ctrl: mux-controller@80 { 55393eee04SMatt Ranostay compatible = "mmio-mux"; 56393eee04SMatt Ranostay reg = <0x80 0x10>; 57393eee04SMatt Ranostay #mux-control-cells = <1>; 58393eee04SMatt Ranostay mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ 59393eee04SMatt Ranostay <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ 60393eee04SMatt Ranostay }; 6120fcf9d6SAswath Govindraju }; 6220fcf9d6SAswath Govindraju 63b8545f9dSAswath Govindraju gic500: interrupt-controller@1800000 { 64b8545f9dSAswath Govindraju compatible = "arm,gic-v3"; 65b8545f9dSAswath Govindraju #address-cells = <2>; 66b8545f9dSAswath Govindraju #size-cells = <2>; 67b8545f9dSAswath Govindraju ranges; 68b8545f9dSAswath Govindraju #interrupt-cells = <3>; 69b8545f9dSAswath Govindraju interrupt-controller; 70856216b7SMatt Ranostay reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */ 71a9668037SNishanth Menon <0x00 0x01900000 0x00 0x100000>, /* GICR */ 72a9668037SNishanth Menon <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 73a9668037SNishanth Menon <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 74a9668037SNishanth Menon <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 75b8545f9dSAswath Govindraju 76b8545f9dSAswath Govindraju /* vcpumntirq: virtual CPU interface maintenance interrupt */ 77b8545f9dSAswath Govindraju interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 78b8545f9dSAswath Govindraju 79b8545f9dSAswath Govindraju gic_its: msi-controller@1820000 { 80b8545f9dSAswath Govindraju compatible = "arm,gic-v3-its"; 81b8545f9dSAswath Govindraju reg = <0x00 0x01820000 0x00 0x10000>; 82b8545f9dSAswath Govindraju socionext,synquacer-pre-its = <0x1000000 0x400000>; 83b8545f9dSAswath Govindraju msi-controller; 84b8545f9dSAswath Govindraju #msi-cells = <1>; 85b8545f9dSAswath Govindraju }; 86b8545f9dSAswath Govindraju }; 87b8545f9dSAswath Govindraju 88b8545f9dSAswath Govindraju main_gpio_intr: interrupt-controller@a00000 { 89b8545f9dSAswath Govindraju compatible = "ti,sci-intr"; 90b8545f9dSAswath Govindraju reg = <0x00 0x00a00000 0x00 0x800>; 91b8545f9dSAswath Govindraju ti,intr-trigger-type = <1>; 92b8545f9dSAswath Govindraju interrupt-controller; 93b8545f9dSAswath Govindraju interrupt-parent = <&gic500>; 94b8545f9dSAswath Govindraju #interrupt-cells = <1>; 95b8545f9dSAswath Govindraju ti,sci = <&sms>; 96b8545f9dSAswath Govindraju ti,sci-dev-id = <148>; 97b8aa36c2SKeerthy ti,interrupt-ranges = <8 392 56>; 98b8545f9dSAswath Govindraju }; 99b8545f9dSAswath Govindraju 100b8545f9dSAswath Govindraju main_pmx0: pinctrl@11c000 { 101b8545f9dSAswath Govindraju compatible = "pinctrl-single"; 102b8545f9dSAswath Govindraju /* Proxy 0 addressing */ 103b8545f9dSAswath Govindraju reg = <0x0 0x11c000 0x0 0x120>; 104b8545f9dSAswath Govindraju #pinctrl-cells = <1>; 105b8545f9dSAswath Govindraju pinctrl-single,register-width = <32>; 106b8545f9dSAswath Govindraju pinctrl-single,function-mask = <0xffffffff>; 107b8545f9dSAswath Govindraju }; 108b8545f9dSAswath Govindraju 1091ecc75beSNishanth Menon /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 1101ecc75beSNishanth Menon main_timerio_input: pinctrl@104200 { 1111ecc75beSNishanth Menon compatible = "pinctrl-single"; 1121ecc75beSNishanth Menon reg = <0x00 0x104200 0x00 0x50>; 1131ecc75beSNishanth Menon #pinctrl-cells = <1>; 1141ecc75beSNishanth Menon pinctrl-single,register-width = <32>; 1151ecc75beSNishanth Menon pinctrl-single,function-mask = <0x00000007>; 1161ecc75beSNishanth Menon }; 1171ecc75beSNishanth Menon 1181ecc75beSNishanth Menon /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 1191ecc75beSNishanth Menon main_timerio_output: pinctrl@104280 { 1201ecc75beSNishanth Menon compatible = "pinctrl-single"; 1211ecc75beSNishanth Menon reg = <0x00 0x104280 0x00 0x20>; 1221ecc75beSNishanth Menon #pinctrl-cells = <1>; 1231ecc75beSNishanth Menon pinctrl-single,register-width = <32>; 1241ecc75beSNishanth Menon pinctrl-single,function-mask = <0x0000001f>; 1251ecc75beSNishanth Menon }; 1261ecc75beSNishanth Menon 127027b85caSJayesh Choudhary main_crypto: crypto@4e00000 { 128027b85caSJayesh Choudhary compatible = "ti,j721e-sa2ul"; 129027b85caSJayesh Choudhary reg = <0x00 0x04e00000 0x00 0x1200>; 130027b85caSJayesh Choudhary power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 131027b85caSJayesh Choudhary #address-cells = <2>; 132027b85caSJayesh Choudhary #size-cells = <2>; 133027b85caSJayesh Choudhary ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 134027b85caSJayesh Choudhary 135027b85caSJayesh Choudhary dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 136027b85caSJayesh Choudhary <&main_udmap 0x4a41>; 137027b85caSJayesh Choudhary dma-names = "tx", "rx1", "rx2"; 138027b85caSJayesh Choudhary 139027b85caSJayesh Choudhary rng: rng@4e10000 { 140027b85caSJayesh Choudhary compatible = "inside-secure,safexcel-eip76"; 141027b85caSJayesh Choudhary reg = <0x00 0x04e10000 0x00 0x7d>; 142027b85caSJayesh Choudhary interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 143027b85caSJayesh Choudhary }; 144027b85caSJayesh Choudhary }; 145027b85caSJayesh Choudhary 146835d0442SNishanth Menon main_timer0: timer@2400000 { 147835d0442SNishanth Menon compatible = "ti,am654-timer"; 148835d0442SNishanth Menon reg = <0x00 0x2400000 0x00 0x400>; 149835d0442SNishanth Menon interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 150835d0442SNishanth Menon clocks = <&k3_clks 63 1>; 151835d0442SNishanth Menon clock-names = "fck"; 152835d0442SNishanth Menon assigned-clocks = <&k3_clks 63 1>; 153835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 63 2>; 154835d0442SNishanth Menon power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 155835d0442SNishanth Menon ti,timer-pwm; 156835d0442SNishanth Menon }; 157835d0442SNishanth Menon 158835d0442SNishanth Menon main_timer1: timer@2410000 { 159835d0442SNishanth Menon compatible = "ti,am654-timer"; 160835d0442SNishanth Menon reg = <0x00 0x2410000 0x00 0x400>; 161835d0442SNishanth Menon interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 162835d0442SNishanth Menon clocks = <&k3_clks 64 1>; 163835d0442SNishanth Menon clock-names = "fck"; 164835d0442SNishanth Menon assigned-clocks = <&k3_clks 64 1>; 165835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 64 2>; 166835d0442SNishanth Menon power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 167835d0442SNishanth Menon ti,timer-pwm; 168835d0442SNishanth Menon }; 169835d0442SNishanth Menon 170835d0442SNishanth Menon main_timer2: timer@2420000 { 171835d0442SNishanth Menon compatible = "ti,am654-timer"; 172835d0442SNishanth Menon reg = <0x00 0x2420000 0x00 0x400>; 173835d0442SNishanth Menon interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 174835d0442SNishanth Menon clocks = <&k3_clks 65 1>; 175835d0442SNishanth Menon clock-names = "fck"; 176835d0442SNishanth Menon assigned-clocks = <&k3_clks 65 1>; 177835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 65 2>; 178835d0442SNishanth Menon power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 179835d0442SNishanth Menon ti,timer-pwm; 180835d0442SNishanth Menon }; 181835d0442SNishanth Menon 182835d0442SNishanth Menon main_timer3: timer@2430000 { 183835d0442SNishanth Menon compatible = "ti,am654-timer"; 184835d0442SNishanth Menon reg = <0x00 0x2430000 0x00 0x400>; 185835d0442SNishanth Menon interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 186835d0442SNishanth Menon clocks = <&k3_clks 66 1>; 187835d0442SNishanth Menon clock-names = "fck"; 188835d0442SNishanth Menon assigned-clocks = <&k3_clks 66 1>; 189835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 66 2>; 190835d0442SNishanth Menon power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 191835d0442SNishanth Menon ti,timer-pwm; 192835d0442SNishanth Menon }; 193835d0442SNishanth Menon 194835d0442SNishanth Menon main_timer4: timer@2440000 { 195835d0442SNishanth Menon compatible = "ti,am654-timer"; 196835d0442SNishanth Menon reg = <0x00 0x2440000 0x00 0x400>; 197835d0442SNishanth Menon interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 198835d0442SNishanth Menon clocks = <&k3_clks 67 1>; 199835d0442SNishanth Menon clock-names = "fck"; 200835d0442SNishanth Menon assigned-clocks = <&k3_clks 67 1>; 201835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 67 2>; 202835d0442SNishanth Menon power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 203835d0442SNishanth Menon ti,timer-pwm; 204835d0442SNishanth Menon }; 205835d0442SNishanth Menon 206835d0442SNishanth Menon main_timer5: timer@2450000 { 207835d0442SNishanth Menon compatible = "ti,am654-timer"; 208835d0442SNishanth Menon reg = <0x00 0x2450000 0x00 0x400>; 209835d0442SNishanth Menon interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 210835d0442SNishanth Menon clocks = <&k3_clks 68 1>; 211835d0442SNishanth Menon clock-names = "fck"; 212835d0442SNishanth Menon assigned-clocks = <&k3_clks 68 1>; 213835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 68 2>; 214835d0442SNishanth Menon power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 215835d0442SNishanth Menon ti,timer-pwm; 216835d0442SNishanth Menon }; 217835d0442SNishanth Menon 218835d0442SNishanth Menon main_timer6: timer@2460000 { 219835d0442SNishanth Menon compatible = "ti,am654-timer"; 220835d0442SNishanth Menon reg = <0x00 0x2460000 0x00 0x400>; 221835d0442SNishanth Menon interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 222835d0442SNishanth Menon clocks = <&k3_clks 69 1>; 223835d0442SNishanth Menon clock-names = "fck"; 224835d0442SNishanth Menon assigned-clocks = <&k3_clks 69 1>; 225835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 69 2>; 226835d0442SNishanth Menon power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 227835d0442SNishanth Menon ti,timer-pwm; 228835d0442SNishanth Menon }; 229835d0442SNishanth Menon 230835d0442SNishanth Menon main_timer7: timer@2470000 { 231835d0442SNishanth Menon compatible = "ti,am654-timer"; 232835d0442SNishanth Menon reg = <0x00 0x2470000 0x00 0x400>; 233835d0442SNishanth Menon interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 234835d0442SNishanth Menon clocks = <&k3_clks 70 1>; 235835d0442SNishanth Menon clock-names = "fck"; 236835d0442SNishanth Menon assigned-clocks = <&k3_clks 70 1>; 237835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 70 2>; 238835d0442SNishanth Menon power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 239835d0442SNishanth Menon ti,timer-pwm; 240835d0442SNishanth Menon }; 241835d0442SNishanth Menon 242835d0442SNishanth Menon main_timer8: timer@2480000 { 243835d0442SNishanth Menon compatible = "ti,am654-timer"; 244835d0442SNishanth Menon reg = <0x00 0x2480000 0x00 0x400>; 245835d0442SNishanth Menon interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 246835d0442SNishanth Menon clocks = <&k3_clks 71 1>; 247835d0442SNishanth Menon clock-names = "fck"; 248835d0442SNishanth Menon assigned-clocks = <&k3_clks 71 1>; 249835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 71 2>; 250835d0442SNishanth Menon power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 251835d0442SNishanth Menon ti,timer-pwm; 252835d0442SNishanth Menon }; 253835d0442SNishanth Menon 254835d0442SNishanth Menon main_timer9: timer@2490000 { 255835d0442SNishanth Menon compatible = "ti,am654-timer"; 256835d0442SNishanth Menon reg = <0x00 0x2490000 0x00 0x400>; 257835d0442SNishanth Menon interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 258835d0442SNishanth Menon clocks = <&k3_clks 72 1>; 259835d0442SNishanth Menon clock-names = "fck"; 260835d0442SNishanth Menon assigned-clocks = <&k3_clks 72 1>; 261835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 72 2>; 262835d0442SNishanth Menon power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 263835d0442SNishanth Menon ti,timer-pwm; 264835d0442SNishanth Menon }; 265835d0442SNishanth Menon 266835d0442SNishanth Menon main_timer10: timer@24a0000 { 267835d0442SNishanth Menon compatible = "ti,am654-timer"; 268835d0442SNishanth Menon reg = <0x00 0x24a0000 0x00 0x400>; 269835d0442SNishanth Menon interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 270835d0442SNishanth Menon clocks = <&k3_clks 73 1>; 271835d0442SNishanth Menon clock-names = "fck"; 272835d0442SNishanth Menon assigned-clocks = <&k3_clks 73 1>; 273835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 73 2>; 274835d0442SNishanth Menon power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 275835d0442SNishanth Menon ti,timer-pwm; 276835d0442SNishanth Menon }; 277835d0442SNishanth Menon 278835d0442SNishanth Menon main_timer11: timer@24b0000 { 279835d0442SNishanth Menon compatible = "ti,am654-timer"; 280835d0442SNishanth Menon reg = <0x00 0x24b0000 0x00 0x400>; 281835d0442SNishanth Menon interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 282835d0442SNishanth Menon clocks = <&k3_clks 74 1>; 283835d0442SNishanth Menon clock-names = "fck"; 284835d0442SNishanth Menon assigned-clocks = <&k3_clks 74 1>; 285835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 74 2>; 286835d0442SNishanth Menon power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 287835d0442SNishanth Menon ti,timer-pwm; 288835d0442SNishanth Menon }; 289835d0442SNishanth Menon 290835d0442SNishanth Menon main_timer12: timer@24c0000 { 291835d0442SNishanth Menon compatible = "ti,am654-timer"; 292835d0442SNishanth Menon reg = <0x00 0x24c0000 0x00 0x400>; 293835d0442SNishanth Menon interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 294835d0442SNishanth Menon clocks = <&k3_clks 75 1>; 295835d0442SNishanth Menon clock-names = "fck"; 296835d0442SNishanth Menon assigned-clocks = <&k3_clks 75 1>; 297835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 75 2>; 298835d0442SNishanth Menon power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 299835d0442SNishanth Menon ti,timer-pwm; 300835d0442SNishanth Menon }; 301835d0442SNishanth Menon 302835d0442SNishanth Menon main_timer13: timer@24d0000 { 303835d0442SNishanth Menon compatible = "ti,am654-timer"; 304835d0442SNishanth Menon reg = <0x00 0x24d0000 0x00 0x400>; 305835d0442SNishanth Menon interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 306835d0442SNishanth Menon clocks = <&k3_clks 76 1>; 307835d0442SNishanth Menon clock-names = "fck"; 308835d0442SNishanth Menon assigned-clocks = <&k3_clks 76 1>; 309835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 76 2>; 310835d0442SNishanth Menon power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; 311835d0442SNishanth Menon ti,timer-pwm; 312835d0442SNishanth Menon }; 313835d0442SNishanth Menon 314835d0442SNishanth Menon main_timer14: timer@24e0000 { 315835d0442SNishanth Menon compatible = "ti,am654-timer"; 316835d0442SNishanth Menon reg = <0x00 0x24e0000 0x00 0x400>; 317835d0442SNishanth Menon interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 318835d0442SNishanth Menon clocks = <&k3_clks 77 1>; 319835d0442SNishanth Menon clock-names = "fck"; 320835d0442SNishanth Menon assigned-clocks = <&k3_clks 77 1>; 321835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 77 2>; 322835d0442SNishanth Menon power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 323835d0442SNishanth Menon ti,timer-pwm; 324835d0442SNishanth Menon }; 325835d0442SNishanth Menon 326835d0442SNishanth Menon main_timer15: timer@24f0000 { 327835d0442SNishanth Menon compatible = "ti,am654-timer"; 328835d0442SNishanth Menon reg = <0x00 0x24f0000 0x00 0x400>; 329835d0442SNishanth Menon interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 330835d0442SNishanth Menon clocks = <&k3_clks 78 1>; 331835d0442SNishanth Menon clock-names = "fck"; 332835d0442SNishanth Menon assigned-clocks = <&k3_clks 78 1>; 333835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 78 2>; 334835d0442SNishanth Menon power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 335835d0442SNishanth Menon ti,timer-pwm; 336835d0442SNishanth Menon }; 337835d0442SNishanth Menon 338835d0442SNishanth Menon main_timer16: timer@2500000 { 339835d0442SNishanth Menon compatible = "ti,am654-timer"; 340835d0442SNishanth Menon reg = <0x00 0x2500000 0x00 0x400>; 341835d0442SNishanth Menon interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 342835d0442SNishanth Menon clocks = <&k3_clks 79 1>; 343835d0442SNishanth Menon clock-names = "fck"; 344835d0442SNishanth Menon assigned-clocks = <&k3_clks 79 1>; 345835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 79 2>; 346835d0442SNishanth Menon power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 347835d0442SNishanth Menon ti,timer-pwm; 348835d0442SNishanth Menon }; 349835d0442SNishanth Menon 350835d0442SNishanth Menon main_timer17: timer@2510000 { 351835d0442SNishanth Menon compatible = "ti,am654-timer"; 352835d0442SNishanth Menon reg = <0x00 0x2510000 0x00 0x400>; 353835d0442SNishanth Menon interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 354835d0442SNishanth Menon clocks = <&k3_clks 80 1>; 355835d0442SNishanth Menon clock-names = "fck"; 356835d0442SNishanth Menon assigned-clocks = <&k3_clks 80 1>; 357835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 80 2>; 358835d0442SNishanth Menon power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 359835d0442SNishanth Menon ti,timer-pwm; 360835d0442SNishanth Menon }; 361835d0442SNishanth Menon 362835d0442SNishanth Menon main_timer18: timer@2520000 { 363835d0442SNishanth Menon compatible = "ti,am654-timer"; 364835d0442SNishanth Menon reg = <0x00 0x2520000 0x00 0x400>; 365835d0442SNishanth Menon interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 366835d0442SNishanth Menon clocks = <&k3_clks 81 1>; 367835d0442SNishanth Menon clock-names = "fck"; 368835d0442SNishanth Menon assigned-clocks = <&k3_clks 81 1>; 369835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 81 2>; 370835d0442SNishanth Menon power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 371835d0442SNishanth Menon ti,timer-pwm; 372835d0442SNishanth Menon }; 373835d0442SNishanth Menon 374835d0442SNishanth Menon main_timer19: timer@2530000 { 375835d0442SNishanth Menon compatible = "ti,am654-timer"; 376835d0442SNishanth Menon reg = <0x00 0x2530000 0x00 0x400>; 377835d0442SNishanth Menon interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 378835d0442SNishanth Menon clocks = <&k3_clks 82 1>; 379835d0442SNishanth Menon clock-names = "fck"; 380835d0442SNishanth Menon assigned-clocks = <&k3_clks 82 1>; 381835d0442SNishanth Menon assigned-clock-parents = <&k3_clks 82 2>; 382835d0442SNishanth Menon power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 383835d0442SNishanth Menon ti,timer-pwm; 384835d0442SNishanth Menon }; 385835d0442SNishanth Menon 386b8545f9dSAswath Govindraju main_uart0: serial@2800000 { 387b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 388b8545f9dSAswath Govindraju reg = <0x00 0x02800000 0x00 0x200>; 389b8545f9dSAswath Govindraju interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 390b8545f9dSAswath Govindraju current-speed = <115200>; 391b8545f9dSAswath Govindraju clocks = <&k3_clks 146 3>; 392b8545f9dSAswath Govindraju clock-names = "fclk"; 393b8545f9dSAswath Govindraju power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 3940e63f35aSAndrew Davis status = "disabled"; 395b8545f9dSAswath Govindraju }; 396b8545f9dSAswath Govindraju 397b8545f9dSAswath Govindraju main_uart1: serial@2810000 { 398b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 399b8545f9dSAswath Govindraju reg = <0x00 0x02810000 0x00 0x200>; 400b8545f9dSAswath Govindraju interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 401b8545f9dSAswath Govindraju current-speed = <115200>; 402b8545f9dSAswath Govindraju clocks = <&k3_clks 350 3>; 403b8545f9dSAswath Govindraju clock-names = "fclk"; 404b8545f9dSAswath Govindraju power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 4050e63f35aSAndrew Davis status = "disabled"; 406b8545f9dSAswath Govindraju }; 407b8545f9dSAswath Govindraju 408b8545f9dSAswath Govindraju main_uart2: serial@2820000 { 409b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 410b8545f9dSAswath Govindraju reg = <0x00 0x02820000 0x00 0x200>; 411b8545f9dSAswath Govindraju interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 412b8545f9dSAswath Govindraju current-speed = <115200>; 413b8545f9dSAswath Govindraju clocks = <&k3_clks 351 3>; 414b8545f9dSAswath Govindraju clock-names = "fclk"; 415b8545f9dSAswath Govindraju power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 4160e63f35aSAndrew Davis status = "disabled"; 417b8545f9dSAswath Govindraju }; 418b8545f9dSAswath Govindraju 419b8545f9dSAswath Govindraju main_uart3: serial@2830000 { 420b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 421b8545f9dSAswath Govindraju reg = <0x00 0x02830000 0x00 0x200>; 422b8545f9dSAswath Govindraju interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 423b8545f9dSAswath Govindraju current-speed = <115200>; 424b8545f9dSAswath Govindraju clocks = <&k3_clks 352 3>; 425b8545f9dSAswath Govindraju clock-names = "fclk"; 426b8545f9dSAswath Govindraju power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 4270e63f35aSAndrew Davis status = "disabled"; 428b8545f9dSAswath Govindraju }; 429b8545f9dSAswath Govindraju 430b8545f9dSAswath Govindraju main_uart4: serial@2840000 { 431b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 432b8545f9dSAswath Govindraju reg = <0x00 0x02840000 0x00 0x200>; 433b8545f9dSAswath Govindraju interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 434b8545f9dSAswath Govindraju current-speed = <115200>; 435b8545f9dSAswath Govindraju clocks = <&k3_clks 353 3>; 436b8545f9dSAswath Govindraju clock-names = "fclk"; 437b8545f9dSAswath Govindraju power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 4380e63f35aSAndrew Davis status = "disabled"; 439b8545f9dSAswath Govindraju }; 440b8545f9dSAswath Govindraju 441b8545f9dSAswath Govindraju main_uart5: serial@2850000 { 442b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 443b8545f9dSAswath Govindraju reg = <0x00 0x02850000 0x00 0x200>; 444b8545f9dSAswath Govindraju interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 445b8545f9dSAswath Govindraju current-speed = <115200>; 446b8545f9dSAswath Govindraju clocks = <&k3_clks 354 3>; 447b8545f9dSAswath Govindraju clock-names = "fclk"; 448b8545f9dSAswath Govindraju power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 4490e63f35aSAndrew Davis status = "disabled"; 450b8545f9dSAswath Govindraju }; 451b8545f9dSAswath Govindraju 452b8545f9dSAswath Govindraju main_uart6: serial@2860000 { 453b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 454b8545f9dSAswath Govindraju reg = <0x00 0x02860000 0x00 0x200>; 455b8545f9dSAswath Govindraju interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 456b8545f9dSAswath Govindraju current-speed = <115200>; 457b8545f9dSAswath Govindraju clocks = <&k3_clks 355 3>; 458b8545f9dSAswath Govindraju clock-names = "fclk"; 459b8545f9dSAswath Govindraju power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 4600e63f35aSAndrew Davis status = "disabled"; 461b8545f9dSAswath Govindraju }; 462b8545f9dSAswath Govindraju 463b8545f9dSAswath Govindraju main_uart7: serial@2870000 { 464b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 465b8545f9dSAswath Govindraju reg = <0x00 0x02870000 0x00 0x200>; 466b8545f9dSAswath Govindraju interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 467b8545f9dSAswath Govindraju current-speed = <115200>; 468b8545f9dSAswath Govindraju clocks = <&k3_clks 356 3>; 469b8545f9dSAswath Govindraju clock-names = "fclk"; 470b8545f9dSAswath Govindraju power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 4710e63f35aSAndrew Davis status = "disabled"; 472b8545f9dSAswath Govindraju }; 473b8545f9dSAswath Govindraju 474b8545f9dSAswath Govindraju main_uart8: serial@2880000 { 475b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 476b8545f9dSAswath Govindraju reg = <0x00 0x02880000 0x00 0x200>; 477b8545f9dSAswath Govindraju interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 478b8545f9dSAswath Govindraju current-speed = <115200>; 479b8545f9dSAswath Govindraju clocks = <&k3_clks 357 3>; 480b8545f9dSAswath Govindraju clock-names = "fclk"; 481b8545f9dSAswath Govindraju power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 4820e63f35aSAndrew Davis status = "disabled"; 483b8545f9dSAswath Govindraju }; 484b8545f9dSAswath Govindraju 485b8545f9dSAswath Govindraju main_uart9: serial@2890000 { 486b8545f9dSAswath Govindraju compatible = "ti,j721e-uart", "ti,am654-uart"; 487b8545f9dSAswath Govindraju reg = <0x00 0x02890000 0x00 0x200>; 488b8545f9dSAswath Govindraju interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 489b8545f9dSAswath Govindraju current-speed = <115200>; 490b8545f9dSAswath Govindraju clocks = <&k3_clks 358 3>; 491b8545f9dSAswath Govindraju clock-names = "fclk"; 492b8545f9dSAswath Govindraju power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 4930e63f35aSAndrew Davis status = "disabled"; 494b8545f9dSAswath Govindraju }; 495b8545f9dSAswath Govindraju 496b8545f9dSAswath Govindraju main_gpio0: gpio@600000 { 497b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 498b8545f9dSAswath Govindraju reg = <0x00 0x00600000 0x00 0x100>; 499b8545f9dSAswath Govindraju gpio-controller; 500b8545f9dSAswath Govindraju #gpio-cells = <2>; 501b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 502b8545f9dSAswath Govindraju interrupts = <145>, <146>, <147>, <148>, <149>; 503b8545f9dSAswath Govindraju interrupt-controller; 504b8545f9dSAswath Govindraju #interrupt-cells = <2>; 505b8545f9dSAswath Govindraju ti,ngpio = <66>; 506b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 507b8545f9dSAswath Govindraju power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 508b8545f9dSAswath Govindraju clocks = <&k3_clks 111 0>; 509b8545f9dSAswath Govindraju clock-names = "gpio"; 510b8545f9dSAswath Govindraju }; 511b8545f9dSAswath Govindraju 512b8545f9dSAswath Govindraju main_gpio2: gpio@610000 { 513b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 514b8545f9dSAswath Govindraju reg = <0x00 0x00610000 0x00 0x100>; 515b8545f9dSAswath Govindraju gpio-controller; 516b8545f9dSAswath Govindraju #gpio-cells = <2>; 517b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 518b8545f9dSAswath Govindraju interrupts = <154>, <155>, <156>, <157>, <158>; 519b8545f9dSAswath Govindraju interrupt-controller; 520b8545f9dSAswath Govindraju #interrupt-cells = <2>; 521b8545f9dSAswath Govindraju ti,ngpio = <66>; 522b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 523b8545f9dSAswath Govindraju power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 524b8545f9dSAswath Govindraju clocks = <&k3_clks 112 0>; 525b8545f9dSAswath Govindraju clock-names = "gpio"; 526b8545f9dSAswath Govindraju }; 527b8545f9dSAswath Govindraju 528b8545f9dSAswath Govindraju main_gpio4: gpio@620000 { 529b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 530b8545f9dSAswath Govindraju reg = <0x00 0x00620000 0x00 0x100>; 531b8545f9dSAswath Govindraju gpio-controller; 532b8545f9dSAswath Govindraju #gpio-cells = <2>; 533b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 534b8545f9dSAswath Govindraju interrupts = <163>, <164>, <165>, <166>, <167>; 535b8545f9dSAswath Govindraju interrupt-controller; 536b8545f9dSAswath Govindraju #interrupt-cells = <2>; 537b8545f9dSAswath Govindraju ti,ngpio = <66>; 538b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 539b8545f9dSAswath Govindraju power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 540b8545f9dSAswath Govindraju clocks = <&k3_clks 113 0>; 541b8545f9dSAswath Govindraju clock-names = "gpio"; 542b8545f9dSAswath Govindraju }; 543b8545f9dSAswath Govindraju 544b8545f9dSAswath Govindraju main_gpio6: gpio@630000 { 545b8545f9dSAswath Govindraju compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 546b8545f9dSAswath Govindraju reg = <0x00 0x00630000 0x00 0x100>; 547b8545f9dSAswath Govindraju gpio-controller; 548b8545f9dSAswath Govindraju #gpio-cells = <2>; 549b8545f9dSAswath Govindraju interrupt-parent = <&main_gpio_intr>; 550b8545f9dSAswath Govindraju interrupts = <172>, <173>, <174>, <175>, <176>; 551b8545f9dSAswath Govindraju interrupt-controller; 552b8545f9dSAswath Govindraju #interrupt-cells = <2>; 553b8545f9dSAswath Govindraju ti,ngpio = <66>; 554b8545f9dSAswath Govindraju ti,davinci-gpio-unbanked = <0>; 555b8545f9dSAswath Govindraju power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 556b8545f9dSAswath Govindraju clocks = <&k3_clks 114 0>; 557b8545f9dSAswath Govindraju clock-names = "gpio"; 558b8545f9dSAswath Govindraju }; 559b8545f9dSAswath Govindraju 560b8545f9dSAswath Govindraju main_i2c0: i2c@2000000 { 561b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 562b8545f9dSAswath Govindraju reg = <0x00 0x02000000 0x00 0x100>; 563b8545f9dSAswath Govindraju interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 564b8545f9dSAswath Govindraju #address-cells = <1>; 565b8545f9dSAswath Govindraju #size-cells = <0>; 566b8545f9dSAswath Govindraju clocks = <&k3_clks 214 1>; 567b8545f9dSAswath Govindraju clock-names = "fck"; 568b8545f9dSAswath Govindraju power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 569b8545f9dSAswath Govindraju }; 570b8545f9dSAswath Govindraju 571b8545f9dSAswath Govindraju main_i2c1: i2c@2010000 { 572b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 573b8545f9dSAswath Govindraju reg = <0x00 0x02010000 0x00 0x100>; 574b8545f9dSAswath Govindraju interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 575b8545f9dSAswath Govindraju #address-cells = <1>; 576b8545f9dSAswath Govindraju #size-cells = <0>; 577b8545f9dSAswath Govindraju clocks = <&k3_clks 215 1>; 578b8545f9dSAswath Govindraju clock-names = "fck"; 579b8545f9dSAswath Govindraju power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; 5800aef5131SAndrew Davis status = "disabled"; 581b8545f9dSAswath Govindraju }; 582b8545f9dSAswath Govindraju 583b8545f9dSAswath Govindraju main_i2c2: i2c@2020000 { 584b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 585b8545f9dSAswath Govindraju reg = <0x00 0x02020000 0x00 0x100>; 586b8545f9dSAswath Govindraju interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 587b8545f9dSAswath Govindraju #address-cells = <1>; 588b8545f9dSAswath Govindraju #size-cells = <0>; 589b8545f9dSAswath Govindraju clocks = <&k3_clks 216 1>; 590b8545f9dSAswath Govindraju clock-names = "fck"; 591b8545f9dSAswath Govindraju power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; 5920aef5131SAndrew Davis status = "disabled"; 593b8545f9dSAswath Govindraju }; 594b8545f9dSAswath Govindraju 595b8545f9dSAswath Govindraju main_i2c3: i2c@2030000 { 596b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 597b8545f9dSAswath Govindraju reg = <0x00 0x02030000 0x00 0x100>; 598b8545f9dSAswath Govindraju interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 599b8545f9dSAswath Govindraju #address-cells = <1>; 600b8545f9dSAswath Govindraju #size-cells = <0>; 601b8545f9dSAswath Govindraju clocks = <&k3_clks 217 1>; 602b8545f9dSAswath Govindraju clock-names = "fck"; 603b8545f9dSAswath Govindraju power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 6040aef5131SAndrew Davis status = "disabled"; 605b8545f9dSAswath Govindraju }; 606b8545f9dSAswath Govindraju 607b8545f9dSAswath Govindraju main_i2c4: i2c@2040000 { 608b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 609b8545f9dSAswath Govindraju reg = <0x00 0x02040000 0x00 0x100>; 610b8545f9dSAswath Govindraju interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 611b8545f9dSAswath Govindraju #address-cells = <1>; 612b8545f9dSAswath Govindraju #size-cells = <0>; 613b8545f9dSAswath Govindraju clocks = <&k3_clks 218 1>; 614b8545f9dSAswath Govindraju clock-names = "fck"; 615b8545f9dSAswath Govindraju power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 6160aef5131SAndrew Davis status = "disabled"; 617b8545f9dSAswath Govindraju }; 618b8545f9dSAswath Govindraju 619b8545f9dSAswath Govindraju main_i2c5: i2c@2050000 { 620b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 621b8545f9dSAswath Govindraju reg = <0x00 0x02050000 0x00 0x100>; 622b8545f9dSAswath Govindraju interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 623b8545f9dSAswath Govindraju #address-cells = <1>; 624b8545f9dSAswath Govindraju #size-cells = <0>; 625b8545f9dSAswath Govindraju clocks = <&k3_clks 219 1>; 626b8545f9dSAswath Govindraju clock-names = "fck"; 627b8545f9dSAswath Govindraju power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 6280aef5131SAndrew Davis status = "disabled"; 629b8545f9dSAswath Govindraju }; 630b8545f9dSAswath Govindraju 631b8545f9dSAswath Govindraju main_i2c6: i2c@2060000 { 632b8545f9dSAswath Govindraju compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 633b8545f9dSAswath Govindraju reg = <0x00 0x02060000 0x00 0x100>; 634b8545f9dSAswath Govindraju interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 635b8545f9dSAswath Govindraju #address-cells = <1>; 636b8545f9dSAswath Govindraju #size-cells = <0>; 637b8545f9dSAswath Govindraju clocks = <&k3_clks 220 1>; 638b8545f9dSAswath Govindraju clock-names = "fck"; 639b8545f9dSAswath Govindraju power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 6400aef5131SAndrew Davis status = "disabled"; 641b8545f9dSAswath Govindraju }; 642b8545f9dSAswath Govindraju 643b8545f9dSAswath Govindraju main_sdhci0: mmc@4f80000 { 644b8545f9dSAswath Govindraju compatible = "ti,j721e-sdhci-8bit"; 645b8545f9dSAswath Govindraju reg = <0x00 0x04f80000 0x00 0x1000>, 646b8545f9dSAswath Govindraju <0x00 0x04f88000 0x00 0x400>; 647b8545f9dSAswath Govindraju interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 648b8545f9dSAswath Govindraju power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 649b8545f9dSAswath Govindraju clocks = <&k3_clks 98 7>, <&k3_clks 98 1>; 650b8545f9dSAswath Govindraju clock-names = "clk_ahb", "clk_xin"; 651b8545f9dSAswath Govindraju assigned-clocks = <&k3_clks 98 1>; 652b8545f9dSAswath Govindraju assigned-clock-parents = <&k3_clks 98 2>; 653b8545f9dSAswath Govindraju bus-width = <8>; 654b8545f9dSAswath Govindraju ti,otap-del-sel-legacy = <0x0>; 655b8545f9dSAswath Govindraju ti,otap-del-sel-mmc-hs = <0x0>; 656b8545f9dSAswath Govindraju ti,otap-del-sel-ddr52 = <0x6>; 657b8545f9dSAswath Govindraju ti,otap-del-sel-hs200 = <0x8>; 658b8545f9dSAswath Govindraju ti,otap-del-sel-hs400 = <0x5>; 659b8545f9dSAswath Govindraju ti,itap-del-sel-legacy = <0x10>; 660b8545f9dSAswath Govindraju ti,itap-del-sel-mmc-hs = <0xa>; 661b8545f9dSAswath Govindraju ti,strobe-sel = <0x77>; 662b8545f9dSAswath Govindraju ti,clkbuf-sel = <0x7>; 663b8545f9dSAswath Govindraju ti,trm-icp = <0x8>; 664b8545f9dSAswath Govindraju mmc-ddr-1_8v; 665b8545f9dSAswath Govindraju mmc-hs200-1_8v; 666b8545f9dSAswath Govindraju mmc-hs400-1_8v; 667b8545f9dSAswath Govindraju dma-coherent; 668b8545f9dSAswath Govindraju }; 669b8545f9dSAswath Govindraju 670b8545f9dSAswath Govindraju main_sdhci1: mmc@4fb0000 { 671b8545f9dSAswath Govindraju compatible = "ti,j721e-sdhci-4bit"; 672b8545f9dSAswath Govindraju reg = <0x00 0x04fb0000 0x00 0x1000>, 673b8545f9dSAswath Govindraju <0x00 0x04fb8000 0x00 0x400>; 674b8545f9dSAswath Govindraju interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 675b8545f9dSAswath Govindraju power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 676b8545f9dSAswath Govindraju clocks = <&k3_clks 99 8>, <&k3_clks 99 1>; 677b8545f9dSAswath Govindraju clock-names = "clk_ahb", "clk_xin"; 678b8545f9dSAswath Govindraju assigned-clocks = <&k3_clks 99 1>; 679b8545f9dSAswath Govindraju assigned-clock-parents = <&k3_clks 99 2>; 680b8545f9dSAswath Govindraju bus-width = <4>; 681b8545f9dSAswath Govindraju ti,otap-del-sel-legacy = <0x0>; 682b8545f9dSAswath Govindraju ti,otap-del-sel-sd-hs = <0x0>; 683b8545f9dSAswath Govindraju ti,otap-del-sel-sdr12 = <0xf>; 684b8545f9dSAswath Govindraju ti,otap-del-sel-sdr25 = <0xf>; 685b8545f9dSAswath Govindraju ti,otap-del-sel-sdr50 = <0xc>; 686b8545f9dSAswath Govindraju ti,otap-del-sel-sdr104 = <0x5>; 687b8545f9dSAswath Govindraju ti,otap-del-sel-ddr50 = <0xc>; 688b8545f9dSAswath Govindraju ti,itap-del-sel-legacy = <0x0>; 689b8545f9dSAswath Govindraju ti,itap-del-sel-sd-hs = <0x0>; 690b8545f9dSAswath Govindraju ti,itap-del-sel-sdr12 = <0x0>; 691b8545f9dSAswath Govindraju ti,itap-del-sel-sdr25 = <0x0>; 692b8545f9dSAswath Govindraju ti,clkbuf-sel = <0x7>; 693b8545f9dSAswath Govindraju ti,trm-icp = <0x8>; 694b8545f9dSAswath Govindraju dma-coherent; 695b8545f9dSAswath Govindraju /* Masking support for SDR104 capability */ 696b8545f9dSAswath Govindraju sdhci-caps-mask = <0x00000003 0x00000000>; 697b8545f9dSAswath Govindraju }; 698b8545f9dSAswath Govindraju 699b8545f9dSAswath Govindraju main_navss: bus@30000000 { 700b8545f9dSAswath Govindraju compatible = "simple-mfd"; 701b8545f9dSAswath Govindraju #address-cells = <2>; 702b8545f9dSAswath Govindraju #size-cells = <2>; 703b8545f9dSAswath Govindraju ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 704b8545f9dSAswath Govindraju ti,sci-dev-id = <224>; 705b8545f9dSAswath Govindraju dma-coherent; 706b8545f9dSAswath Govindraju dma-ranges; 707b8545f9dSAswath Govindraju 708b8545f9dSAswath Govindraju main_navss_intr: interrupt-controller@310e0000 { 709b8545f9dSAswath Govindraju compatible = "ti,sci-intr"; 710b8545f9dSAswath Govindraju reg = <0x00 0x310e0000 0x00 0x4000>; 711b8545f9dSAswath Govindraju ti,intr-trigger-type = <4>; 712b8545f9dSAswath Govindraju interrupt-controller; 713b8545f9dSAswath Govindraju interrupt-parent = <&gic500>; 714b8545f9dSAswath Govindraju #interrupt-cells = <1>; 715b8545f9dSAswath Govindraju ti,sci = <&sms>; 716b8545f9dSAswath Govindraju ti,sci-dev-id = <227>; 717b8545f9dSAswath Govindraju ti,interrupt-ranges = <0 64 64>, 718b8545f9dSAswath Govindraju <64 448 64>, 719b8545f9dSAswath Govindraju <128 672 64>; 720b8545f9dSAswath Govindraju }; 721b8545f9dSAswath Govindraju 722b8545f9dSAswath Govindraju main_udmass_inta: msi-controller@33d00000 { 723b8545f9dSAswath Govindraju compatible = "ti,sci-inta"; 724b8545f9dSAswath Govindraju reg = <0x00 0x33d00000 0x00 0x100000>; 725b8545f9dSAswath Govindraju interrupt-controller; 726b8545f9dSAswath Govindraju #interrupt-cells = <0>; 727b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 728b8545f9dSAswath Govindraju msi-controller; 729b8545f9dSAswath Govindraju ti,sci = <&sms>; 730b8545f9dSAswath Govindraju ti,sci-dev-id = <265>; 731b8545f9dSAswath Govindraju ti,interrupt-ranges = <0 0 256>; 732b8545f9dSAswath Govindraju }; 733b8545f9dSAswath Govindraju 734b8545f9dSAswath Govindraju secure_proxy_main: mailbox@32c00000 { 735b8545f9dSAswath Govindraju compatible = "ti,am654-secure-proxy"; 736b8545f9dSAswath Govindraju #mbox-cells = <1>; 737b8545f9dSAswath Govindraju reg-names = "target_data", "rt", "scfg"; 738b8545f9dSAswath Govindraju reg = <0x00 0x32c00000 0x00 0x100000>, 739b8545f9dSAswath Govindraju <0x00 0x32400000 0x00 0x100000>, 740b8545f9dSAswath Govindraju <0x00 0x32800000 0x00 0x100000>; 741b8545f9dSAswath Govindraju interrupt-names = "rx_011"; 742b8545f9dSAswath Govindraju interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 743b8545f9dSAswath Govindraju }; 744b8545f9dSAswath Govindraju 745b8545f9dSAswath Govindraju hwspinlock: spinlock@30e00000 { 746b8545f9dSAswath Govindraju compatible = "ti,am654-hwspinlock"; 747b8545f9dSAswath Govindraju reg = <0x00 0x30e00000 0x00 0x1000>; 748b8545f9dSAswath Govindraju #hwlock-cells = <1>; 749b8545f9dSAswath Govindraju }; 750b8545f9dSAswath Govindraju 751b8545f9dSAswath Govindraju mailbox0_cluster0: mailbox@31f80000 { 752b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 753b8545f9dSAswath Govindraju reg = <0x00 0x31f80000 0x00 0x200>; 754b8545f9dSAswath Govindraju #mbox-cells = <1>; 755b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 756b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 757b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7583fb0402fSAndrew Davis status = "disabled"; 759b8545f9dSAswath Govindraju }; 760b8545f9dSAswath Govindraju 761b8545f9dSAswath Govindraju mailbox0_cluster1: mailbox@31f81000 { 762b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 763b8545f9dSAswath Govindraju reg = <0x00 0x31f81000 0x00 0x200>; 764b8545f9dSAswath Govindraju #mbox-cells = <1>; 765b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 766b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 767b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7683fb0402fSAndrew Davis status = "disabled"; 769b8545f9dSAswath Govindraju }; 770b8545f9dSAswath Govindraju 771b8545f9dSAswath Govindraju mailbox0_cluster2: mailbox@31f82000 { 772b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 773b8545f9dSAswath Govindraju reg = <0x00 0x31f82000 0x00 0x200>; 774b8545f9dSAswath Govindraju #mbox-cells = <1>; 775b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 776b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 777b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7783fb0402fSAndrew Davis status = "disabled"; 779b8545f9dSAswath Govindraju }; 780b8545f9dSAswath Govindraju 781b8545f9dSAswath Govindraju mailbox0_cluster3: mailbox@31f83000 { 782b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 783b8545f9dSAswath Govindraju reg = <0x00 0x31f83000 0x00 0x200>; 784b8545f9dSAswath Govindraju #mbox-cells = <1>; 785b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 786b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 787b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7883fb0402fSAndrew Davis status = "disabled"; 789b8545f9dSAswath Govindraju }; 790b8545f9dSAswath Govindraju 791b8545f9dSAswath Govindraju mailbox0_cluster4: mailbox@31f84000 { 792b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 793b8545f9dSAswath Govindraju reg = <0x00 0x31f84000 0x00 0x200>; 794b8545f9dSAswath Govindraju #mbox-cells = <1>; 795b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 796b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 797b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 7983fb0402fSAndrew Davis status = "disabled"; 799b8545f9dSAswath Govindraju }; 800b8545f9dSAswath Govindraju 801b8545f9dSAswath Govindraju mailbox0_cluster5: mailbox@31f85000 { 802b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 803b8545f9dSAswath Govindraju reg = <0x00 0x31f85000 0x00 0x200>; 804b8545f9dSAswath Govindraju #mbox-cells = <1>; 805b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 806b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 807b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8083fb0402fSAndrew Davis status = "disabled"; 809b8545f9dSAswath Govindraju }; 810b8545f9dSAswath Govindraju 811b8545f9dSAswath Govindraju mailbox0_cluster6: mailbox@31f86000 { 812b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 813b8545f9dSAswath Govindraju reg = <0x00 0x31f86000 0x00 0x200>; 814b8545f9dSAswath Govindraju #mbox-cells = <1>; 815b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 816b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 817b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8183fb0402fSAndrew Davis status = "disabled"; 819b8545f9dSAswath Govindraju }; 820b8545f9dSAswath Govindraju 821b8545f9dSAswath Govindraju mailbox0_cluster7: mailbox@31f87000 { 822b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 823b8545f9dSAswath Govindraju reg = <0x00 0x31f87000 0x00 0x200>; 824b8545f9dSAswath Govindraju #mbox-cells = <1>; 825b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 826b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 827b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8283fb0402fSAndrew Davis status = "disabled"; 829b8545f9dSAswath Govindraju }; 830b8545f9dSAswath Govindraju 831b8545f9dSAswath Govindraju mailbox0_cluster8: mailbox@31f88000 { 832b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 833b8545f9dSAswath Govindraju reg = <0x00 0x31f88000 0x00 0x200>; 834b8545f9dSAswath Govindraju #mbox-cells = <1>; 835b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 836b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 837b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8383fb0402fSAndrew Davis status = "disabled"; 839b8545f9dSAswath Govindraju }; 840b8545f9dSAswath Govindraju 841b8545f9dSAswath Govindraju mailbox0_cluster9: mailbox@31f89000 { 842b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 843b8545f9dSAswath Govindraju reg = <0x00 0x31f89000 0x00 0x200>; 844b8545f9dSAswath Govindraju #mbox-cells = <1>; 845b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 846b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 847b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8483fb0402fSAndrew Davis status = "disabled"; 849b8545f9dSAswath Govindraju }; 850b8545f9dSAswath Govindraju 851b8545f9dSAswath Govindraju mailbox0_cluster10: mailbox@31f8a000 { 852b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 853b8545f9dSAswath Govindraju reg = <0x00 0x31f8a000 0x00 0x200>; 854b8545f9dSAswath Govindraju #mbox-cells = <1>; 855b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 856b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 857b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8583fb0402fSAndrew Davis status = "disabled"; 859b8545f9dSAswath Govindraju }; 860b8545f9dSAswath Govindraju 861b8545f9dSAswath Govindraju mailbox0_cluster11: mailbox@31f8b000 { 862b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 863b8545f9dSAswath Govindraju reg = <0x00 0x31f8b000 0x00 0x200>; 864b8545f9dSAswath Govindraju #mbox-cells = <1>; 865b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 866b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 867b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8683fb0402fSAndrew Davis status = "disabled"; 869b8545f9dSAswath Govindraju }; 870b8545f9dSAswath Govindraju 871b8545f9dSAswath Govindraju mailbox1_cluster0: mailbox@31f90000 { 872b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 873b8545f9dSAswath Govindraju reg = <0x00 0x31f90000 0x00 0x200>; 874b8545f9dSAswath Govindraju #mbox-cells = <1>; 875b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 876b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 877b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8783fb0402fSAndrew Davis status = "disabled"; 879b8545f9dSAswath Govindraju }; 880b8545f9dSAswath Govindraju 881b8545f9dSAswath Govindraju mailbox1_cluster1: mailbox@31f91000 { 882b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 883b8545f9dSAswath Govindraju reg = <0x00 0x31f91000 0x00 0x200>; 884b8545f9dSAswath Govindraju #mbox-cells = <1>; 885b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 886b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 887b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8883fb0402fSAndrew Davis status = "disabled"; 889b8545f9dSAswath Govindraju }; 890b8545f9dSAswath Govindraju 891b8545f9dSAswath Govindraju mailbox1_cluster2: mailbox@31f92000 { 892b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 893b8545f9dSAswath Govindraju reg = <0x00 0x31f92000 0x00 0x200>; 894b8545f9dSAswath Govindraju #mbox-cells = <1>; 895b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 896b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 897b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 8983fb0402fSAndrew Davis status = "disabled"; 899b8545f9dSAswath Govindraju }; 900b8545f9dSAswath Govindraju 901b8545f9dSAswath Govindraju mailbox1_cluster3: mailbox@31f93000 { 902b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 903b8545f9dSAswath Govindraju reg = <0x00 0x31f93000 0x00 0x200>; 904b8545f9dSAswath Govindraju #mbox-cells = <1>; 905b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 906b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 907b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9083fb0402fSAndrew Davis status = "disabled"; 909b8545f9dSAswath Govindraju }; 910b8545f9dSAswath Govindraju 911b8545f9dSAswath Govindraju mailbox1_cluster4: mailbox@31f94000 { 912b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 913b8545f9dSAswath Govindraju reg = <0x00 0x31f94000 0x00 0x200>; 914b8545f9dSAswath Govindraju #mbox-cells = <1>; 915b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 916b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 917b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9183fb0402fSAndrew Davis status = "disabled"; 919b8545f9dSAswath Govindraju }; 920b8545f9dSAswath Govindraju 921b8545f9dSAswath Govindraju mailbox1_cluster5: mailbox@31f95000 { 922b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 923b8545f9dSAswath Govindraju reg = <0x00 0x31f95000 0x00 0x200>; 924b8545f9dSAswath Govindraju #mbox-cells = <1>; 925b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 926b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 927b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9283fb0402fSAndrew Davis status = "disabled"; 929b8545f9dSAswath Govindraju }; 930b8545f9dSAswath Govindraju 931b8545f9dSAswath Govindraju mailbox1_cluster6: mailbox@31f96000 { 932b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 933b8545f9dSAswath Govindraju reg = <0x00 0x31f96000 0x00 0x200>; 934b8545f9dSAswath Govindraju #mbox-cells = <1>; 935b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 936b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 937b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9383fb0402fSAndrew Davis status = "disabled"; 939b8545f9dSAswath Govindraju }; 940b8545f9dSAswath Govindraju 941b8545f9dSAswath Govindraju mailbox1_cluster7: mailbox@31f97000 { 942b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 943b8545f9dSAswath Govindraju reg = <0x00 0x31f97000 0x00 0x200>; 944b8545f9dSAswath Govindraju #mbox-cells = <1>; 945b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 946b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 947b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9483fb0402fSAndrew Davis status = "disabled"; 949b8545f9dSAswath Govindraju }; 950b8545f9dSAswath Govindraju 951b8545f9dSAswath Govindraju mailbox1_cluster8: mailbox@31f98000 { 952b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 953b8545f9dSAswath Govindraju reg = <0x00 0x31f98000 0x00 0x200>; 954b8545f9dSAswath Govindraju #mbox-cells = <1>; 955b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 956b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 957b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9583fb0402fSAndrew Davis status = "disabled"; 959b8545f9dSAswath Govindraju }; 960b8545f9dSAswath Govindraju 961b8545f9dSAswath Govindraju mailbox1_cluster9: mailbox@31f99000 { 962b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 963b8545f9dSAswath Govindraju reg = <0x00 0x31f99000 0x00 0x200>; 964b8545f9dSAswath Govindraju #mbox-cells = <1>; 965b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 966b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 967b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9683fb0402fSAndrew Davis status = "disabled"; 969b8545f9dSAswath Govindraju }; 970b8545f9dSAswath Govindraju 971b8545f9dSAswath Govindraju mailbox1_cluster10: mailbox@31f9a000 { 972b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 973b8545f9dSAswath Govindraju reg = <0x00 0x31f9a000 0x00 0x200>; 974b8545f9dSAswath Govindraju #mbox-cells = <1>; 975b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 976b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 977b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9783fb0402fSAndrew Davis status = "disabled"; 979b8545f9dSAswath Govindraju }; 980b8545f9dSAswath Govindraju 981b8545f9dSAswath Govindraju mailbox1_cluster11: mailbox@31f9b000 { 982b8545f9dSAswath Govindraju compatible = "ti,am654-mailbox"; 983b8545f9dSAswath Govindraju reg = <0x00 0x31f9b000 0x00 0x200>; 984b8545f9dSAswath Govindraju #mbox-cells = <1>; 985b8545f9dSAswath Govindraju ti,mbox-num-users = <4>; 986b8545f9dSAswath Govindraju ti,mbox-num-fifos = <16>; 987b8545f9dSAswath Govindraju interrupt-parent = <&main_navss_intr>; 9883fb0402fSAndrew Davis status = "disabled"; 989b8545f9dSAswath Govindraju }; 990b8545f9dSAswath Govindraju 991b8545f9dSAswath Govindraju main_ringacc: ringacc@3c000000 { 992b8545f9dSAswath Govindraju compatible = "ti,am654-navss-ringacc"; 993b8545f9dSAswath Govindraju reg = <0x0 0x3c000000 0x0 0x400000>, 994b8545f9dSAswath Govindraju <0x0 0x38000000 0x0 0x400000>, 995b8545f9dSAswath Govindraju <0x0 0x31120000 0x0 0x100>, 996b8545f9dSAswath Govindraju <0x0 0x33000000 0x0 0x40000>; 997b8545f9dSAswath Govindraju reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 998b8545f9dSAswath Govindraju ti,num-rings = <1024>; 999b8545f9dSAswath Govindraju ti,sci-rm-range-gp-rings = <0x1>; 1000b8545f9dSAswath Govindraju ti,sci = <&sms>; 1001b8545f9dSAswath Govindraju ti,sci-dev-id = <259>; 1002b8545f9dSAswath Govindraju msi-parent = <&main_udmass_inta>; 1003b8545f9dSAswath Govindraju }; 1004b8545f9dSAswath Govindraju 1005b8545f9dSAswath Govindraju main_udmap: dma-controller@31150000 { 1006b8545f9dSAswath Govindraju compatible = "ti,j721e-navss-main-udmap"; 1007b8545f9dSAswath Govindraju reg = <0x0 0x31150000 0x0 0x100>, 1008b8545f9dSAswath Govindraju <0x0 0x34000000 0x0 0x80000>, 1009b8545f9dSAswath Govindraju <0x0 0x35000000 0x0 0x200000>; 1010b8545f9dSAswath Govindraju reg-names = "gcfg", "rchanrt", "tchanrt"; 1011b8545f9dSAswath Govindraju msi-parent = <&main_udmass_inta>; 1012b8545f9dSAswath Govindraju #dma-cells = <1>; 1013b8545f9dSAswath Govindraju 1014b8545f9dSAswath Govindraju ti,sci = <&sms>; 1015b8545f9dSAswath Govindraju ti,sci-dev-id = <263>; 1016b8545f9dSAswath Govindraju ti,ringacc = <&main_ringacc>; 1017b8545f9dSAswath Govindraju 1018b8545f9dSAswath Govindraju ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1019b8545f9dSAswath Govindraju <0x0f>, /* TX_HCHAN */ 1020b8545f9dSAswath Govindraju <0x10>; /* TX_UHCHAN */ 1021b8545f9dSAswath Govindraju ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1022b8545f9dSAswath Govindraju <0x0b>, /* RX_HCHAN */ 1023b8545f9dSAswath Govindraju <0x0c>; /* RX_UHCHAN */ 1024b8545f9dSAswath Govindraju ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1025b8545f9dSAswath Govindraju }; 1026b8545f9dSAswath Govindraju 1027b8545f9dSAswath Govindraju cpts@310d0000 { 1028b8545f9dSAswath Govindraju compatible = "ti,j721e-cpts"; 1029b8545f9dSAswath Govindraju reg = <0x0 0x310d0000 0x0 0x400>; 1030b8545f9dSAswath Govindraju reg-names = "cpts"; 1031b8545f9dSAswath Govindraju clocks = <&k3_clks 226 5>; 1032b8545f9dSAswath Govindraju clock-names = "cpts"; 1033*1f36d0e8SNeha Malcom Francis assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ 1034*1f36d0e8SNeha Malcom Francis assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ 1035b8545f9dSAswath Govindraju interrupts-extended = <&main_navss_intr 391>; 1036b8545f9dSAswath Govindraju interrupt-names = "cpts"; 1037b8545f9dSAswath Govindraju ti,cpts-periodic-outputs = <6>; 1038b8545f9dSAswath Govindraju ti,cpts-ext-ts-inputs = <8>; 1039b8545f9dSAswath Govindraju }; 1040b8545f9dSAswath Govindraju }; 1041b8545f9dSAswath Govindraju 104220fcf9d6SAswath Govindraju usbss0: cdns-usb@4104000 { 104320fcf9d6SAswath Govindraju compatible = "ti,j721e-usb"; 104420fcf9d6SAswath Govindraju reg = <0x00 0x04104000 0x00 0x100>; 104520fcf9d6SAswath Govindraju clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; 104620fcf9d6SAswath Govindraju clock-names = "ref", "lpm"; 104720fcf9d6SAswath Govindraju assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ 104820fcf9d6SAswath Govindraju assigned-clock-parents = <&k3_clks 360 17>; 104920fcf9d6SAswath Govindraju power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 105020fcf9d6SAswath Govindraju #address-cells = <2>; 105120fcf9d6SAswath Govindraju #size-cells = <2>; 105220fcf9d6SAswath Govindraju ranges; 105320fcf9d6SAswath Govindraju dma-coherent; 105420fcf9d6SAswath Govindraju 105520fcf9d6SAswath Govindraju status = "disabled"; /* Needs pinmux */ 105620fcf9d6SAswath Govindraju 105720fcf9d6SAswath Govindraju usb0: usb@6000000 { 105820fcf9d6SAswath Govindraju compatible = "cdns,usb3"; 105920fcf9d6SAswath Govindraju reg = <0x00 0x06000000 0x00 0x10000>, 106020fcf9d6SAswath Govindraju <0x00 0x06010000 0x00 0x10000>, 106120fcf9d6SAswath Govindraju <0x00 0x06020000 0x00 0x10000>; 106220fcf9d6SAswath Govindraju reg-names = "otg", "xhci", "dev"; 106320fcf9d6SAswath Govindraju interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 106420fcf9d6SAswath Govindraju <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 106520fcf9d6SAswath Govindraju <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 106620fcf9d6SAswath Govindraju interrupt-names = "host", "peripheral", "otg"; 106720fcf9d6SAswath Govindraju maximum-speed = "super-speed"; 106820fcf9d6SAswath Govindraju dr_mode = "otg"; 106920fcf9d6SAswath Govindraju }; 107020fcf9d6SAswath Govindraju }; 107120fcf9d6SAswath Govindraju 1072393eee04SMatt Ranostay serdes_wiz0: wiz@5060000 { 1073393eee04SMatt Ranostay compatible = "ti,j721s2-wiz-10g"; 1074393eee04SMatt Ranostay #address-cells = <1>; 1075393eee04SMatt Ranostay #size-cells = <1>; 1076393eee04SMatt Ranostay power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 1077393eee04SMatt Ranostay clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; 1078393eee04SMatt Ranostay clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1079393eee04SMatt Ranostay num-lanes = <4>; 1080393eee04SMatt Ranostay #reset-cells = <1>; 1081393eee04SMatt Ranostay #clock-cells = <1>; 1082393eee04SMatt Ranostay ranges = <0x5060000 0x0 0x5060000 0x10000>; 1083393eee04SMatt Ranostay 1084393eee04SMatt Ranostay assigned-clocks = <&k3_clks 365 3>; 1085393eee04SMatt Ranostay assigned-clock-parents = <&k3_clks 365 7>; 1086393eee04SMatt Ranostay 1087393eee04SMatt Ranostay serdes0: serdes@5060000 { 1088393eee04SMatt Ranostay compatible = "ti,j721e-serdes-10g"; 1089393eee04SMatt Ranostay reg = <0x05060000 0x00010000>; 1090393eee04SMatt Ranostay reg-names = "torrent_phy"; 1091393eee04SMatt Ranostay resets = <&serdes_wiz0 0>; 1092393eee04SMatt Ranostay reset-names = "torrent_reset"; 1093393eee04SMatt Ranostay clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1094393eee04SMatt Ranostay <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1095393eee04SMatt Ranostay clock-names = "refclk", "phy_en_refclk"; 1096393eee04SMatt Ranostay assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1097393eee04SMatt Ranostay <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1098393eee04SMatt Ranostay <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1099393eee04SMatt Ranostay assigned-clock-parents = <&k3_clks 365 3>, 1100393eee04SMatt Ranostay <&k3_clks 365 3>, 1101393eee04SMatt Ranostay <&k3_clks 365 3>; 1102393eee04SMatt Ranostay #address-cells = <1>; 1103393eee04SMatt Ranostay #size-cells = <0>; 1104393eee04SMatt Ranostay #clock-cells = <1>; 1105393eee04SMatt Ranostay 1106393eee04SMatt Ranostay status = "disabled"; /* Needs lane config */ 1107393eee04SMatt Ranostay }; 1108393eee04SMatt Ranostay }; 1109393eee04SMatt Ranostay 1110b6f18aa8SAswath Govindraju pcie1_rc: pcie@2910000 { 1111b6f18aa8SAswath Govindraju compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 1112b6f18aa8SAswath Govindraju reg = <0x00 0x02910000 0x00 0x1000>, 1113b6f18aa8SAswath Govindraju <0x00 0x02917000 0x00 0x400>, 1114b6f18aa8SAswath Govindraju <0x00 0x0d800000 0x00 0x800000>, 1115b6f18aa8SAswath Govindraju <0x00 0x18000000 0x00 0x1000>; 1116b6f18aa8SAswath Govindraju reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1117b6f18aa8SAswath Govindraju interrupt-names = "link_state"; 1118b6f18aa8SAswath Govindraju interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1119b6f18aa8SAswath Govindraju device_type = "pci"; 1120b6f18aa8SAswath Govindraju ti,syscon-pcie-ctrl = <&scm_conf 0x074>; 1121b6f18aa8SAswath Govindraju max-link-speed = <3>; 1122b6f18aa8SAswath Govindraju num-lanes = <4>; 1123b6f18aa8SAswath Govindraju power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 1124b6f18aa8SAswath Govindraju clocks = <&k3_clks 276 41>; 1125b6f18aa8SAswath Govindraju clock-names = "fck"; 1126b6f18aa8SAswath Govindraju #address-cells = <3>; 1127b6f18aa8SAswath Govindraju #size-cells = <2>; 1128b6f18aa8SAswath Govindraju bus-range = <0x0 0xff>; 1129b6f18aa8SAswath Govindraju vendor-id = <0x104c>; 1130b6f18aa8SAswath Govindraju device-id = <0xb013>; 1131b6f18aa8SAswath Govindraju msi-map = <0x0 &gic_its 0x0 0x10000>; 1132b6f18aa8SAswath Govindraju dma-coherent; 1133b6f18aa8SAswath Govindraju ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1134b6f18aa8SAswath Govindraju <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1135b6f18aa8SAswath Govindraju dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1136b6f18aa8SAswath Govindraju #interrupt-cells = <1>; 1137b6f18aa8SAswath Govindraju interrupt-map-mask = <0 0 0 7>; 1138b6f18aa8SAswath Govindraju interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ 1139b6f18aa8SAswath Govindraju <0 0 0 2 &pcie1_intc 0>, /* INT B */ 1140b6f18aa8SAswath Govindraju <0 0 0 3 &pcie1_intc 0>, /* INT C */ 1141b6f18aa8SAswath Govindraju <0 0 0 4 &pcie1_intc 0>; /* INT D */ 1142b6f18aa8SAswath Govindraju 1143b6f18aa8SAswath Govindraju status = "disabled"; /* Needs gpio and serdes info */ 1144b6f18aa8SAswath Govindraju 1145b6f18aa8SAswath Govindraju pcie1_intc: interrupt-controller { 1146b6f18aa8SAswath Govindraju interrupt-controller; 1147b6f18aa8SAswath Govindraju #interrupt-cells = <1>; 1148b6f18aa8SAswath Govindraju interrupt-parent = <&gic500>; 1149b6f18aa8SAswath Govindraju interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>; 1150b6f18aa8SAswath Govindraju }; 1151b6f18aa8SAswath Govindraju }; 1152b6f18aa8SAswath Govindraju 1153b8545f9dSAswath Govindraju main_mcan0: can@2701000 { 1154b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1155b8545f9dSAswath Govindraju reg = <0x00 0x02701000 0x00 0x200>, 1156b8545f9dSAswath Govindraju <0x00 0x02708000 0x00 0x8000>; 1157b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1158b8545f9dSAswath Govindraju power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1159b8545f9dSAswath Govindraju clocks = <&k3_clks 182 0>, <&k3_clks 182 1>; 1160b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1161b8545f9dSAswath Govindraju interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1162b8545f9dSAswath Govindraju <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1163b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1164b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 116506639b8aSAndrew Davis status = "disabled"; 1166b8545f9dSAswath Govindraju }; 1167b8545f9dSAswath Govindraju 1168b8545f9dSAswath Govindraju main_mcan1: can@2711000 { 1169b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1170b8545f9dSAswath Govindraju reg = <0x00 0x02711000 0x00 0x200>, 1171b8545f9dSAswath Govindraju <0x00 0x02718000 0x00 0x8000>; 1172b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1173b8545f9dSAswath Govindraju power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 1174b8545f9dSAswath Govindraju clocks = <&k3_clks 183 0>, <&k3_clks 183 1>; 1175b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1176b8545f9dSAswath Govindraju interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1177b8545f9dSAswath Govindraju <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1178b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1179b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 118006639b8aSAndrew Davis status = "disabled"; 1181b8545f9dSAswath Govindraju }; 1182b8545f9dSAswath Govindraju 1183b8545f9dSAswath Govindraju main_mcan2: can@2721000 { 1184b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1185b8545f9dSAswath Govindraju reg = <0x00 0x02721000 0x00 0x200>, 1186b8545f9dSAswath Govindraju <0x00 0x02728000 0x00 0x8000>; 1187b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1188b8545f9dSAswath Govindraju power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 1189b8545f9dSAswath Govindraju clocks = <&k3_clks 184 0>, <&k3_clks 184 1>; 1190b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1191b8545f9dSAswath Govindraju interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1192b8545f9dSAswath Govindraju <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1193b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1194b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 119506639b8aSAndrew Davis status = "disabled"; 1196b8545f9dSAswath Govindraju }; 1197b8545f9dSAswath Govindraju 1198b8545f9dSAswath Govindraju main_mcan3: can@2731000 { 1199b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1200b8545f9dSAswath Govindraju reg = <0x00 0x02731000 0x00 0x200>, 1201b8545f9dSAswath Govindraju <0x00 0x02738000 0x00 0x8000>; 1202b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1203b8545f9dSAswath Govindraju power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1204b8545f9dSAswath Govindraju clocks = <&k3_clks 185 0>, <&k3_clks 185 1>; 1205b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1206b8545f9dSAswath Govindraju interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1207b8545f9dSAswath Govindraju <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1208b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1209b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 121006639b8aSAndrew Davis status = "disabled"; 1211b8545f9dSAswath Govindraju }; 1212b8545f9dSAswath Govindraju 1213b8545f9dSAswath Govindraju main_mcan4: can@2741000 { 1214b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1215b8545f9dSAswath Govindraju reg = <0x00 0x02741000 0x00 0x200>, 1216b8545f9dSAswath Govindraju <0x00 0x02748000 0x00 0x8000>; 1217b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1218b8545f9dSAswath Govindraju power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1219b8545f9dSAswath Govindraju clocks = <&k3_clks 186 0>, <&k3_clks 186 1>; 1220b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1221b8545f9dSAswath Govindraju interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1222b8545f9dSAswath Govindraju <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1223b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1224b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 122506639b8aSAndrew Davis status = "disabled"; 1226b8545f9dSAswath Govindraju }; 1227b8545f9dSAswath Govindraju 1228b8545f9dSAswath Govindraju main_mcan5: can@2751000 { 1229b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1230b8545f9dSAswath Govindraju reg = <0x00 0x02751000 0x00 0x200>, 1231b8545f9dSAswath Govindraju <0x00 0x02758000 0x00 0x8000>; 1232b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1233b8545f9dSAswath Govindraju power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; 1234b8545f9dSAswath Govindraju clocks = <&k3_clks 187 0>, <&k3_clks 187 1>; 1235b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1236b8545f9dSAswath Govindraju interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1237b8545f9dSAswath Govindraju <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1238b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1239b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 124006639b8aSAndrew Davis status = "disabled"; 1241b8545f9dSAswath Govindraju }; 1242b8545f9dSAswath Govindraju 1243b8545f9dSAswath Govindraju main_mcan6: can@2761000 { 1244b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1245b8545f9dSAswath Govindraju reg = <0x00 0x02761000 0x00 0x200>, 1246b8545f9dSAswath Govindraju <0x00 0x02768000 0x00 0x8000>; 1247b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1248b8545f9dSAswath Govindraju power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1249b8545f9dSAswath Govindraju clocks = <&k3_clks 188 0>, <&k3_clks 188 1>; 1250b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1251b8545f9dSAswath Govindraju interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1252b8545f9dSAswath Govindraju <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1253b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1254b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 125506639b8aSAndrew Davis status = "disabled"; 1256b8545f9dSAswath Govindraju }; 1257b8545f9dSAswath Govindraju 1258b8545f9dSAswath Govindraju main_mcan7: can@2771000 { 1259b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1260b8545f9dSAswath Govindraju reg = <0x00 0x02771000 0x00 0x200>, 1261b8545f9dSAswath Govindraju <0x00 0x02778000 0x00 0x8000>; 1262b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1263b8545f9dSAswath Govindraju power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1264b8545f9dSAswath Govindraju clocks = <&k3_clks 189 0>, <&k3_clks 189 1>; 1265b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1266b8545f9dSAswath Govindraju interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1267b8545f9dSAswath Govindraju <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1268b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1269b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 127006639b8aSAndrew Davis status = "disabled"; 1271b8545f9dSAswath Govindraju }; 1272b8545f9dSAswath Govindraju 1273b8545f9dSAswath Govindraju main_mcan8: can@2781000 { 1274b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1275b8545f9dSAswath Govindraju reg = <0x00 0x02781000 0x00 0x200>, 1276b8545f9dSAswath Govindraju <0x00 0x02788000 0x00 0x8000>; 1277b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1278b8545f9dSAswath Govindraju power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1279b8545f9dSAswath Govindraju clocks = <&k3_clks 190 0>, <&k3_clks 190 1>; 1280b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1281b8545f9dSAswath Govindraju interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1282b8545f9dSAswath Govindraju <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1283b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1284b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 128506639b8aSAndrew Davis status = "disabled"; 1286b8545f9dSAswath Govindraju }; 1287b8545f9dSAswath Govindraju 1288b8545f9dSAswath Govindraju main_mcan9: can@2791000 { 1289b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1290b8545f9dSAswath Govindraju reg = <0x00 0x02791000 0x00 0x200>, 1291b8545f9dSAswath Govindraju <0x00 0x02798000 0x00 0x8000>; 1292b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1293b8545f9dSAswath Govindraju power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1294b8545f9dSAswath Govindraju clocks = <&k3_clks 191 0>, <&k3_clks 191 1>; 1295b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1296b8545f9dSAswath Govindraju interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1297b8545f9dSAswath Govindraju <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1298b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1299b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 130006639b8aSAndrew Davis status = "disabled"; 1301b8545f9dSAswath Govindraju }; 1302b8545f9dSAswath Govindraju 1303b8545f9dSAswath Govindraju main_mcan10: can@27a1000 { 1304b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1305b8545f9dSAswath Govindraju reg = <0x00 0x027a1000 0x00 0x200>, 1306b8545f9dSAswath Govindraju <0x00 0x027a8000 0x00 0x8000>; 1307b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1308b8545f9dSAswath Govindraju power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1309b8545f9dSAswath Govindraju clocks = <&k3_clks 192 0>, <&k3_clks 192 1>; 1310b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1311b8545f9dSAswath Govindraju interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1312b8545f9dSAswath Govindraju <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1313b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1314b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 131506639b8aSAndrew Davis status = "disabled"; 1316b8545f9dSAswath Govindraju }; 1317b8545f9dSAswath Govindraju 1318b8545f9dSAswath Govindraju main_mcan11: can@27b1000 { 1319b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1320b8545f9dSAswath Govindraju reg = <0x00 0x027b1000 0x00 0x200>, 1321b8545f9dSAswath Govindraju <0x00 0x027b8000 0x00 0x8000>; 1322b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1323b8545f9dSAswath Govindraju power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1324b8545f9dSAswath Govindraju clocks = <&k3_clks 193 0>, <&k3_clks 193 1>; 1325b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1326b8545f9dSAswath Govindraju interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1327b8545f9dSAswath Govindraju <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1328b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1329b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 133006639b8aSAndrew Davis status = "disabled"; 1331b8545f9dSAswath Govindraju }; 1332b8545f9dSAswath Govindraju 1333b8545f9dSAswath Govindraju main_mcan12: can@27c1000 { 1334b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1335b8545f9dSAswath Govindraju reg = <0x00 0x027c1000 0x00 0x200>, 1336b8545f9dSAswath Govindraju <0x00 0x027c8000 0x00 0x8000>; 1337b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1338b8545f9dSAswath Govindraju power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 1339b8545f9dSAswath Govindraju clocks = <&k3_clks 194 0>, <&k3_clks 194 1>; 1340b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1341b8545f9dSAswath Govindraju interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1342b8545f9dSAswath Govindraju <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1343b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1344b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 134506639b8aSAndrew Davis status = "disabled"; 1346b8545f9dSAswath Govindraju }; 1347b8545f9dSAswath Govindraju 1348b8545f9dSAswath Govindraju main_mcan13: can@27d1000 { 1349b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1350b8545f9dSAswath Govindraju reg = <0x00 0x027d1000 0x00 0x200>, 1351b8545f9dSAswath Govindraju <0x00 0x027d8000 0x00 0x8000>; 1352b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1353b8545f9dSAswath Govindraju power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 1354b8545f9dSAswath Govindraju clocks = <&k3_clks 195 0>, <&k3_clks 195 1>; 1355b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1356b8545f9dSAswath Govindraju interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1357b8545f9dSAswath Govindraju <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1358b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1359b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 136006639b8aSAndrew Davis status = "disabled"; 1361b8545f9dSAswath Govindraju }; 1362b8545f9dSAswath Govindraju 1363b8545f9dSAswath Govindraju main_mcan14: can@2681000 { 1364b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1365b8545f9dSAswath Govindraju reg = <0x00 0x02681000 0x00 0x200>, 1366b8545f9dSAswath Govindraju <0x00 0x02688000 0x00 0x8000>; 1367b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1368b8545f9dSAswath Govindraju power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>; 1369b8545f9dSAswath Govindraju clocks = <&k3_clks 197 0>, <&k3_clks 197 1>; 1370b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1371b8545f9dSAswath Govindraju interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1372b8545f9dSAswath Govindraju <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1373b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1374b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 137506639b8aSAndrew Davis status = "disabled"; 1376b8545f9dSAswath Govindraju }; 1377b8545f9dSAswath Govindraju 1378b8545f9dSAswath Govindraju main_mcan15: can@2691000 { 1379b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1380b8545f9dSAswath Govindraju reg = <0x00 0x02691000 0x00 0x200>, 1381b8545f9dSAswath Govindraju <0x00 0x02698000 0x00 0x8000>; 1382b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1383b8545f9dSAswath Govindraju power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>; 1384b8545f9dSAswath Govindraju clocks = <&k3_clks 199 0>, <&k3_clks 199 1>; 1385b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1386b8545f9dSAswath Govindraju interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1387b8545f9dSAswath Govindraju <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 1388b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1389b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 139006639b8aSAndrew Davis status = "disabled"; 1391b8545f9dSAswath Govindraju }; 1392b8545f9dSAswath Govindraju 1393b8545f9dSAswath Govindraju main_mcan16: can@26a1000 { 1394b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1395b8545f9dSAswath Govindraju reg = <0x00 0x026a1000 0x00 0x200>, 1396b8545f9dSAswath Govindraju <0x00 0x026a8000 0x00 0x8000>; 1397b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1398b8545f9dSAswath Govindraju power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1399b8545f9dSAswath Govindraju clocks = <&k3_clks 201 0>, <&k3_clks 201 1>; 1400b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1401b8545f9dSAswath Govindraju interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1402b8545f9dSAswath Govindraju <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1403b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1404b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 140506639b8aSAndrew Davis status = "disabled"; 1406b8545f9dSAswath Govindraju }; 1407b8545f9dSAswath Govindraju 1408b8545f9dSAswath Govindraju main_mcan17: can@26b1000 { 1409b8545f9dSAswath Govindraju compatible = "bosch,m_can"; 1410b8545f9dSAswath Govindraju reg = <0x00 0x026b1000 0x00 0x200>, 1411b8545f9dSAswath Govindraju <0x00 0x026b8000 0x00 0x8000>; 1412b8545f9dSAswath Govindraju reg-names = "m_can", "message_ram"; 1413b8545f9dSAswath Govindraju power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>; 1414b8545f9dSAswath Govindraju clocks = <&k3_clks 206 0>, <&k3_clks 206 1>; 1415b8545f9dSAswath Govindraju clock-names = "hclk", "cclk"; 1416b8545f9dSAswath Govindraju interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1417b8545f9dSAswath Govindraju <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1418b8545f9dSAswath Govindraju interrupt-names = "int0", "int1"; 1419b8545f9dSAswath Govindraju bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 142006639b8aSAndrew Davis status = "disabled"; 1421b8545f9dSAswath Govindraju }; 142204d7cb64SVaishnav Achath 142304d7cb64SVaishnav Achath main_spi0: spi@2100000 { 142404d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 142504d7cb64SVaishnav Achath reg = <0x00 0x02100000 0x00 0x400>; 142604d7cb64SVaishnav Achath interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 142704d7cb64SVaishnav Achath #address-cells = <1>; 142804d7cb64SVaishnav Achath #size-cells = <0>; 142904d7cb64SVaishnav Achath power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 143004d7cb64SVaishnav Achath clocks = <&k3_clks 339 1>; 143104d7cb64SVaishnav Achath status = "disabled"; 143204d7cb64SVaishnav Achath }; 143304d7cb64SVaishnav Achath 143404d7cb64SVaishnav Achath main_spi1: spi@2110000 { 143504d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 143604d7cb64SVaishnav Achath reg = <0x00 0x02110000 0x00 0x400>; 143704d7cb64SVaishnav Achath interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 143804d7cb64SVaishnav Achath #address-cells = <1>; 143904d7cb64SVaishnav Achath #size-cells = <0>; 144004d7cb64SVaishnav Achath power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 144104d7cb64SVaishnav Achath clocks = <&k3_clks 340 1>; 144204d7cb64SVaishnav Achath status = "disabled"; 144304d7cb64SVaishnav Achath }; 144404d7cb64SVaishnav Achath 144504d7cb64SVaishnav Achath main_spi2: spi@2120000 { 144604d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 144704d7cb64SVaishnav Achath reg = <0x00 0x02120000 0x00 0x400>; 144804d7cb64SVaishnav Achath interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 144904d7cb64SVaishnav Achath #address-cells = <1>; 145004d7cb64SVaishnav Achath #size-cells = <0>; 145104d7cb64SVaishnav Achath power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 145204d7cb64SVaishnav Achath clocks = <&k3_clks 341 1>; 145304d7cb64SVaishnav Achath status = "disabled"; 145404d7cb64SVaishnav Achath }; 145504d7cb64SVaishnav Achath 145604d7cb64SVaishnav Achath main_spi3: spi@2130000 { 145704d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 145804d7cb64SVaishnav Achath reg = <0x00 0x02130000 0x00 0x400>; 145904d7cb64SVaishnav Achath interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 146004d7cb64SVaishnav Achath #address-cells = <1>; 146104d7cb64SVaishnav Achath #size-cells = <0>; 146204d7cb64SVaishnav Achath power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 146304d7cb64SVaishnav Achath clocks = <&k3_clks 342 1>; 146404d7cb64SVaishnav Achath status = "disabled"; 146504d7cb64SVaishnav Achath }; 146604d7cb64SVaishnav Achath 146704d7cb64SVaishnav Achath main_spi4: spi@2140000 { 146804d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 146904d7cb64SVaishnav Achath reg = <0x00 0x02140000 0x00 0x400>; 147004d7cb64SVaishnav Achath interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 147104d7cb64SVaishnav Achath #address-cells = <1>; 147204d7cb64SVaishnav Achath #size-cells = <0>; 147304d7cb64SVaishnav Achath power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 147404d7cb64SVaishnav Achath clocks = <&k3_clks 343 1>; 147504d7cb64SVaishnav Achath status = "disabled"; 147604d7cb64SVaishnav Achath }; 147704d7cb64SVaishnav Achath 147804d7cb64SVaishnav Achath main_spi5: spi@2150000 { 147904d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 148004d7cb64SVaishnav Achath reg = <0x00 0x02150000 0x00 0x400>; 148104d7cb64SVaishnav Achath interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 148204d7cb64SVaishnav Achath #address-cells = <1>; 148304d7cb64SVaishnav Achath #size-cells = <0>; 148404d7cb64SVaishnav Achath power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 148504d7cb64SVaishnav Achath clocks = <&k3_clks 344 1>; 148604d7cb64SVaishnav Achath status = "disabled"; 148704d7cb64SVaishnav Achath }; 148804d7cb64SVaishnav Achath 148904d7cb64SVaishnav Achath main_spi6: spi@2160000 { 149004d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 149104d7cb64SVaishnav Achath reg = <0x00 0x02160000 0x00 0x400>; 149204d7cb64SVaishnav Achath interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 149304d7cb64SVaishnav Achath #address-cells = <1>; 149404d7cb64SVaishnav Achath #size-cells = <0>; 149504d7cb64SVaishnav Achath power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 149604d7cb64SVaishnav Achath clocks = <&k3_clks 345 1>; 149704d7cb64SVaishnav Achath status = "disabled"; 149804d7cb64SVaishnav Achath }; 149904d7cb64SVaishnav Achath 150004d7cb64SVaishnav Achath main_spi7: spi@2170000 { 150104d7cb64SVaishnav Achath compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 150204d7cb64SVaishnav Achath reg = <0x00 0x02170000 0x00 0x400>; 150304d7cb64SVaishnav Achath interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 150404d7cb64SVaishnav Achath #address-cells = <1>; 150504d7cb64SVaishnav Achath #size-cells = <0>; 150604d7cb64SVaishnav Achath power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 150704d7cb64SVaishnav Achath clocks = <&k3_clks 346 1>; 150804d7cb64SVaishnav Achath status = "disabled"; 150904d7cb64SVaishnav Achath }; 1510b8545f9dSAswath Govindraju}; 1511