12d87061eSNishanth Menon// SPDX-License-Identifier: GPL-2.0 22d87061eSNishanth Menon/* 32d87061eSNishanth Menon * Device Tree Source for J721E SoC Family 42d87061eSNishanth Menon * 52d87061eSNishanth Menon * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ 62d87061eSNishanth Menon */ 72d87061eSNishanth Menon 82d87061eSNishanth Menon#include <dt-bindings/interrupt-controller/irq.h> 92d87061eSNishanth Menon#include <dt-bindings/interrupt-controller/arm-gic.h> 102d87061eSNishanth Menon#include <dt-bindings/pinctrl/k3.h> 112d87061eSNishanth Menon 122d87061eSNishanth Menon/ { 132d87061eSNishanth Menon model = "Texas Instruments K3 J721E SoC"; 142d87061eSNishanth Menon compatible = "ti,j721e"; 152d87061eSNishanth Menon interrupt-parent = <&gic500>; 162d87061eSNishanth Menon #address-cells = <2>; 172d87061eSNishanth Menon #size-cells = <2>; 182d87061eSNishanth Menon 192d87061eSNishanth Menon aliases { 202d87061eSNishanth Menon serial0 = &wkup_uart0; 212d87061eSNishanth Menon serial1 = &mcu_uart0; 222d87061eSNishanth Menon serial2 = &main_uart0; 232d87061eSNishanth Menon serial3 = &main_uart1; 242d87061eSNishanth Menon serial4 = &main_uart2; 252d87061eSNishanth Menon serial5 = &main_uart3; 262d87061eSNishanth Menon serial6 = &main_uart4; 272d87061eSNishanth Menon serial7 = &main_uart5; 282d87061eSNishanth Menon serial8 = &main_uart6; 292d87061eSNishanth Menon serial9 = &main_uart7; 302d87061eSNishanth Menon serial10 = &main_uart8; 312d87061eSNishanth Menon serial11 = &main_uart9; 322d87061eSNishanth Menon }; 332d87061eSNishanth Menon 342d87061eSNishanth Menon chosen { }; 352d87061eSNishanth Menon 362d87061eSNishanth Menon cpus { 372d87061eSNishanth Menon #address-cells = <1>; 382d87061eSNishanth Menon #size-cells = <0>; 392d87061eSNishanth Menon cpu-map { 402d87061eSNishanth Menon cluster0: cluster0 { 412d87061eSNishanth Menon core0 { 422d87061eSNishanth Menon cpu = <&cpu0>; 432d87061eSNishanth Menon }; 442d87061eSNishanth Menon 452d87061eSNishanth Menon core1 { 462d87061eSNishanth Menon cpu = <&cpu1>; 472d87061eSNishanth Menon }; 482d87061eSNishanth Menon }; 492d87061eSNishanth Menon 502d87061eSNishanth Menon }; 512d87061eSNishanth Menon 522d87061eSNishanth Menon cpu0: cpu@0 { 532d87061eSNishanth Menon compatible = "arm,cortex-a72"; 542d87061eSNishanth Menon reg = <0x000>; 552d87061eSNishanth Menon device_type = "cpu"; 562d87061eSNishanth Menon enable-method = "psci"; 572d87061eSNishanth Menon i-cache-size = <0xC000>; 582d87061eSNishanth Menon i-cache-line-size = <64>; 592d87061eSNishanth Menon i-cache-sets = <256>; 602d87061eSNishanth Menon d-cache-size = <0x8000>; 612d87061eSNishanth Menon d-cache-line-size = <64>; 622d87061eSNishanth Menon d-cache-sets = <128>; 632d87061eSNishanth Menon next-level-cache = <&L2_0>; 642d87061eSNishanth Menon }; 652d87061eSNishanth Menon 662d87061eSNishanth Menon cpu1: cpu@1 { 672d87061eSNishanth Menon compatible = "arm,cortex-a72"; 682d87061eSNishanth Menon reg = <0x001>; 692d87061eSNishanth Menon device_type = "cpu"; 702d87061eSNishanth Menon enable-method = "psci"; 712d87061eSNishanth Menon i-cache-size = <0xC000>; 722d87061eSNishanth Menon i-cache-line-size = <64>; 732d87061eSNishanth Menon i-cache-sets = <256>; 742d87061eSNishanth Menon d-cache-size = <0x8000>; 752d87061eSNishanth Menon d-cache-line-size = <64>; 762d87061eSNishanth Menon d-cache-sets = <128>; 772d87061eSNishanth Menon next-level-cache = <&L2_0>; 782d87061eSNishanth Menon }; 792d87061eSNishanth Menon }; 802d87061eSNishanth Menon 812d87061eSNishanth Menon L2_0: l2-cache0 { 822d87061eSNishanth Menon compatible = "cache"; 832d87061eSNishanth Menon cache-level = <2>; 842d87061eSNishanth Menon cache-size = <0x100000>; 852d87061eSNishanth Menon cache-line-size = <64>; 862d87061eSNishanth Menon cache-sets = <2048>; 872d87061eSNishanth Menon next-level-cache = <&msmc_l3>; 882d87061eSNishanth Menon }; 892d87061eSNishanth Menon 902d87061eSNishanth Menon msmc_l3: l3-cache0 { 912d87061eSNishanth Menon compatible = "cache"; 922d87061eSNishanth Menon cache-level = <3>; 932d87061eSNishanth Menon }; 942d87061eSNishanth Menon 952d87061eSNishanth Menon firmware { 962d87061eSNishanth Menon optee { 972d87061eSNishanth Menon compatible = "linaro,optee-tz"; 982d87061eSNishanth Menon method = "smc"; 992d87061eSNishanth Menon }; 1002d87061eSNishanth Menon 1012d87061eSNishanth Menon psci: psci { 1022d87061eSNishanth Menon compatible = "arm,psci-1.0"; 1032d87061eSNishanth Menon method = "smc"; 1042d87061eSNishanth Menon }; 1052d87061eSNishanth Menon }; 1062d87061eSNishanth Menon 1072d87061eSNishanth Menon a72_timer0: timer-cl0-cpu0 { 1082d87061eSNishanth Menon compatible = "arm,armv8-timer"; 1092d87061eSNishanth Menon interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 1102d87061eSNishanth Menon <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 1112d87061eSNishanth Menon <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 1122d87061eSNishanth Menon <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 1132d87061eSNishanth Menon }; 1142d87061eSNishanth Menon 1152d87061eSNishanth Menon pmu: pmu { 1162d87061eSNishanth Menon compatible = "arm,armv8-pmuv3"; 1172d87061eSNishanth Menon /* Recommendation from GIC500 TRM Table A.3 */ 1182d87061eSNishanth Menon interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1192d87061eSNishanth Menon }; 1202d87061eSNishanth Menon 1212d87061eSNishanth Menon cbass_main: interconnect@100000 { 1222d87061eSNishanth Menon compatible = "simple-bus"; 1232d87061eSNishanth Menon #address-cells = <2>; 1242d87061eSNishanth Menon #size-cells = <2>; 1252d87061eSNishanth Menon ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 1262d87061eSNishanth Menon <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 1272d87061eSNishanth Menon <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ 1282d87061eSNishanth Menon <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ 1292d87061eSNishanth Menon <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 1302d87061eSNishanth Menon <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ 1312d87061eSNishanth Menon <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ 1322d87061eSNishanth Menon <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ 1332d87061eSNishanth Menon <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ 1342d87061eSNishanth Menon <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ 1352d87061eSNishanth Menon <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ 1362d87061eSNishanth Menon <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 1372d87061eSNishanth Menon <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 1382d87061eSNishanth Menon 1392d87061eSNishanth Menon /* MCUSS_WKUP Range */ 1402d87061eSNishanth Menon <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 1412d87061eSNishanth Menon <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 1422d87061eSNishanth Menon <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 1432d87061eSNishanth Menon <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 1442d87061eSNishanth Menon <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 1452d87061eSNishanth Menon <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 1462d87061eSNishanth Menon <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 1472d87061eSNishanth Menon <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 1482d87061eSNishanth Menon <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 1492d87061eSNishanth Menon <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 1502d87061eSNishanth Menon <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 1512d87061eSNishanth Menon <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 1522d87061eSNishanth Menon <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 1532d87061eSNishanth Menon 1542d87061eSNishanth Menon cbass_mcu_wakeup: interconnect@28380000 { 1552d87061eSNishanth Menon compatible = "simple-bus"; 1562d87061eSNishanth Menon #address-cells = <2>; 1572d87061eSNishanth Menon #size-cells = <2>; 1582d87061eSNishanth Menon ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 1592d87061eSNishanth Menon <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 1602d87061eSNishanth Menon <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 1612d87061eSNishanth Menon <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 1622d87061eSNishanth Menon <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 1632d87061eSNishanth Menon <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 1642d87061eSNishanth Menon <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 1652d87061eSNishanth Menon <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 1662d87061eSNishanth Menon <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 1672d87061eSNishanth Menon <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 1682d87061eSNishanth Menon <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 1692d87061eSNishanth Menon <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 1702d87061eSNishanth Menon <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 1712d87061eSNishanth Menon }; 1722d87061eSNishanth Menon }; 1732d87061eSNishanth Menon}; 1742d87061eSNishanth Menon 1752d87061eSNishanth Menon/* Now include the peripherals for each bus segments */ 1762d87061eSNishanth Menon#include "k3-j721e-main.dtsi" 1772d87061eSNishanth Menon#include "k3-j721e-mcu-wakeup.dtsi" 178