1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J7200 SoC Family
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/k3.h>
11#include <dt-bindings/soc/ti,sci_pm_domain.h>
12
13/ {
14	model = "Texas Instruments K3 J7200 SoC";
15	compatible = "ti,j7200";
16	interrupt-parent = <&gic500>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &wkup_uart0;
22		serial1 = &mcu_uart0;
23		serial2 = &main_uart0;
24		serial3 = &main_uart1;
25		serial4 = &main_uart2;
26		serial5 = &main_uart3;
27		serial6 = &main_uart4;
28		serial7 = &main_uart5;
29		serial8 = &main_uart6;
30		serial9 = &main_uart7;
31		serial10 = &main_uart8;
32		serial11 = &main_uart9;
33		mmc0 = &main_sdhci0;
34		mmc1 = &main_sdhci1;
35	};
36
37	chosen { };
38
39	cpus {
40		#address-cells = <1>;
41		#size-cells = <0>;
42		cpu-map {
43			cluster0: cluster0 {
44				core0 {
45					cpu = <&cpu0>;
46				};
47
48				core1 {
49					cpu = <&cpu1>;
50				};
51			};
52
53		};
54
55		cpu0: cpu@0 {
56			compatible = "arm,cortex-a72";
57			reg = <0x000>;
58			device_type = "cpu";
59			enable-method = "psci";
60			i-cache-size = <0xc000>;
61			i-cache-line-size = <64>;
62			i-cache-sets = <256>;
63			d-cache-size = <0x8000>;
64			d-cache-line-size = <64>;
65			d-cache-sets = <128>;
66			next-level-cache = <&L2_0>;
67		};
68
69		cpu1: cpu@1 {
70			compatible = "arm,cortex-a72";
71			reg = <0x001>;
72			device_type = "cpu";
73			enable-method = "psci";
74			i-cache-size = <0xc000>;
75			i-cache-line-size = <64>;
76			i-cache-sets = <256>;
77			d-cache-size = <0x8000>;
78			d-cache-line-size = <64>;
79			d-cache-sets = <128>;
80			next-level-cache = <&L2_0>;
81		};
82	};
83
84	L2_0: l2-cache0 {
85		compatible = "cache";
86		cache-level = <2>;
87		cache-size = <0x100000>;
88		cache-line-size = <64>;
89		cache-sets = <1024>;
90		next-level-cache = <&msmc_l3>;
91	};
92
93	msmc_l3: l3-cache0 {
94		compatible = "cache";
95		cache-level = <3>;
96	};
97
98	firmware {
99		optee {
100			compatible = "linaro,optee-tz";
101			method = "smc";
102		};
103
104		psci: psci {
105			compatible = "arm,psci-1.0";
106			method = "smc";
107		};
108	};
109
110	a72_timer0: timer-cl0-cpu0 {
111		compatible = "arm,armv8-timer";
112		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
113			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
114			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
115			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
116	};
117
118	pmu: pmu {
119		compatible = "arm,cortex-a72-pmu";
120		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
121	};
122
123	cbass_main: bus@100000 {
124		compatible = "simple-bus";
125		#address-cells = <2>;
126		#size-cells = <2>;
127		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
128			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
129			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
130			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
131			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
132			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
133			 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
134			 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
135
136			 /* MCUSS_WKUP Range */
137			 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
138			 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
139			 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
140			 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
141			 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
142			 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
143			 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
144			 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
145			 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
146			 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
147			 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
148			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
149			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
150
151		cbass_mcu_wakeup: bus@28380000 {
152			compatible = "simple-bus";
153			#address-cells = <2>;
154			#size-cells = <2>;
155			ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
156				 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
157				 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
158				 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
159				 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
160				 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
161				 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
162				 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
163				 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
164				 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
165				 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
166				 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
167				 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
168		};
169	};
170};
171
172/* Now include the peripherals for each bus segments */
173#include "k3-j7200-main.dtsi"
174#include "k3-j7200-mcu-wakeup.dtsi"
175