1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/k3.h> 11#include <dt-bindings/soc/ti,sci_pm_domain.h> 12 13/ { 14 model = "Texas Instruments K3 J7200 SoC"; 15 compatible = "ti,j7200"; 16 interrupt-parent = <&gic500>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &wkup_uart0; 22 serial1 = &mcu_uart0; 23 serial2 = &main_uart0; 24 serial3 = &main_uart1; 25 serial4 = &main_uart2; 26 serial5 = &main_uart3; 27 serial6 = &main_uart4; 28 serial7 = &main_uart5; 29 serial8 = &main_uart6; 30 serial9 = &main_uart7; 31 serial10 = &main_uart8; 32 serial11 = &main_uart9; 33 mmc0 = &main_sdhci0; 34 mmc1 = &main_sdhci1; 35 }; 36 37 chosen { }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 cpu-map { 43 cluster0: cluster0 { 44 core0 { 45 cpu = <&cpu0>; 46 }; 47 48 core1 { 49 cpu = <&cpu1>; 50 }; 51 }; 52 53 }; 54 55 cpu0: cpu@0 { 56 compatible = "arm,cortex-a72"; 57 reg = <0x000>; 58 device_type = "cpu"; 59 enable-method = "psci"; 60 i-cache-size = <0xc000>; 61 i-cache-line-size = <64>; 62 i-cache-sets = <256>; 63 d-cache-size = <0x8000>; 64 d-cache-line-size = <64>; 65 d-cache-sets = <256>; 66 next-level-cache = <&L2_0>; 67 }; 68 69 cpu1: cpu@1 { 70 compatible = "arm,cortex-a72"; 71 reg = <0x001>; 72 device_type = "cpu"; 73 enable-method = "psci"; 74 i-cache-size = <0xc000>; 75 i-cache-line-size = <64>; 76 i-cache-sets = <256>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <64>; 79 d-cache-sets = <256>; 80 next-level-cache = <&L2_0>; 81 }; 82 }; 83 84 L2_0: l2-cache0 { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 cache-size = <0x100000>; 89 cache-line-size = <64>; 90 cache-sets = <1024>; 91 next-level-cache = <&msmc_l3>; 92 }; 93 94 msmc_l3: l3-cache0 { 95 compatible = "cache"; 96 cache-level = <3>; 97 }; 98 99 firmware { 100 optee { 101 compatible = "linaro,optee-tz"; 102 method = "smc"; 103 }; 104 105 psci: psci { 106 compatible = "arm,psci-1.0"; 107 method = "smc"; 108 }; 109 }; 110 111 a72_timer0: timer-cl0-cpu0 { 112 compatible = "arm,armv8-timer"; 113 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 114 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 115 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 116 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 117 }; 118 119 pmu: pmu { 120 compatible = "arm,cortex-a72-pmu"; 121 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 124 cbass_main: bus@100000 { 125 compatible = "simple-bus"; 126 #address-cells = <2>; 127 #size-cells = <2>; 128 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 129 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 130 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ 131 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ 132 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 133 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 134 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 135 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ 136 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ 137 138 /* MCUSS_WKUP Range */ 139 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 140 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 141 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 142 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 143 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 144 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 145 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 146 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 147 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 148 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 149 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 150 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 151 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 152 153 cbass_mcu_wakeup: bus@28380000 { 154 compatible = "simple-bus"; 155 #address-cells = <2>; 156 #size-cells = <2>; 157 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 158 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 159 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 160 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 161 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 162 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 163 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 164 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 165 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 166 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 167 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 168 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 169 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ 170 }; 171 }; 172}; 173 174/* Now include the peripherals for each bus segments */ 175#include "k3-j7200-main.dtsi" 176#include "k3-j7200-mcu-wakeup.dtsi" 177