1d361ed88SLokesh Vutla// SPDX-License-Identifier: GPL-2.0 2d361ed88SLokesh Vutla/* 3d361ed88SLokesh Vutla * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4d361ed88SLokesh Vutla * 5eb6f3655SSuman Anna * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6d361ed88SLokesh Vutla */ 7d361ed88SLokesh Vutla 8d361ed88SLokesh Vutla&cbass_mcu_wakeup { 99d3c9378SNishanth Menon dmsc: system-controller@44083000 { 10d361ed88SLokesh Vutla compatible = "ti,k2g-sci"; 11d361ed88SLokesh Vutla ti,host-id = <12>; 12d361ed88SLokesh Vutla 13d361ed88SLokesh Vutla mbox-names = "rx", "tx"; 14d361ed88SLokesh Vutla 15d361ed88SLokesh Vutla mboxes = <&secure_proxy_main 11>, 16d361ed88SLokesh Vutla <&secure_proxy_main 13>; 17d361ed88SLokesh Vutla 18d361ed88SLokesh Vutla reg-names = "debug_messages"; 19d361ed88SLokesh Vutla reg = <0x00 0x44083000 0x00 0x1000>; 20d361ed88SLokesh Vutla 21d361ed88SLokesh Vutla k3_pds: power-controller { 22d361ed88SLokesh Vutla compatible = "ti,sci-pm-domain"; 23d361ed88SLokesh Vutla #power-domain-cells = <2>; 24d361ed88SLokesh Vutla }; 25d361ed88SLokesh Vutla 26a0812885SNishanth Menon k3_clks: clock-controller { 27d361ed88SLokesh Vutla compatible = "ti,k2g-sci-clk"; 28d361ed88SLokesh Vutla #clock-cells = <2>; 29d361ed88SLokesh Vutla }; 30d361ed88SLokesh Vutla 31d361ed88SLokesh Vutla k3_reset: reset-controller { 32d361ed88SLokesh Vutla compatible = "ti,sci-reset"; 33d361ed88SLokesh Vutla #reset-cells = <2>; 34d361ed88SLokesh Vutla }; 35d361ed88SLokesh Vutla }; 36d361ed88SLokesh Vutla 37a323da4bSGrygorii Strashko mcu_conf: syscon@40f00000 { 38a323da4bSGrygorii Strashko compatible = "syscon", "simple-mfd"; 39a323da4bSGrygorii Strashko reg = <0x00 0x40f00000 0x00 0x20000>; 40a323da4bSGrygorii Strashko #address-cells = <1>; 41a323da4bSGrygorii Strashko #size-cells = <1>; 42a323da4bSGrygorii Strashko ranges = <0x00 0x00 0x40f00000 0x20000>; 43a323da4bSGrygorii Strashko 44a323da4bSGrygorii Strashko phy_gmii_sel: phy@4040 { 45a323da4bSGrygorii Strashko compatible = "ti,am654-phy-gmii-sel"; 46a323da4bSGrygorii Strashko reg = <0x4040 0x4>; 47a323da4bSGrygorii Strashko #phy-cells = <1>; 48a323da4bSGrygorii Strashko }; 49a323da4bSGrygorii Strashko }; 50a323da4bSGrygorii Strashko 51d361ed88SLokesh Vutla chipid@43000014 { 52d361ed88SLokesh Vutla compatible = "ti,am654-chipid"; 53d361ed88SLokesh Vutla reg = <0x00 0x43000014 0x00 0x4>; 54d361ed88SLokesh Vutla }; 55d361ed88SLokesh Vutla 56d361ed88SLokesh Vutla wkup_pmx0: pinctrl@4301c000 { 57d361ed88SLokesh Vutla compatible = "pinctrl-single"; 58d361ed88SLokesh Vutla /* Proxy 0 addressing */ 59d361ed88SLokesh Vutla reg = <0x00 0x4301c000 0x00 0x178>; 60d361ed88SLokesh Vutla #pinctrl-cells = <1>; 61d361ed88SLokesh Vutla pinctrl-single,register-width = <32>; 62d361ed88SLokesh Vutla pinctrl-single,function-mask = <0xffffffff>; 63d361ed88SLokesh Vutla }; 64d361ed88SLokesh Vutla 65d361ed88SLokesh Vutla mcu_ram: sram@41c00000 { 66d361ed88SLokesh Vutla compatible = "mmio-sram"; 67d361ed88SLokesh Vutla reg = <0x00 0x41c00000 0x00 0x100000>; 68d361ed88SLokesh Vutla ranges = <0x00 0x00 0x41c00000 0x100000>; 69d361ed88SLokesh Vutla #address-cells = <1>; 70d361ed88SLokesh Vutla #size-cells = <1>; 71d361ed88SLokesh Vutla }; 72d361ed88SLokesh Vutla 73d361ed88SLokesh Vutla wkup_uart0: serial@42300000 { 74d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 75d361ed88SLokesh Vutla reg = <0x00 0x42300000 0x00 0x100>; 76d361ed88SLokesh Vutla interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 77d361ed88SLokesh Vutla clock-frequency = <48000000>; 78d361ed88SLokesh Vutla current-speed = <115200>; 79d361ed88SLokesh Vutla power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 80d361ed88SLokesh Vutla clocks = <&k3_clks 287 2>; 81d361ed88SLokesh Vutla clock-names = "fclk"; 82d361ed88SLokesh Vutla }; 83d361ed88SLokesh Vutla 84d361ed88SLokesh Vutla mcu_uart0: serial@40a00000 { 85d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 86d361ed88SLokesh Vutla reg = <0x00 0x40a00000 0x00 0x100>; 87d361ed88SLokesh Vutla interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 88d361ed88SLokesh Vutla clock-frequency = <96000000>; 89d361ed88SLokesh Vutla current-speed = <115200>; 90d361ed88SLokesh Vutla power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 91d361ed88SLokesh Vutla clocks = <&k3_clks 149 2>; 92d361ed88SLokesh Vutla clock-names = "fclk"; 93d361ed88SLokesh Vutla }; 94d361ed88SLokesh Vutla 95cab12badSNishanth Menon wkup_gpio_intr: interrupt-controller@42200000 { 96d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 97cab12badSNishanth Menon reg = <0x00 0x42200000 0x00 0x400>; 98d361ed88SLokesh Vutla ti,intr-trigger-type = <1>; 99d361ed88SLokesh Vutla interrupt-controller; 100d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 101d361ed88SLokesh Vutla #interrupt-cells = <1>; 102d361ed88SLokesh Vutla ti,sci = <&dmsc>; 103d361ed88SLokesh Vutla ti,sci-dev-id = <137>; 104d361ed88SLokesh Vutla ti,interrupt-ranges = <16 960 16>; 105d361ed88SLokesh Vutla }; 10646374264SPeter Ujfalusi 107e0b2e6afSFaiz Abbas wkup_gpio0: gpio@42110000 { 108e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 109e0b2e6afSFaiz Abbas reg = <0x00 0x42110000 0x00 0x100>; 110e0b2e6afSFaiz Abbas gpio-controller; 111e0b2e6afSFaiz Abbas #gpio-cells = <2>; 112e0b2e6afSFaiz Abbas interrupt-parent = <&wkup_gpio_intr>; 113e0b2e6afSFaiz Abbas interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 114e0b2e6afSFaiz Abbas interrupt-controller; 115e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 116e0b2e6afSFaiz Abbas ti,ngpio = <85>; 117e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 118e0b2e6afSFaiz Abbas power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 119e0b2e6afSFaiz Abbas clocks = <&k3_clks 113 0>; 120e0b2e6afSFaiz Abbas clock-names = "gpio"; 121e0b2e6afSFaiz Abbas }; 122e0b2e6afSFaiz Abbas 123e0b2e6afSFaiz Abbas wkup_gpio1: gpio@42100000 { 124e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 125e0b2e6afSFaiz Abbas reg = <0x00 0x42100000 0x00 0x100>; 126e0b2e6afSFaiz Abbas gpio-controller; 127e0b2e6afSFaiz Abbas #gpio-cells = <2>; 128e0b2e6afSFaiz Abbas interrupt-parent = <&wkup_gpio_intr>; 129e0b2e6afSFaiz Abbas interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 130e0b2e6afSFaiz Abbas interrupt-controller; 131e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 132e0b2e6afSFaiz Abbas ti,ngpio = <85>; 133e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 134e0b2e6afSFaiz Abbas power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 135e0b2e6afSFaiz Abbas clocks = <&k3_clks 114 0>; 136e0b2e6afSFaiz Abbas clock-names = "gpio"; 137e0b2e6afSFaiz Abbas }; 138e0b2e6afSFaiz Abbas 13946374264SPeter Ujfalusi mcu_navss: bus@28380000 { 14046374264SPeter Ujfalusi compatible = "simple-mfd"; 14146374264SPeter Ujfalusi #address-cells = <2>; 14246374264SPeter Ujfalusi #size-cells = <2>; 14346374264SPeter Ujfalusi ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 14446374264SPeter Ujfalusi dma-coherent; 14546374264SPeter Ujfalusi dma-ranges; 14646374264SPeter Ujfalusi ti,sci-dev-id = <232>; 14746374264SPeter Ujfalusi 14846374264SPeter Ujfalusi mcu_ringacc: ringacc@2b800000 { 14946374264SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 15046374264SPeter Ujfalusi reg = <0x00 0x2b800000 0x00 0x400000>, 15146374264SPeter Ujfalusi <0x00 0x2b000000 0x00 0x400000>, 15246374264SPeter Ujfalusi <0x00 0x28590000 0x00 0x100>, 15346374264SPeter Ujfalusi <0x00 0x2a500000 0x00 0x40000>; 15446374264SPeter Ujfalusi reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 15546374264SPeter Ujfalusi ti,num-rings = <286>; 15646374264SPeter Ujfalusi ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 15746374264SPeter Ujfalusi ti,sci = <&dmsc>; 15846374264SPeter Ujfalusi ti,sci-dev-id = <235>; 15946374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 16046374264SPeter Ujfalusi }; 16146374264SPeter Ujfalusi 16246374264SPeter Ujfalusi mcu_udmap: dma-controller@285c0000 { 16346374264SPeter Ujfalusi compatible = "ti,j721e-navss-mcu-udmap"; 16446374264SPeter Ujfalusi reg = <0x00 0x285c0000 0x00 0x100>, 16546374264SPeter Ujfalusi <0x00 0x2a800000 0x00 0x40000>, 16646374264SPeter Ujfalusi <0x00 0x2aa00000 0x00 0x40000>; 16746374264SPeter Ujfalusi reg-names = "gcfg", "rchanrt", "tchanrt"; 16846374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 16946374264SPeter Ujfalusi #dma-cells = <1>; 17046374264SPeter Ujfalusi 17146374264SPeter Ujfalusi ti,sci = <&dmsc>; 17246374264SPeter Ujfalusi ti,sci-dev-id = <236>; 17346374264SPeter Ujfalusi ti,ringacc = <&mcu_ringacc>; 17446374264SPeter Ujfalusi 17546374264SPeter Ujfalusi ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 17646374264SPeter Ujfalusi <0x0f>; /* TX_HCHAN */ 17746374264SPeter Ujfalusi ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 17846374264SPeter Ujfalusi <0x0b>; /* RX_HCHAN */ 17946374264SPeter Ujfalusi ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 18046374264SPeter Ujfalusi }; 18146374264SPeter Ujfalusi }; 182a323da4bSGrygorii Strashko 183a323da4bSGrygorii Strashko mcu_cpsw: ethernet@46000000 { 184a323da4bSGrygorii Strashko compatible = "ti,j721e-cpsw-nuss"; 185a323da4bSGrygorii Strashko #address-cells = <2>; 186a323da4bSGrygorii Strashko #size-cells = <2>; 187a323da4bSGrygorii Strashko reg = <0x00 0x46000000 0x00 0x200000>; 188a323da4bSGrygorii Strashko reg-names = "cpsw_nuss"; 189a323da4bSGrygorii Strashko ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 190a323da4bSGrygorii Strashko dma-coherent; 191a323da4bSGrygorii Strashko clocks = <&k3_clks 18 21>; 192a323da4bSGrygorii Strashko clock-names = "fck"; 193a323da4bSGrygorii Strashko power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 194a323da4bSGrygorii Strashko 195a323da4bSGrygorii Strashko dmas = <&mcu_udmap 0xf000>, 196a323da4bSGrygorii Strashko <&mcu_udmap 0xf001>, 197a323da4bSGrygorii Strashko <&mcu_udmap 0xf002>, 198a323da4bSGrygorii Strashko <&mcu_udmap 0xf003>, 199a323da4bSGrygorii Strashko <&mcu_udmap 0xf004>, 200a323da4bSGrygorii Strashko <&mcu_udmap 0xf005>, 201a323da4bSGrygorii Strashko <&mcu_udmap 0xf006>, 202a323da4bSGrygorii Strashko <&mcu_udmap 0xf007>, 203a323da4bSGrygorii Strashko <&mcu_udmap 0x7000>; 204a323da4bSGrygorii Strashko dma-names = "tx0", "tx1", "tx2", "tx3", 205a323da4bSGrygorii Strashko "tx4", "tx5", "tx6", "tx7", 206a323da4bSGrygorii Strashko "rx"; 207a323da4bSGrygorii Strashko 208a323da4bSGrygorii Strashko ethernet-ports { 209a323da4bSGrygorii Strashko #address-cells = <1>; 210a323da4bSGrygorii Strashko #size-cells = <0>; 211a323da4bSGrygorii Strashko 212a323da4bSGrygorii Strashko cpsw_port1: port@1 { 213a323da4bSGrygorii Strashko reg = <1>; 214a323da4bSGrygorii Strashko ti,mac-only; 215a323da4bSGrygorii Strashko label = "port1"; 216a323da4bSGrygorii Strashko ti,syscon-efuse = <&mcu_conf 0x200>; 217a323da4bSGrygorii Strashko phys = <&phy_gmii_sel 1>; 218a323da4bSGrygorii Strashko }; 219a323da4bSGrygorii Strashko }; 220a323da4bSGrygorii Strashko 221a323da4bSGrygorii Strashko davinci_mdio: mdio@f00 { 222a323da4bSGrygorii Strashko compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 223a323da4bSGrygorii Strashko reg = <0x00 0xf00 0x00 0x100>; 224a323da4bSGrygorii Strashko #address-cells = <1>; 225a323da4bSGrygorii Strashko #size-cells = <0>; 226a323da4bSGrygorii Strashko clocks = <&k3_clks 18 21>; 227a323da4bSGrygorii Strashko clock-names = "fck"; 228a323da4bSGrygorii Strashko bus_freq = <1000000>; 229a323da4bSGrygorii Strashko }; 230a323da4bSGrygorii Strashko 231a323da4bSGrygorii Strashko cpts@3d000 { 232a323da4bSGrygorii Strashko compatible = "ti,am65-cpts"; 233a323da4bSGrygorii Strashko reg = <0x00 0x3d000 0x00 0x400>; 234a323da4bSGrygorii Strashko clocks = <&k3_clks 18 2>; 235a323da4bSGrygorii Strashko clock-names = "cpts"; 236a323da4bSGrygorii Strashko interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 237a323da4bSGrygorii Strashko interrupt-names = "cpts"; 238a323da4bSGrygorii Strashko ti,cpts-ext-ts-inputs = <4>; 239a323da4bSGrygorii Strashko ti,cpts-periodic-outputs = <2>; 240a323da4bSGrygorii Strashko }; 241a323da4bSGrygorii Strashko }; 24203bfeb52SVignesh Raghavendra 24303bfeb52SVignesh Raghavendra mcu_i2c0: i2c@40b00000 { 24403bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 24503bfeb52SVignesh Raghavendra reg = <0x00 0x40b00000 0x00 0x100>; 24603bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 24703bfeb52SVignesh Raghavendra #address-cells = <1>; 24803bfeb52SVignesh Raghavendra #size-cells = <0>; 24903bfeb52SVignesh Raghavendra clock-names = "fck"; 25003bfeb52SVignesh Raghavendra clocks = <&k3_clks 194 1>; 25103bfeb52SVignesh Raghavendra power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 25203bfeb52SVignesh Raghavendra }; 25303bfeb52SVignesh Raghavendra 25403bfeb52SVignesh Raghavendra mcu_i2c1: i2c@40b10000 { 25503bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 25603bfeb52SVignesh Raghavendra reg = <0x00 0x40b10000 0x00 0x100>; 25703bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 25803bfeb52SVignesh Raghavendra #address-cells = <1>; 25903bfeb52SVignesh Raghavendra #size-cells = <0>; 26003bfeb52SVignesh Raghavendra clock-names = "fck"; 26103bfeb52SVignesh Raghavendra clocks = <&k3_clks 195 1>; 26203bfeb52SVignesh Raghavendra power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 26303bfeb52SVignesh Raghavendra }; 26403bfeb52SVignesh Raghavendra 26503bfeb52SVignesh Raghavendra wkup_i2c0: i2c@42120000 { 26603bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 26703bfeb52SVignesh Raghavendra reg = <0x00 0x42120000 0x00 0x100>; 26803bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 26903bfeb52SVignesh Raghavendra #address-cells = <1>; 27003bfeb52SVignesh Raghavendra #size-cells = <0>; 27103bfeb52SVignesh Raghavendra clock-names = "fck"; 27203bfeb52SVignesh Raghavendra clocks = <&k3_clks 197 1>; 27303bfeb52SVignesh Raghavendra power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 27403bfeb52SVignesh Raghavendra }; 2751b772656SVignesh Raghavendra 2761b772656SVignesh Raghavendra fss: syscon@47000000 { 2771b772656SVignesh Raghavendra compatible = "syscon", "simple-mfd"; 2781b772656SVignesh Raghavendra reg = <0x00 0x47000000 0x00 0x100>; 2791b772656SVignesh Raghavendra #address-cells = <2>; 2801b772656SVignesh Raghavendra #size-cells = <2>; 2811b772656SVignesh Raghavendra ranges; 2821b772656SVignesh Raghavendra 2831b772656SVignesh Raghavendra hbmc_mux: hbmc-mux { 2841b772656SVignesh Raghavendra compatible = "mmio-mux"; 2851b772656SVignesh Raghavendra #mux-control-cells = <1>; 2861b772656SVignesh Raghavendra mux-reg-masks = <0x4 0x2>; /* HBMC select */ 2871b772656SVignesh Raghavendra }; 2881b772656SVignesh Raghavendra 2891b772656SVignesh Raghavendra hbmc: hyperbus@47034000 { 2901b772656SVignesh Raghavendra compatible = "ti,am654-hbmc"; 2911b772656SVignesh Raghavendra reg = <0x00 0x47034000 0x00 0x100>, 2921b772656SVignesh Raghavendra <0x05 0x00000000 0x01 0x0000000>; 2931b772656SVignesh Raghavendra power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 2941b772656SVignesh Raghavendra clocks = <&k3_clks 102 0>; 2951b772656SVignesh Raghavendra assigned-clocks = <&k3_clks 102 5>; 2961b772656SVignesh Raghavendra assigned-clock-rates = <333333333>; 2971b772656SVignesh Raghavendra #address-cells = <2>; 2981b772656SVignesh Raghavendra #size-cells = <1>; 2991b772656SVignesh Raghavendra mux-controls = <&hbmc_mux 0>; 3001b772656SVignesh Raghavendra }; 301efbdf2e9SPratyush Yadav 302efbdf2e9SPratyush Yadav ospi0: spi@47040000 { 3030e941f49SPratyush Yadav compatible = "ti,am654-ospi", "cdns,qspi-nor"; 304efbdf2e9SPratyush Yadav reg = <0x0 0x47040000 0x0 0x100>, 305efbdf2e9SPratyush Yadav <0x5 0x00000000 0x1 0x0000000>; 306efbdf2e9SPratyush Yadav interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 307efbdf2e9SPratyush Yadav cdns,fifo-depth = <256>; 308efbdf2e9SPratyush Yadav cdns,fifo-width = <4>; 309efbdf2e9SPratyush Yadav cdns,trigger-address = <0x0>; 310efbdf2e9SPratyush Yadav clocks = <&k3_clks 103 0>; 311efbdf2e9SPratyush Yadav assigned-clocks = <&k3_clks 103 0>; 312efbdf2e9SPratyush Yadav assigned-clock-parents = <&k3_clks 103 2>; 313efbdf2e9SPratyush Yadav assigned-clock-rates = <166666666>; 314efbdf2e9SPratyush Yadav power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 315efbdf2e9SPratyush Yadav #address-cells = <1>; 316efbdf2e9SPratyush Yadav #size-cells = <0>; 317efbdf2e9SPratyush Yadav }; 3181b772656SVignesh Raghavendra }; 319e6b45168SVignesh Raghavendra 320e6b45168SVignesh Raghavendra tscadc0: tscadc@40200000 { 321e6b45168SVignesh Raghavendra compatible = "ti,am3359-tscadc"; 322e6b45168SVignesh Raghavendra reg = <0x00 0x40200000 0x00 0x1000>; 323e6b45168SVignesh Raghavendra interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 324e6b45168SVignesh Raghavendra power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 325e6b45168SVignesh Raghavendra clocks = <&k3_clks 0 1>; 326e6b45168SVignesh Raghavendra assigned-clocks = <&k3_clks 0 3>; 327e6b45168SVignesh Raghavendra assigned-clock-rates = <60000000>; 328e6b45168SVignesh Raghavendra clock-names = "adc_tsc_fck"; 329e6b45168SVignesh Raghavendra dmas = <&main_udmap 0x7400>, 330e6b45168SVignesh Raghavendra <&main_udmap 0x7401>; 331e6b45168SVignesh Raghavendra dma-names = "fifo0", "fifo1"; 332e6b45168SVignesh Raghavendra 333e6b45168SVignesh Raghavendra adc { 334e6b45168SVignesh Raghavendra #io-channel-cells = <1>; 335e6b45168SVignesh Raghavendra compatible = "ti,am3359-adc"; 336e6b45168SVignesh Raghavendra }; 337e6b45168SVignesh Raghavendra }; 338eb6f3655SSuman Anna 339eb6f3655SSuman Anna mcu_r5fss0: r5fss@41000000 { 340eb6f3655SSuman Anna compatible = "ti,j7200-r5fss"; 341eb6f3655SSuman Anna ti,cluster-mode = <1>; 342eb6f3655SSuman Anna #address-cells = <1>; 343eb6f3655SSuman Anna #size-cells = <1>; 344eb6f3655SSuman Anna ranges = <0x41000000 0x00 0x41000000 0x20000>, 345eb6f3655SSuman Anna <0x41400000 0x00 0x41400000 0x20000>; 346eb6f3655SSuman Anna power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 347eb6f3655SSuman Anna 348eb6f3655SSuman Anna mcu_r5fss0_core0: r5f@41000000 { 349eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 350eb6f3655SSuman Anna reg = <0x41000000 0x00010000>, 351eb6f3655SSuman Anna <0x41010000 0x00010000>; 352eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 353eb6f3655SSuman Anna ti,sci = <&dmsc>; 354eb6f3655SSuman Anna ti,sci-dev-id = <250>; 355eb6f3655SSuman Anna ti,sci-proc-ids = <0x01 0xff>; 356eb6f3655SSuman Anna resets = <&k3_reset 250 1>; 357eb6f3655SSuman Anna firmware-name = "j7200-mcu-r5f0_0-fw"; 358eb6f3655SSuman Anna ti,atcm-enable = <1>; 359eb6f3655SSuman Anna ti,btcm-enable = <1>; 360eb6f3655SSuman Anna ti,loczrama = <1>; 361eb6f3655SSuman Anna }; 362eb6f3655SSuman Anna 363eb6f3655SSuman Anna mcu_r5fss0_core1: r5f@41400000 { 364eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 365eb6f3655SSuman Anna reg = <0x41400000 0x00008000>, 366eb6f3655SSuman Anna <0x41410000 0x00008000>; 367eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 368eb6f3655SSuman Anna ti,sci = <&dmsc>; 369eb6f3655SSuman Anna ti,sci-dev-id = <251>; 370eb6f3655SSuman Anna ti,sci-proc-ids = <0x02 0xff>; 371eb6f3655SSuman Anna resets = <&k3_reset 251 1>; 372eb6f3655SSuman Anna firmware-name = "j7200-mcu-r5f0_1-fw"; 373eb6f3655SSuman Anna ti,atcm-enable = <1>; 374eb6f3655SSuman Anna ti,btcm-enable = <1>; 375eb6f3655SSuman Anna ti,loczrama = <1>; 376eb6f3655SSuman Anna }; 377eb6f3655SSuman Anna }; 378*d683a739SAndrew Davis 379*d683a739SAndrew Davis mcu_crypto: crypto@40900000 { 380*d683a739SAndrew Davis compatible = "ti,j721e-sa2ul"; 381*d683a739SAndrew Davis reg = <0x00 0x40900000 0x00 0x1200>; 382*d683a739SAndrew Davis power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 383*d683a739SAndrew Davis #address-cells = <2>; 384*d683a739SAndrew Davis #size-cells = <2>; 385*d683a739SAndrew Davis ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 386*d683a739SAndrew Davis dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 387*d683a739SAndrew Davis <&mcu_udmap 0x7503>; 388*d683a739SAndrew Davis dma-names = "tx", "rx1", "rx2"; 389*d683a739SAndrew Davis dma-coherent; 390*d683a739SAndrew Davis 391*d683a739SAndrew Davis rng: rng@40910000 { 392*d683a739SAndrew Davis compatible = "inside-secure,safexcel-eip76"; 393*d683a739SAndrew Davis reg = <0x00 0x40910000 0x00 0x7d>; 394*d683a739SAndrew Davis interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 395*d683a739SAndrew Davis status = "disabled"; /* Used by OP-TEE */ 396*d683a739SAndrew Davis }; 397*d683a739SAndrew Davis }; 398d361ed88SLokesh Vutla}; 399