1d361ed88SLokesh Vutla// SPDX-License-Identifier: GPL-2.0 2d361ed88SLokesh Vutla/* 3d361ed88SLokesh Vutla * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4d361ed88SLokesh Vutla * 5eb6f3655SSuman Anna * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6d361ed88SLokesh Vutla */ 7d361ed88SLokesh Vutla 8d361ed88SLokesh Vutla&cbass_mcu_wakeup { 99d3c9378SNishanth Menon dmsc: system-controller@44083000 { 10d361ed88SLokesh Vutla compatible = "ti,k2g-sci"; 11d361ed88SLokesh Vutla ti,host-id = <12>; 12d361ed88SLokesh Vutla 13d361ed88SLokesh Vutla mbox-names = "rx", "tx"; 14d361ed88SLokesh Vutla 15d361ed88SLokesh Vutla mboxes = <&secure_proxy_main 11>, 16d361ed88SLokesh Vutla <&secure_proxy_main 13>; 17d361ed88SLokesh Vutla 18d361ed88SLokesh Vutla reg-names = "debug_messages"; 19d361ed88SLokesh Vutla reg = <0x00 0x44083000 0x00 0x1000>; 20d361ed88SLokesh Vutla 21d361ed88SLokesh Vutla k3_pds: power-controller { 22d361ed88SLokesh Vutla compatible = "ti,sci-pm-domain"; 23d361ed88SLokesh Vutla #power-domain-cells = <2>; 24d361ed88SLokesh Vutla }; 25d361ed88SLokesh Vutla 26a0812885SNishanth Menon k3_clks: clock-controller { 27d361ed88SLokesh Vutla compatible = "ti,k2g-sci-clk"; 28d361ed88SLokesh Vutla #clock-cells = <2>; 29d361ed88SLokesh Vutla }; 30d361ed88SLokesh Vutla 31d361ed88SLokesh Vutla k3_reset: reset-controller { 32d361ed88SLokesh Vutla compatible = "ti,sci-reset"; 33d361ed88SLokesh Vutla #reset-cells = <2>; 34d361ed88SLokesh Vutla }; 35d361ed88SLokesh Vutla }; 36d361ed88SLokesh Vutla 37a323da4bSGrygorii Strashko mcu_conf: syscon@40f00000 { 38a323da4bSGrygorii Strashko compatible = "syscon", "simple-mfd"; 39a323da4bSGrygorii Strashko reg = <0x00 0x40f00000 0x00 0x20000>; 40a323da4bSGrygorii Strashko #address-cells = <1>; 41a323da4bSGrygorii Strashko #size-cells = <1>; 42a323da4bSGrygorii Strashko ranges = <0x00 0x00 0x40f00000 0x20000>; 43a323da4bSGrygorii Strashko 44a323da4bSGrygorii Strashko phy_gmii_sel: phy@4040 { 45a323da4bSGrygorii Strashko compatible = "ti,am654-phy-gmii-sel"; 46a323da4bSGrygorii Strashko reg = <0x4040 0x4>; 47a323da4bSGrygorii Strashko #phy-cells = <1>; 48a323da4bSGrygorii Strashko }; 49a323da4bSGrygorii Strashko }; 50a323da4bSGrygorii Strashko 51d361ed88SLokesh Vutla chipid@43000014 { 52d361ed88SLokesh Vutla compatible = "ti,am654-chipid"; 53d361ed88SLokesh Vutla reg = <0x00 0x43000014 0x00 0x4>; 54d361ed88SLokesh Vutla }; 55d361ed88SLokesh Vutla 56d361ed88SLokesh Vutla wkup_pmx0: pinctrl@4301c000 { 57d361ed88SLokesh Vutla compatible = "pinctrl-single"; 58d361ed88SLokesh Vutla /* Proxy 0 addressing */ 599ae21ac4SVaishnav Achath reg = <0x00 0x4301c000 0x00 0x34>; 609ae21ac4SVaishnav Achath #pinctrl-cells = <1>; 619ae21ac4SVaishnav Achath pinctrl-single,register-width = <32>; 629ae21ac4SVaishnav Achath pinctrl-single,function-mask = <0xffffffff>; 639ae21ac4SVaishnav Achath }; 649ae21ac4SVaishnav Achath 659ae21ac4SVaishnav Achath wkup_pmx1: pinctrl@0x4301c038 { 669ae21ac4SVaishnav Achath compatible = "pinctrl-single"; 679ae21ac4SVaishnav Achath /* Proxy 0 addressing */ 689ae21ac4SVaishnav Achath reg = <0x00 0x4301c038 0x00 0x8>; 699ae21ac4SVaishnav Achath #pinctrl-cells = <1>; 709ae21ac4SVaishnav Achath pinctrl-single,register-width = <32>; 719ae21ac4SVaishnav Achath pinctrl-single,function-mask = <0xffffffff>; 729ae21ac4SVaishnav Achath }; 739ae21ac4SVaishnav Achath 749ae21ac4SVaishnav Achath wkup_pmx2: pinctrl@0x4301c068 { 759ae21ac4SVaishnav Achath compatible = "pinctrl-single"; 769ae21ac4SVaishnav Achath /* Proxy 0 addressing */ 779ae21ac4SVaishnav Achath reg = <0x00 0x4301c068 0x00 0xec>; 789ae21ac4SVaishnav Achath #pinctrl-cells = <1>; 799ae21ac4SVaishnav Achath pinctrl-single,register-width = <32>; 809ae21ac4SVaishnav Achath pinctrl-single,function-mask = <0xffffffff>; 819ae21ac4SVaishnav Achath }; 829ae21ac4SVaishnav Achath 839ae21ac4SVaishnav Achath wkup_pmx3: pinctrl@0x4301c174 { 849ae21ac4SVaishnav Achath compatible = "pinctrl-single"; 859ae21ac4SVaishnav Achath /* Proxy 0 addressing */ 869ae21ac4SVaishnav Achath reg = <0x00 0x4301c174 0x00 0x20>; 87d361ed88SLokesh Vutla #pinctrl-cells = <1>; 88d361ed88SLokesh Vutla pinctrl-single,register-width = <32>; 89d361ed88SLokesh Vutla pinctrl-single,function-mask = <0xffffffff>; 90d361ed88SLokesh Vutla }; 91d361ed88SLokesh Vutla 92d361ed88SLokesh Vutla mcu_ram: sram@41c00000 { 93d361ed88SLokesh Vutla compatible = "mmio-sram"; 94d361ed88SLokesh Vutla reg = <0x00 0x41c00000 0x00 0x100000>; 95d361ed88SLokesh Vutla ranges = <0x00 0x00 0x41c00000 0x100000>; 96d361ed88SLokesh Vutla #address-cells = <1>; 97d361ed88SLokesh Vutla #size-cells = <1>; 98d361ed88SLokesh Vutla }; 99d361ed88SLokesh Vutla 100d361ed88SLokesh Vutla wkup_uart0: serial@42300000 { 101d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 102d361ed88SLokesh Vutla reg = <0x00 0x42300000 0x00 0x100>; 103d361ed88SLokesh Vutla interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 104d361ed88SLokesh Vutla clock-frequency = <48000000>; 105d361ed88SLokesh Vutla current-speed = <115200>; 106d361ed88SLokesh Vutla power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 107d361ed88SLokesh Vutla clocks = <&k3_clks 287 2>; 108d361ed88SLokesh Vutla clock-names = "fclk"; 109dae322f8SAndrew Davis status = "disabled"; 110d361ed88SLokesh Vutla }; 111d361ed88SLokesh Vutla 112d361ed88SLokesh Vutla mcu_uart0: serial@40a00000 { 113d361ed88SLokesh Vutla compatible = "ti,j721e-uart", "ti,am654-uart"; 114d361ed88SLokesh Vutla reg = <0x00 0x40a00000 0x00 0x100>; 115d361ed88SLokesh Vutla interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 116d361ed88SLokesh Vutla clock-frequency = <96000000>; 117d361ed88SLokesh Vutla current-speed = <115200>; 118d361ed88SLokesh Vutla power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 119d361ed88SLokesh Vutla clocks = <&k3_clks 149 2>; 120d361ed88SLokesh Vutla clock-names = "fclk"; 121dae322f8SAndrew Davis status = "disabled"; 122d361ed88SLokesh Vutla }; 123d361ed88SLokesh Vutla 124cab12badSNishanth Menon wkup_gpio_intr: interrupt-controller@42200000 { 125d361ed88SLokesh Vutla compatible = "ti,sci-intr"; 126cab12badSNishanth Menon reg = <0x00 0x42200000 0x00 0x400>; 127d361ed88SLokesh Vutla ti,intr-trigger-type = <1>; 128d361ed88SLokesh Vutla interrupt-controller; 129d361ed88SLokesh Vutla interrupt-parent = <&gic500>; 130d361ed88SLokesh Vutla #interrupt-cells = <1>; 131d361ed88SLokesh Vutla ti,sci = <&dmsc>; 132d361ed88SLokesh Vutla ti,sci-dev-id = <137>; 133d361ed88SLokesh Vutla ti,interrupt-ranges = <16 960 16>; 134d361ed88SLokesh Vutla }; 13546374264SPeter Ujfalusi 136e0b2e6afSFaiz Abbas wkup_gpio0: gpio@42110000 { 137e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 138e0b2e6afSFaiz Abbas reg = <0x00 0x42110000 0x00 0x100>; 139e0b2e6afSFaiz Abbas gpio-controller; 140e0b2e6afSFaiz Abbas #gpio-cells = <2>; 141e0b2e6afSFaiz Abbas interrupt-parent = <&wkup_gpio_intr>; 142e0b2e6afSFaiz Abbas interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 143e0b2e6afSFaiz Abbas interrupt-controller; 144e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 145e0b2e6afSFaiz Abbas ti,ngpio = <85>; 146e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 147e0b2e6afSFaiz Abbas power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 148e0b2e6afSFaiz Abbas clocks = <&k3_clks 113 0>; 149e0b2e6afSFaiz Abbas clock-names = "gpio"; 150e0b2e6afSFaiz Abbas }; 151e0b2e6afSFaiz Abbas 152e0b2e6afSFaiz Abbas wkup_gpio1: gpio@42100000 { 153e0b2e6afSFaiz Abbas compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 154e0b2e6afSFaiz Abbas reg = <0x00 0x42100000 0x00 0x100>; 155e0b2e6afSFaiz Abbas gpio-controller; 156e0b2e6afSFaiz Abbas #gpio-cells = <2>; 157e0b2e6afSFaiz Abbas interrupt-parent = <&wkup_gpio_intr>; 158e0b2e6afSFaiz Abbas interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 159e0b2e6afSFaiz Abbas interrupt-controller; 160e0b2e6afSFaiz Abbas #interrupt-cells = <2>; 161e0b2e6afSFaiz Abbas ti,ngpio = <85>; 162e0b2e6afSFaiz Abbas ti,davinci-gpio-unbanked = <0>; 163e0b2e6afSFaiz Abbas power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 164e0b2e6afSFaiz Abbas clocks = <&k3_clks 114 0>; 165e0b2e6afSFaiz Abbas clock-names = "gpio"; 166e0b2e6afSFaiz Abbas }; 167e0b2e6afSFaiz Abbas 16846374264SPeter Ujfalusi mcu_navss: bus@28380000 { 16946374264SPeter Ujfalusi compatible = "simple-mfd"; 17046374264SPeter Ujfalusi #address-cells = <2>; 17146374264SPeter Ujfalusi #size-cells = <2>; 17246374264SPeter Ujfalusi ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 17346374264SPeter Ujfalusi dma-coherent; 17446374264SPeter Ujfalusi dma-ranges; 17546374264SPeter Ujfalusi ti,sci-dev-id = <232>; 17646374264SPeter Ujfalusi 17746374264SPeter Ujfalusi mcu_ringacc: ringacc@2b800000 { 17846374264SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 17946374264SPeter Ujfalusi reg = <0x00 0x2b800000 0x00 0x400000>, 18046374264SPeter Ujfalusi <0x00 0x2b000000 0x00 0x400000>, 18146374264SPeter Ujfalusi <0x00 0x28590000 0x00 0x100>, 18246374264SPeter Ujfalusi <0x00 0x2a500000 0x00 0x40000>; 18346374264SPeter Ujfalusi reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 18446374264SPeter Ujfalusi ti,num-rings = <286>; 18546374264SPeter Ujfalusi ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 18646374264SPeter Ujfalusi ti,sci = <&dmsc>; 18746374264SPeter Ujfalusi ti,sci-dev-id = <235>; 18846374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 18946374264SPeter Ujfalusi }; 19046374264SPeter Ujfalusi 19146374264SPeter Ujfalusi mcu_udmap: dma-controller@285c0000 { 19246374264SPeter Ujfalusi compatible = "ti,j721e-navss-mcu-udmap"; 19346374264SPeter Ujfalusi reg = <0x00 0x285c0000 0x00 0x100>, 19446374264SPeter Ujfalusi <0x00 0x2a800000 0x00 0x40000>, 19546374264SPeter Ujfalusi <0x00 0x2aa00000 0x00 0x40000>; 19646374264SPeter Ujfalusi reg-names = "gcfg", "rchanrt", "tchanrt"; 19746374264SPeter Ujfalusi msi-parent = <&main_udmass_inta>; 19846374264SPeter Ujfalusi #dma-cells = <1>; 19946374264SPeter Ujfalusi 20046374264SPeter Ujfalusi ti,sci = <&dmsc>; 20146374264SPeter Ujfalusi ti,sci-dev-id = <236>; 20246374264SPeter Ujfalusi ti,ringacc = <&mcu_ringacc>; 20346374264SPeter Ujfalusi 20446374264SPeter Ujfalusi ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 20546374264SPeter Ujfalusi <0x0f>; /* TX_HCHAN */ 20646374264SPeter Ujfalusi ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 20746374264SPeter Ujfalusi <0x0b>; /* RX_HCHAN */ 20846374264SPeter Ujfalusi ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 20946374264SPeter Ujfalusi }; 21046374264SPeter Ujfalusi }; 211a323da4bSGrygorii Strashko 212*c4e43f5aSNishanth Menon secure_proxy_mcu: mailbox@2a480000 { 213*c4e43f5aSNishanth Menon compatible = "ti,am654-secure-proxy"; 214*c4e43f5aSNishanth Menon #mbox-cells = <1>; 215*c4e43f5aSNishanth Menon reg-names = "target_data", "rt", "scfg"; 216*c4e43f5aSNishanth Menon reg = <0x0 0x2a480000 0x0 0x80000>, 217*c4e43f5aSNishanth Menon <0x0 0x2a380000 0x0 0x80000>, 218*c4e43f5aSNishanth Menon <0x0 0x2a400000 0x0 0x80000>; 219*c4e43f5aSNishanth Menon /* 220*c4e43f5aSNishanth Menon * Marked Disabled: 221*c4e43f5aSNishanth Menon * Node is incomplete as it is meant for bootloaders and 222*c4e43f5aSNishanth Menon * firmware on non-MPU processors 223*c4e43f5aSNishanth Menon */ 224*c4e43f5aSNishanth Menon status = "disabled"; 225*c4e43f5aSNishanth Menon }; 226*c4e43f5aSNishanth Menon 227a323da4bSGrygorii Strashko mcu_cpsw: ethernet@46000000 { 228a323da4bSGrygorii Strashko compatible = "ti,j721e-cpsw-nuss"; 229a323da4bSGrygorii Strashko #address-cells = <2>; 230a323da4bSGrygorii Strashko #size-cells = <2>; 231a323da4bSGrygorii Strashko reg = <0x00 0x46000000 0x00 0x200000>; 232a323da4bSGrygorii Strashko reg-names = "cpsw_nuss"; 233a323da4bSGrygorii Strashko ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 234a323da4bSGrygorii Strashko dma-coherent; 235a323da4bSGrygorii Strashko clocks = <&k3_clks 18 21>; 236a323da4bSGrygorii Strashko clock-names = "fck"; 237a323da4bSGrygorii Strashko power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 238a323da4bSGrygorii Strashko 239a323da4bSGrygorii Strashko dmas = <&mcu_udmap 0xf000>, 240a323da4bSGrygorii Strashko <&mcu_udmap 0xf001>, 241a323da4bSGrygorii Strashko <&mcu_udmap 0xf002>, 242a323da4bSGrygorii Strashko <&mcu_udmap 0xf003>, 243a323da4bSGrygorii Strashko <&mcu_udmap 0xf004>, 244a323da4bSGrygorii Strashko <&mcu_udmap 0xf005>, 245a323da4bSGrygorii Strashko <&mcu_udmap 0xf006>, 246a323da4bSGrygorii Strashko <&mcu_udmap 0xf007>, 247a323da4bSGrygorii Strashko <&mcu_udmap 0x7000>; 248a323da4bSGrygorii Strashko dma-names = "tx0", "tx1", "tx2", "tx3", 249a323da4bSGrygorii Strashko "tx4", "tx5", "tx6", "tx7", 250a323da4bSGrygorii Strashko "rx"; 251a323da4bSGrygorii Strashko 252a323da4bSGrygorii Strashko ethernet-ports { 253a323da4bSGrygorii Strashko #address-cells = <1>; 254a323da4bSGrygorii Strashko #size-cells = <0>; 255a323da4bSGrygorii Strashko 256a323da4bSGrygorii Strashko cpsw_port1: port@1 { 257a323da4bSGrygorii Strashko reg = <1>; 258a323da4bSGrygorii Strashko ti,mac-only; 259a323da4bSGrygorii Strashko label = "port1"; 260a323da4bSGrygorii Strashko ti,syscon-efuse = <&mcu_conf 0x200>; 261a323da4bSGrygorii Strashko phys = <&phy_gmii_sel 1>; 262a323da4bSGrygorii Strashko }; 263a323da4bSGrygorii Strashko }; 264a323da4bSGrygorii Strashko 265a323da4bSGrygorii Strashko davinci_mdio: mdio@f00 { 266a323da4bSGrygorii Strashko compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 267a323da4bSGrygorii Strashko reg = <0x00 0xf00 0x00 0x100>; 268a323da4bSGrygorii Strashko #address-cells = <1>; 269a323da4bSGrygorii Strashko #size-cells = <0>; 270a323da4bSGrygorii Strashko clocks = <&k3_clks 18 21>; 271a323da4bSGrygorii Strashko clock-names = "fck"; 272a323da4bSGrygorii Strashko bus_freq = <1000000>; 273a323da4bSGrygorii Strashko }; 274a323da4bSGrygorii Strashko 275a323da4bSGrygorii Strashko cpts@3d000 { 276a323da4bSGrygorii Strashko compatible = "ti,am65-cpts"; 277a323da4bSGrygorii Strashko reg = <0x00 0x3d000 0x00 0x400>; 278a323da4bSGrygorii Strashko clocks = <&k3_clks 18 2>; 279a323da4bSGrygorii Strashko clock-names = "cpts"; 280a323da4bSGrygorii Strashko interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 281a323da4bSGrygorii Strashko interrupt-names = "cpts"; 282a323da4bSGrygorii Strashko ti,cpts-ext-ts-inputs = <4>; 283a323da4bSGrygorii Strashko ti,cpts-periodic-outputs = <2>; 284a323da4bSGrygorii Strashko }; 285a323da4bSGrygorii Strashko }; 28603bfeb52SVignesh Raghavendra 28703bfeb52SVignesh Raghavendra mcu_i2c0: i2c@40b00000 { 28803bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 28903bfeb52SVignesh Raghavendra reg = <0x00 0x40b00000 0x00 0x100>; 29003bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 29103bfeb52SVignesh Raghavendra #address-cells = <1>; 29203bfeb52SVignesh Raghavendra #size-cells = <0>; 29303bfeb52SVignesh Raghavendra clock-names = "fck"; 29403bfeb52SVignesh Raghavendra clocks = <&k3_clks 194 1>; 29503bfeb52SVignesh Raghavendra power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 296a9ed915cSAndrew Davis status = "disabled"; 29703bfeb52SVignesh Raghavendra }; 29803bfeb52SVignesh Raghavendra 29903bfeb52SVignesh Raghavendra mcu_i2c1: i2c@40b10000 { 30003bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 30103bfeb52SVignesh Raghavendra reg = <0x00 0x40b10000 0x00 0x100>; 30203bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 30303bfeb52SVignesh Raghavendra #address-cells = <1>; 30403bfeb52SVignesh Raghavendra #size-cells = <0>; 30503bfeb52SVignesh Raghavendra clock-names = "fck"; 30603bfeb52SVignesh Raghavendra clocks = <&k3_clks 195 1>; 30703bfeb52SVignesh Raghavendra power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 308a9ed915cSAndrew Davis status = "disabled"; 30903bfeb52SVignesh Raghavendra }; 31003bfeb52SVignesh Raghavendra 31103bfeb52SVignesh Raghavendra wkup_i2c0: i2c@42120000 { 31203bfeb52SVignesh Raghavendra compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 31303bfeb52SVignesh Raghavendra reg = <0x00 0x42120000 0x00 0x100>; 31403bfeb52SVignesh Raghavendra interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 31503bfeb52SVignesh Raghavendra #address-cells = <1>; 31603bfeb52SVignesh Raghavendra #size-cells = <0>; 31703bfeb52SVignesh Raghavendra clock-names = "fck"; 31803bfeb52SVignesh Raghavendra clocks = <&k3_clks 197 1>; 31903bfeb52SVignesh Raghavendra power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 320a9ed915cSAndrew Davis status = "disabled"; 32103bfeb52SVignesh Raghavendra }; 3221b772656SVignesh Raghavendra 3238f6c475fSVaishnav Achath mcu_spi0: spi@40300000 { 3248f6c475fSVaishnav Achath compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 3258f6c475fSVaishnav Achath reg = <0x00 0x040300000 0x00 0x400>; 3268f6c475fSVaishnav Achath interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 3278f6c475fSVaishnav Achath #address-cells = <1>; 3288f6c475fSVaishnav Achath #size-cells = <0>; 3298f6c475fSVaishnav Achath power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 3308f6c475fSVaishnav Achath clocks = <&k3_clks 274 0>; 3318f6c475fSVaishnav Achath status = "disabled"; 3328f6c475fSVaishnav Achath }; 3338f6c475fSVaishnav Achath 3348f6c475fSVaishnav Achath mcu_spi1: spi@40310000 { 3358f6c475fSVaishnav Achath compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 3368f6c475fSVaishnav Achath reg = <0x00 0x040310000 0x00 0x400>; 3378f6c475fSVaishnav Achath interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 3388f6c475fSVaishnav Achath #address-cells = <1>; 3398f6c475fSVaishnav Achath #size-cells = <0>; 3408f6c475fSVaishnav Achath power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 3418f6c475fSVaishnav Achath clocks = <&k3_clks 275 0>; 3428f6c475fSVaishnav Achath status = "disabled"; 3438f6c475fSVaishnav Achath }; 3448f6c475fSVaishnav Achath 3458f6c475fSVaishnav Achath mcu_spi2: spi@40320000 { 3468f6c475fSVaishnav Achath compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 3478f6c475fSVaishnav Achath reg = <0x00 0x040320000 0x00 0x400>; 3488f6c475fSVaishnav Achath interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 3498f6c475fSVaishnav Achath #address-cells = <1>; 3508f6c475fSVaishnav Achath #size-cells = <0>; 3518f6c475fSVaishnav Achath power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 3528f6c475fSVaishnav Achath clocks = <&k3_clks 276 0>; 3538f6c475fSVaishnav Achath status = "disabled"; 3548f6c475fSVaishnav Achath }; 3558f6c475fSVaishnav Achath 3561b772656SVignesh Raghavendra fss: syscon@47000000 { 3571b772656SVignesh Raghavendra compatible = "syscon", "simple-mfd"; 3581b772656SVignesh Raghavendra reg = <0x00 0x47000000 0x00 0x100>; 3591b772656SVignesh Raghavendra #address-cells = <2>; 3601b772656SVignesh Raghavendra #size-cells = <2>; 3611b772656SVignesh Raghavendra ranges; 3621b772656SVignesh Raghavendra 3631b772656SVignesh Raghavendra hbmc_mux: hbmc-mux { 3641b772656SVignesh Raghavendra compatible = "mmio-mux"; 3651b772656SVignesh Raghavendra #mux-control-cells = <1>; 3661b772656SVignesh Raghavendra mux-reg-masks = <0x4 0x2>; /* HBMC select */ 3671b772656SVignesh Raghavendra }; 3681b772656SVignesh Raghavendra 3691b772656SVignesh Raghavendra hbmc: hyperbus@47034000 { 3701b772656SVignesh Raghavendra compatible = "ti,am654-hbmc"; 3711b772656SVignesh Raghavendra reg = <0x00 0x47034000 0x00 0x100>, 3721b772656SVignesh Raghavendra <0x05 0x00000000 0x01 0x0000000>; 3731b772656SVignesh Raghavendra power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 3741b772656SVignesh Raghavendra clocks = <&k3_clks 102 0>; 3751b772656SVignesh Raghavendra assigned-clocks = <&k3_clks 102 5>; 3761b772656SVignesh Raghavendra assigned-clock-rates = <333333333>; 3771b772656SVignesh Raghavendra #address-cells = <2>; 3781b772656SVignesh Raghavendra #size-cells = <1>; 3791b772656SVignesh Raghavendra mux-controls = <&hbmc_mux 0>; 3801b772656SVignesh Raghavendra }; 381efbdf2e9SPratyush Yadav 382efbdf2e9SPratyush Yadav ospi0: spi@47040000 { 3830e941f49SPratyush Yadav compatible = "ti,am654-ospi", "cdns,qspi-nor"; 384efbdf2e9SPratyush Yadav reg = <0x0 0x47040000 0x0 0x100>, 385efbdf2e9SPratyush Yadav <0x5 0x00000000 0x1 0x0000000>; 386efbdf2e9SPratyush Yadav interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 387efbdf2e9SPratyush Yadav cdns,fifo-depth = <256>; 388efbdf2e9SPratyush Yadav cdns,fifo-width = <4>; 389efbdf2e9SPratyush Yadav cdns,trigger-address = <0x0>; 390efbdf2e9SPratyush Yadav clocks = <&k3_clks 103 0>; 391efbdf2e9SPratyush Yadav assigned-clocks = <&k3_clks 103 0>; 392efbdf2e9SPratyush Yadav assigned-clock-parents = <&k3_clks 103 2>; 393efbdf2e9SPratyush Yadav assigned-clock-rates = <166666666>; 394efbdf2e9SPratyush Yadav power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 395efbdf2e9SPratyush Yadav #address-cells = <1>; 396efbdf2e9SPratyush Yadav #size-cells = <0>; 397efbdf2e9SPratyush Yadav }; 3981b772656SVignesh Raghavendra }; 399e6b45168SVignesh Raghavendra 400e6b45168SVignesh Raghavendra tscadc0: tscadc@40200000 { 401e6b45168SVignesh Raghavendra compatible = "ti,am3359-tscadc"; 402e6b45168SVignesh Raghavendra reg = <0x00 0x40200000 0x00 0x1000>; 403e6b45168SVignesh Raghavendra interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 404e6b45168SVignesh Raghavendra power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 405e6b45168SVignesh Raghavendra clocks = <&k3_clks 0 1>; 406e6b45168SVignesh Raghavendra assigned-clocks = <&k3_clks 0 3>; 407e6b45168SVignesh Raghavendra assigned-clock-rates = <60000000>; 408e5bad300SMatt Ranostay clock-names = "fck"; 409e6b45168SVignesh Raghavendra dmas = <&main_udmap 0x7400>, 410e6b45168SVignesh Raghavendra <&main_udmap 0x7401>; 411e6b45168SVignesh Raghavendra dma-names = "fifo0", "fifo1"; 412e6b45168SVignesh Raghavendra 413e6b45168SVignesh Raghavendra adc { 414e6b45168SVignesh Raghavendra #io-channel-cells = <1>; 415e6b45168SVignesh Raghavendra compatible = "ti,am3359-adc"; 416e6b45168SVignesh Raghavendra }; 417e6b45168SVignesh Raghavendra }; 418eb6f3655SSuman Anna 419eb6f3655SSuman Anna mcu_r5fss0: r5fss@41000000 { 420eb6f3655SSuman Anna compatible = "ti,j7200-r5fss"; 421eb6f3655SSuman Anna ti,cluster-mode = <1>; 422eb6f3655SSuman Anna #address-cells = <1>; 423eb6f3655SSuman Anna #size-cells = <1>; 424eb6f3655SSuman Anna ranges = <0x41000000 0x00 0x41000000 0x20000>, 425eb6f3655SSuman Anna <0x41400000 0x00 0x41400000 0x20000>; 426eb6f3655SSuman Anna power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 427eb6f3655SSuman Anna 428eb6f3655SSuman Anna mcu_r5fss0_core0: r5f@41000000 { 429eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 430eb6f3655SSuman Anna reg = <0x41000000 0x00010000>, 431eb6f3655SSuman Anna <0x41010000 0x00010000>; 432eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 433eb6f3655SSuman Anna ti,sci = <&dmsc>; 434eb6f3655SSuman Anna ti,sci-dev-id = <250>; 435eb6f3655SSuman Anna ti,sci-proc-ids = <0x01 0xff>; 436eb6f3655SSuman Anna resets = <&k3_reset 250 1>; 437eb6f3655SSuman Anna firmware-name = "j7200-mcu-r5f0_0-fw"; 438eb6f3655SSuman Anna ti,atcm-enable = <1>; 439eb6f3655SSuman Anna ti,btcm-enable = <1>; 440eb6f3655SSuman Anna ti,loczrama = <1>; 441eb6f3655SSuman Anna }; 442eb6f3655SSuman Anna 443eb6f3655SSuman Anna mcu_r5fss0_core1: r5f@41400000 { 444eb6f3655SSuman Anna compatible = "ti,j7200-r5f"; 445eb6f3655SSuman Anna reg = <0x41400000 0x00008000>, 446eb6f3655SSuman Anna <0x41410000 0x00008000>; 447eb6f3655SSuman Anna reg-names = "atcm", "btcm"; 448eb6f3655SSuman Anna ti,sci = <&dmsc>; 449eb6f3655SSuman Anna ti,sci-dev-id = <251>; 450eb6f3655SSuman Anna ti,sci-proc-ids = <0x02 0xff>; 451eb6f3655SSuman Anna resets = <&k3_reset 251 1>; 452eb6f3655SSuman Anna firmware-name = "j7200-mcu-r5f0_1-fw"; 453eb6f3655SSuman Anna ti,atcm-enable = <1>; 454eb6f3655SSuman Anna ti,btcm-enable = <1>; 455eb6f3655SSuman Anna ti,loczrama = <1>; 456eb6f3655SSuman Anna }; 457eb6f3655SSuman Anna }; 458d683a739SAndrew Davis 459d683a739SAndrew Davis mcu_crypto: crypto@40900000 { 460d683a739SAndrew Davis compatible = "ti,j721e-sa2ul"; 461d683a739SAndrew Davis reg = <0x00 0x40900000 0x00 0x1200>; 462d683a739SAndrew Davis power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 463d683a739SAndrew Davis #address-cells = <2>; 464d683a739SAndrew Davis #size-cells = <2>; 465d683a739SAndrew Davis ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 466d683a739SAndrew Davis dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 467d683a739SAndrew Davis <&mcu_udmap 0x7503>; 468d683a739SAndrew Davis dma-names = "tx", "rx1", "rx2"; 469d683a739SAndrew Davis 470d683a739SAndrew Davis rng: rng@40910000 { 471d683a739SAndrew Davis compatible = "inside-secure,safexcel-eip76"; 472d683a739SAndrew Davis reg = <0x00 0x40910000 0x00 0x7d>; 473d683a739SAndrew Davis interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 474d683a739SAndrew Davis status = "disabled"; /* Used by OP-TEE */ 475d683a739SAndrew Davis }; 476d683a739SAndrew Davis }; 4774aa6586aSKeerthy 4784aa6586aSKeerthy wkup_vtm0: temperature-sensor@42040000 { 4794aa6586aSKeerthy compatible = "ti,j7200-vtm"; 4804aa6586aSKeerthy reg = <0x00 0x42040000 0x00 0x350>, 4814aa6586aSKeerthy <0x00 0x42050000 0x00 0x350>; 4824aa6586aSKeerthy power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 4834aa6586aSKeerthy #thermal-sensor-cells = <1>; 4844aa6586aSKeerthy }; 485d361ed88SLokesh Vutla}; 486