1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 cpsw0_phy_gmii_sel: phy@4044 { 43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 44 ti,qsgmii-main-ports = <1>; 45 reg = <0x4044 0x10>; 46 #phy-cells = <1>; 47 }; 48 49 usb_serdes_mux: mux-controller@4000 { 50 compatible = "mmio-mux"; 51 #mux-control-cells = <1>; 52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 53 }; 54 }; 55 56 gic500: interrupt-controller@1800000 { 57 compatible = "arm,gic-v3"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 #interrupt-cells = <3>; 62 interrupt-controller; 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 64 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 68 69 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 main_gpio_intr: interrupt-controller@a00000 { 82 compatible = "ti,sci-intr"; 83 reg = <0x00 0x00a00000 0x00 0x800>; 84 ti,intr-trigger-type = <1>; 85 interrupt-controller; 86 interrupt-parent = <&gic500>; 87 #interrupt-cells = <1>; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <131>; 90 ti,interrupt-ranges = <8 392 56>; 91 }; 92 93 main_navss: bus@30000000 { 94 compatible = "simple-mfd"; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 98 ti,sci-dev-id = <199>; 99 dma-coherent; 100 dma-ranges; 101 102 main_navss_intr: interrupt-controller@310e0000 { 103 compatible = "ti,sci-intr"; 104 reg = <0x00 0x310e0000 0x00 0x4000>; 105 ti,intr-trigger-type = <4>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 #interrupt-cells = <1>; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <213>; 111 ti,interrupt-ranges = <0 64 64>, 112 <64 448 64>, 113 <128 672 64>; 114 }; 115 116 main_udmass_inta: msi-controller@33d00000 { 117 compatible = "ti,sci-inta"; 118 reg = <0x00 0x33d00000 0x00 0x100000>; 119 interrupt-controller; 120 #interrupt-cells = <0>; 121 interrupt-parent = <&main_navss_intr>; 122 msi-controller; 123 ti,sci = <&dmsc>; 124 ti,sci-dev-id = <209>; 125 ti,interrupt-ranges = <0 0 256>; 126 }; 127 128 secure_proxy_main: mailbox@32c00000 { 129 compatible = "ti,am654-secure-proxy"; 130 #mbox-cells = <1>; 131 reg-names = "target_data", "rt", "scfg"; 132 reg = <0x00 0x32c00000 0x00 0x100000>, 133 <0x00 0x32400000 0x00 0x100000>, 134 <0x00 0x32800000 0x00 0x100000>; 135 interrupt-names = "rx_011"; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 hwspinlock: spinlock@30e00000 { 140 compatible = "ti,am654-hwspinlock"; 141 reg = <0x00 0x30e00000 0x00 0x1000>; 142 #hwlock-cells = <1>; 143 }; 144 145 mailbox0_cluster0: mailbox@31f80000 { 146 compatible = "ti,am654-mailbox"; 147 reg = <0x00 0x31f80000 0x00 0x200>; 148 #mbox-cells = <1>; 149 ti,mbox-num-users = <4>; 150 ti,mbox-num-fifos = <16>; 151 interrupt-parent = <&main_navss_intr>; 152 status = "disabled"; 153 }; 154 155 mailbox0_cluster1: mailbox@31f81000 { 156 compatible = "ti,am654-mailbox"; 157 reg = <0x00 0x31f81000 0x00 0x200>; 158 #mbox-cells = <1>; 159 ti,mbox-num-users = <4>; 160 ti,mbox-num-fifos = <16>; 161 interrupt-parent = <&main_navss_intr>; 162 status = "disabled"; 163 }; 164 165 mailbox0_cluster2: mailbox@31f82000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f82000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 status = "disabled"; 173 }; 174 175 mailbox0_cluster3: mailbox@31f83000 { 176 compatible = "ti,am654-mailbox"; 177 reg = <0x00 0x31f83000 0x00 0x200>; 178 #mbox-cells = <1>; 179 ti,mbox-num-users = <4>; 180 ti,mbox-num-fifos = <16>; 181 interrupt-parent = <&main_navss_intr>; 182 status = "disabled"; 183 }; 184 185 mailbox0_cluster4: mailbox@31f84000 { 186 compatible = "ti,am654-mailbox"; 187 reg = <0x00 0x31f84000 0x00 0x200>; 188 #mbox-cells = <1>; 189 ti,mbox-num-users = <4>; 190 ti,mbox-num-fifos = <16>; 191 interrupt-parent = <&main_navss_intr>; 192 status = "disabled"; 193 }; 194 195 mailbox0_cluster5: mailbox@31f85000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f85000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 status = "disabled"; 203 }; 204 205 mailbox0_cluster6: mailbox@31f86000 { 206 compatible = "ti,am654-mailbox"; 207 reg = <0x00 0x31f86000 0x00 0x200>; 208 #mbox-cells = <1>; 209 ti,mbox-num-users = <4>; 210 ti,mbox-num-fifos = <16>; 211 interrupt-parent = <&main_navss_intr>; 212 status = "disabled"; 213 }; 214 215 mailbox0_cluster7: mailbox@31f87000 { 216 compatible = "ti,am654-mailbox"; 217 reg = <0x00 0x31f87000 0x00 0x200>; 218 #mbox-cells = <1>; 219 ti,mbox-num-users = <4>; 220 ti,mbox-num-fifos = <16>; 221 interrupt-parent = <&main_navss_intr>; 222 status = "disabled"; 223 }; 224 225 mailbox0_cluster8: mailbox@31f88000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f88000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 status = "disabled"; 233 }; 234 235 mailbox0_cluster9: mailbox@31f89000 { 236 compatible = "ti,am654-mailbox"; 237 reg = <0x00 0x31f89000 0x00 0x200>; 238 #mbox-cells = <1>; 239 ti,mbox-num-users = <4>; 240 ti,mbox-num-fifos = <16>; 241 interrupt-parent = <&main_navss_intr>; 242 status = "disabled"; 243 }; 244 245 mailbox0_cluster10: mailbox@31f8a000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f8a000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster11: mailbox@31f8b000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f8b000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 main_ringacc: ringacc@3c000000 { 266 compatible = "ti,am654-navss-ringacc"; 267 reg = <0x00 0x3c000000 0x00 0x400000>, 268 <0x00 0x38000000 0x00 0x400000>, 269 <0x00 0x31120000 0x00 0x100>, 270 <0x00 0x33000000 0x00 0x40000>; 271 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 272 ti,num-rings = <1024>; 273 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 274 ti,sci = <&dmsc>; 275 ti,sci-dev-id = <211>; 276 msi-parent = <&main_udmass_inta>; 277 }; 278 279 main_udmap: dma-controller@31150000 { 280 compatible = "ti,j721e-navss-main-udmap"; 281 reg = <0x00 0x31150000 0x00 0x100>, 282 <0x00 0x34000000 0x00 0x100000>, 283 <0x00 0x35000000 0x00 0x100000>; 284 reg-names = "gcfg", "rchanrt", "tchanrt"; 285 msi-parent = <&main_udmass_inta>; 286 #dma-cells = <1>; 287 288 ti,sci = <&dmsc>; 289 ti,sci-dev-id = <212>; 290 ti,ringacc = <&main_ringacc>; 291 292 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 293 <0x0f>, /* TX_HCHAN */ 294 <0x10>; /* TX_UHCHAN */ 295 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 296 <0x0b>, /* RX_HCHAN */ 297 <0x0c>; /* RX_UHCHAN */ 298 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 299 }; 300 301 cpts@310d0000 { 302 compatible = "ti,j721e-cpts"; 303 reg = <0x00 0x310d0000 0x00 0x400>; 304 reg-names = "cpts"; 305 clocks = <&k3_clks 201 1>; 306 clock-names = "cpts"; 307 interrupts-extended = <&main_navss_intr 391>; 308 interrupt-names = "cpts"; 309 ti,cpts-periodic-outputs = <6>; 310 ti,cpts-ext-ts-inputs = <8>; 311 }; 312 }; 313 314 cpsw0: ethernet@c000000 { 315 compatible = "ti,j7200-cpswxg-nuss"; 316 #address-cells = <2>; 317 #size-cells = <2>; 318 reg = <0x00 0xc000000 0x00 0x200000>; 319 reg-names = "cpsw_nuss"; 320 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 321 clocks = <&k3_clks 19 33>; 322 clock-names = "fck"; 323 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 324 325 dmas = <&main_udmap 0xca00>, 326 <&main_udmap 0xca01>, 327 <&main_udmap 0xca02>, 328 <&main_udmap 0xca03>, 329 <&main_udmap 0xca04>, 330 <&main_udmap 0xca05>, 331 <&main_udmap 0xca06>, 332 <&main_udmap 0xca07>, 333 <&main_udmap 0x4a00>; 334 dma-names = "tx0", "tx1", "tx2", "tx3", 335 "tx4", "tx5", "tx6", "tx7", 336 "rx"; 337 338 status = "disabled"; 339 340 ethernet-ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 cpsw0_port1: port@1 { 344 reg = <1>; 345 ti,mac-only; 346 label = "port1"; 347 status = "disabled"; 348 }; 349 350 cpsw0_port2: port@2 { 351 reg = <2>; 352 ti,mac-only; 353 label = "port2"; 354 status = "disabled"; 355 }; 356 357 cpsw0_port3: port@3 { 358 reg = <3>; 359 ti,mac-only; 360 label = "port3"; 361 status = "disabled"; 362 }; 363 364 cpsw0_port4: port@4 { 365 reg = <4>; 366 ti,mac-only; 367 label = "port4"; 368 status = "disabled"; 369 }; 370 }; 371 372 cpsw5g_mdio: mdio@f00 { 373 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 374 reg = <0x00 0xf00 0x00 0x100>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clocks = <&k3_clks 19 33>; 378 clock-names = "fck"; 379 bus_freq = <1000000>; 380 status = "disabled"; 381 }; 382 383 cpts@3d000 { 384 compatible = "ti,j721e-cpts"; 385 reg = <0x00 0x3d000 0x00 0x400>; 386 clocks = <&k3_clks 19 16>; 387 clock-names = "cpts"; 388 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-names = "cpts"; 390 ti,cpts-ext-ts-inputs = <4>; 391 ti,cpts-periodic-outputs = <2>; 392 }; 393 }; 394 395 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 396 main_timerio_input: pinctrl@104200 { 397 compatible = "pinctrl-single"; 398 reg = <0x0 0x104200 0x0 0x50>; 399 #pinctrl-cells = <1>; 400 pinctrl-single,register-width = <32>; 401 pinctrl-single,function-mask = <0x000001ff>; 402 }; 403 404 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 405 main_timerio_output: pinctrl@104280 { 406 compatible = "pinctrl-single"; 407 reg = <0x0 0x104280 0x0 0x20>; 408 #pinctrl-cells = <1>; 409 pinctrl-single,register-width = <32>; 410 pinctrl-single,function-mask = <0x0000001f>; 411 }; 412 413 main_pmx0: pinctrl@11c000 { 414 compatible = "pinctrl-single"; 415 /* Proxy 0 addressing */ 416 reg = <0x00 0x11c000 0x00 0x10c>; 417 #pinctrl-cells = <1>; 418 pinctrl-single,register-width = <32>; 419 pinctrl-single,function-mask = <0xffffffff>; 420 }; 421 422 main_pmx1: pinctrl@11c11c { 423 compatible = "pinctrl-single"; 424 /* Proxy 0 addressing */ 425 reg = <0x00 0x11c11c 0x00 0xc>; 426 #pinctrl-cells = <1>; 427 pinctrl-single,register-width = <32>; 428 pinctrl-single,function-mask = <0xffffffff>; 429 }; 430 431 main_uart0: serial@2800000 { 432 compatible = "ti,j721e-uart", "ti,am654-uart"; 433 reg = <0x00 0x02800000 0x00 0x100>; 434 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 435 clock-frequency = <48000000>; 436 current-speed = <115200>; 437 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 438 clocks = <&k3_clks 146 2>; 439 clock-names = "fclk"; 440 status = "disabled"; 441 }; 442 443 main_uart1: serial@2810000 { 444 compatible = "ti,j721e-uart", "ti,am654-uart"; 445 reg = <0x00 0x02810000 0x00 0x100>; 446 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 447 clock-frequency = <48000000>; 448 current-speed = <115200>; 449 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 450 clocks = <&k3_clks 278 2>; 451 clock-names = "fclk"; 452 status = "disabled"; 453 }; 454 455 main_uart2: serial@2820000 { 456 compatible = "ti,j721e-uart", "ti,am654-uart"; 457 reg = <0x00 0x02820000 0x00 0x100>; 458 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 459 clock-frequency = <48000000>; 460 current-speed = <115200>; 461 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 462 clocks = <&k3_clks 279 2>; 463 clock-names = "fclk"; 464 status = "disabled"; 465 }; 466 467 main_uart3: serial@2830000 { 468 compatible = "ti,j721e-uart", "ti,am654-uart"; 469 reg = <0x00 0x02830000 0x00 0x100>; 470 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 471 clock-frequency = <48000000>; 472 current-speed = <115200>; 473 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 474 clocks = <&k3_clks 280 2>; 475 clock-names = "fclk"; 476 status = "disabled"; 477 }; 478 479 main_uart4: serial@2840000 { 480 compatible = "ti,j721e-uart", "ti,am654-uart"; 481 reg = <0x00 0x02840000 0x00 0x100>; 482 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 483 clock-frequency = <48000000>; 484 current-speed = <115200>; 485 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 486 clocks = <&k3_clks 281 2>; 487 clock-names = "fclk"; 488 status = "disabled"; 489 }; 490 491 main_uart5: serial@2850000 { 492 compatible = "ti,j721e-uart", "ti,am654-uart"; 493 reg = <0x00 0x02850000 0x00 0x100>; 494 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 495 clock-frequency = <48000000>; 496 current-speed = <115200>; 497 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 498 clocks = <&k3_clks 282 2>; 499 clock-names = "fclk"; 500 status = "disabled"; 501 }; 502 503 main_uart6: serial@2860000 { 504 compatible = "ti,j721e-uart", "ti,am654-uart"; 505 reg = <0x00 0x02860000 0x00 0x100>; 506 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 507 clock-frequency = <48000000>; 508 current-speed = <115200>; 509 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 510 clocks = <&k3_clks 283 2>; 511 clock-names = "fclk"; 512 status = "disabled"; 513 }; 514 515 main_uart7: serial@2870000 { 516 compatible = "ti,j721e-uart", "ti,am654-uart"; 517 reg = <0x00 0x02870000 0x00 0x100>; 518 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 519 clock-frequency = <48000000>; 520 current-speed = <115200>; 521 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 522 clocks = <&k3_clks 284 2>; 523 clock-names = "fclk"; 524 status = "disabled"; 525 }; 526 527 main_uart8: serial@2880000 { 528 compatible = "ti,j721e-uart", "ti,am654-uart"; 529 reg = <0x00 0x02880000 0x00 0x100>; 530 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 531 clock-frequency = <48000000>; 532 current-speed = <115200>; 533 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 534 clocks = <&k3_clks 285 2>; 535 clock-names = "fclk"; 536 status = "disabled"; 537 }; 538 539 main_uart9: serial@2890000 { 540 compatible = "ti,j721e-uart", "ti,am654-uart"; 541 reg = <0x00 0x02890000 0x00 0x100>; 542 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 543 clock-frequency = <48000000>; 544 current-speed = <115200>; 545 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 546 clocks = <&k3_clks 286 2>; 547 clock-names = "fclk"; 548 status = "disabled"; 549 }; 550 551 main_i2c0: i2c@2000000 { 552 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 553 reg = <0x00 0x2000000 0x00 0x100>; 554 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 clock-names = "fck"; 558 clocks = <&k3_clks 187 1>; 559 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 560 status = "disabled"; 561 }; 562 563 main_i2c1: i2c@2010000 { 564 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 565 reg = <0x00 0x2010000 0x00 0x100>; 566 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 clock-names = "fck"; 570 clocks = <&k3_clks 188 1>; 571 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 572 status = "disabled"; 573 }; 574 575 main_i2c2: i2c@2020000 { 576 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 577 reg = <0x00 0x2020000 0x00 0x100>; 578 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 clock-names = "fck"; 582 clocks = <&k3_clks 189 1>; 583 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 584 status = "disabled"; 585 }; 586 587 main_i2c3: i2c@2030000 { 588 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 589 reg = <0x00 0x2030000 0x00 0x100>; 590 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 clock-names = "fck"; 594 clocks = <&k3_clks 190 1>; 595 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 596 status = "disabled"; 597 }; 598 599 main_i2c4: i2c@2040000 { 600 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 601 reg = <0x00 0x2040000 0x00 0x100>; 602 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clock-names = "fck"; 606 clocks = <&k3_clks 191 1>; 607 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 608 status = "disabled"; 609 }; 610 611 main_i2c5: i2c@2050000 { 612 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 613 reg = <0x00 0x2050000 0x00 0x100>; 614 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 clock-names = "fck"; 618 clocks = <&k3_clks 192 1>; 619 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 620 status = "disabled"; 621 }; 622 623 main_i2c6: i2c@2060000 { 624 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 625 reg = <0x00 0x2060000 0x00 0x100>; 626 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 clock-names = "fck"; 630 clocks = <&k3_clks 193 1>; 631 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 632 status = "disabled"; 633 }; 634 635 main_sdhci0: mmc@4f80000 { 636 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 637 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 638 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 639 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 640 clock-names = "clk_ahb", "clk_xin"; 641 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 642 ti,otap-del-sel-legacy = <0x0>; 643 ti,otap-del-sel-mmc-hs = <0x0>; 644 ti,otap-del-sel-ddr52 = <0x6>; 645 ti,otap-del-sel-hs200 = <0x8>; 646 ti,otap-del-sel-hs400 = <0x5>; 647 ti,itap-del-sel-legacy = <0x10>; 648 ti,itap-del-sel-mmc-hs = <0xa>; 649 ti,strobe-sel = <0x77>; 650 ti,clkbuf-sel = <0x7>; 651 ti,trm-icp = <0x8>; 652 bus-width = <8>; 653 mmc-ddr-1_8v; 654 mmc-hs200-1_8v; 655 mmc-hs400-1_8v; 656 dma-coherent; 657 }; 658 659 main_sdhci1: mmc@4fb0000 { 660 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 661 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 662 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 663 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 664 clock-names = "clk_ahb", "clk_xin"; 665 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 666 ti,otap-del-sel-legacy = <0x0>; 667 ti,otap-del-sel-sd-hs = <0x0>; 668 ti,otap-del-sel-sdr12 = <0xf>; 669 ti,otap-del-sel-sdr25 = <0xf>; 670 ti,otap-del-sel-sdr50 = <0xc>; 671 ti,otap-del-sel-sdr104 = <0x5>; 672 ti,otap-del-sel-ddr50 = <0xc>; 673 ti,itap-del-sel-legacy = <0x0>; 674 ti,itap-del-sel-sd-hs = <0x0>; 675 ti,itap-del-sel-sdr12 = <0x0>; 676 ti,itap-del-sel-sdr25 = <0x0>; 677 ti,clkbuf-sel = <0x7>; 678 ti,trm-icp = <0x8>; 679 dma-coherent; 680 }; 681 682 serdes_wiz0: wiz@5060000 { 683 compatible = "ti,j721e-wiz-10g"; 684 #address-cells = <1>; 685 #size-cells = <1>; 686 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 687 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 688 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 689 num-lanes = <4>; 690 #reset-cells = <1>; 691 ranges = <0x5060000 0x0 0x5060000 0x10000>; 692 693 assigned-clocks = <&k3_clks 292 85>; 694 assigned-clock-parents = <&k3_clks 292 89>; 695 696 wiz0_pll0_refclk: pll0-refclk { 697 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 698 clock-output-names = "wiz0_pll0_refclk"; 699 #clock-cells = <0>; 700 assigned-clocks = <&wiz0_pll0_refclk>; 701 assigned-clock-parents = <&k3_clks 292 85>; 702 }; 703 704 wiz0_pll1_refclk: pll1-refclk { 705 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 706 clock-output-names = "wiz0_pll1_refclk"; 707 #clock-cells = <0>; 708 assigned-clocks = <&wiz0_pll1_refclk>; 709 assigned-clock-parents = <&k3_clks 292 85>; 710 }; 711 712 wiz0_refclk_dig: refclk-dig { 713 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 714 clock-output-names = "wiz0_refclk_dig"; 715 #clock-cells = <0>; 716 assigned-clocks = <&wiz0_refclk_dig>; 717 assigned-clock-parents = <&k3_clks 292 85>; 718 }; 719 720 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 721 clocks = <&wiz0_refclk_dig>; 722 #clock-cells = <0>; 723 }; 724 725 serdes0: serdes@5060000 { 726 compatible = "ti,j721e-serdes-10g"; 727 reg = <0x05060000 0x00010000>; 728 reg-names = "torrent_phy"; 729 resets = <&serdes_wiz0 0>; 730 reset-names = "torrent_reset"; 731 clocks = <&wiz0_pll0_refclk>; 732 clock-names = "refclk"; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 }; 736 }; 737 738 pcie1_rc: pcie@2910000 { 739 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 740 reg = <0x00 0x02910000 0x00 0x1000>, 741 <0x00 0x02917000 0x00 0x400>, 742 <0x00 0x0d800000 0x00 0x00800000>, 743 <0x00 0x18000000 0x00 0x00001000>; 744 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 745 interrupt-names = "link_state"; 746 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 747 device_type = "pci"; 748 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 749 max-link-speed = <3>; 750 num-lanes = <4>; 751 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 752 clocks = <&k3_clks 240 6>; 753 clock-names = "fck"; 754 #address-cells = <3>; 755 #size-cells = <2>; 756 bus-range = <0x0 0xff>; 757 cdns,no-bar-match-nbits = <64>; 758 vendor-id = <0x104c>; 759 device-id = <0xb00f>; 760 msi-map = <0x0 &gic_its 0x0 0x10000>; 761 dma-coherent; 762 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 763 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 764 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 765 }; 766 767 pcie1_ep: pcie-ep@2910000 { 768 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 769 reg = <0x00 0x02910000 0x00 0x1000>, 770 <0x00 0x02917000 0x00 0x400>, 771 <0x00 0x0d800000 0x00 0x00800000>, 772 <0x00 0x18000000 0x00 0x08000000>; 773 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 774 interrupt-names = "link_state"; 775 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 776 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 777 max-link-speed = <3>; 778 num-lanes = <4>; 779 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 780 clocks = <&k3_clks 240 6>; 781 clock-names = "fck"; 782 max-functions = /bits/ 8 <6>; 783 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 784 dma-coherent; 785 }; 786 787 usbss0: cdns-usb@4104000 { 788 compatible = "ti,j721e-usb"; 789 reg = <0x00 0x4104000 0x00 0x100>; 790 dma-coherent; 791 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 792 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 793 clock-names = "ref", "lpm"; 794 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 795 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 796 #address-cells = <2>; 797 #size-cells = <2>; 798 ranges; 799 800 usb0: usb@6000000 { 801 compatible = "cdns,usb3"; 802 reg = <0x00 0x6000000 0x00 0x10000>, 803 <0x00 0x6010000 0x00 0x10000>, 804 <0x00 0x6020000 0x00 0x10000>; 805 reg-names = "otg", "xhci", "dev"; 806 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 807 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 808 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 809 interrupt-names = "host", 810 "peripheral", 811 "otg"; 812 maximum-speed = "super-speed"; 813 dr_mode = "otg"; 814 cdns,phyrst-a-enable; 815 }; 816 }; 817 818 main_gpio0: gpio@600000 { 819 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 820 reg = <0x00 0x00600000 0x00 0x100>; 821 gpio-controller; 822 #gpio-cells = <2>; 823 interrupt-parent = <&main_gpio_intr>; 824 interrupts = <145>, <146>, <147>, <148>, 825 <149>; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 ti,ngpio = <69>; 829 ti,davinci-gpio-unbanked = <0>; 830 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&k3_clks 105 0>; 832 clock-names = "gpio"; 833 }; 834 835 main_gpio2: gpio@610000 { 836 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 837 reg = <0x00 0x00610000 0x00 0x100>; 838 gpio-controller; 839 #gpio-cells = <2>; 840 interrupt-parent = <&main_gpio_intr>; 841 interrupts = <154>, <155>, <156>, <157>, 842 <158>; 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 ti,ngpio = <69>; 846 ti,davinci-gpio-unbanked = <0>; 847 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 848 clocks = <&k3_clks 107 0>; 849 clock-names = "gpio"; 850 }; 851 852 main_gpio4: gpio@620000 { 853 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 854 reg = <0x00 0x00620000 0x00 0x100>; 855 gpio-controller; 856 #gpio-cells = <2>; 857 interrupt-parent = <&main_gpio_intr>; 858 interrupts = <163>, <164>, <165>, <166>, 859 <167>; 860 interrupt-controller; 861 #interrupt-cells = <2>; 862 ti,ngpio = <69>; 863 ti,davinci-gpio-unbanked = <0>; 864 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 865 clocks = <&k3_clks 109 0>; 866 clock-names = "gpio"; 867 }; 868 869 main_gpio6: gpio@630000 { 870 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 871 reg = <0x00 0x00630000 0x00 0x100>; 872 gpio-controller; 873 #gpio-cells = <2>; 874 interrupt-parent = <&main_gpio_intr>; 875 interrupts = <172>, <173>, <174>, <175>, 876 <176>; 877 interrupt-controller; 878 #interrupt-cells = <2>; 879 ti,ngpio = <69>; 880 ti,davinci-gpio-unbanked = <0>; 881 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 882 clocks = <&k3_clks 111 0>; 883 clock-names = "gpio"; 884 }; 885 886 main_spi0: spi@2100000 { 887 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 888 reg = <0x00 0x02100000 0x00 0x400>; 889 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 893 clocks = <&k3_clks 266 1>; 894 status = "disabled"; 895 }; 896 897 main_spi1: spi@2110000 { 898 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 899 reg = <0x00 0x02110000 0x00 0x400>; 900 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 904 clocks = <&k3_clks 267 1>; 905 status = "disabled"; 906 }; 907 908 main_spi2: spi@2120000 { 909 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 910 reg = <0x00 0x02120000 0x00 0x400>; 911 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 915 clocks = <&k3_clks 268 1>; 916 status = "disabled"; 917 }; 918 919 main_spi3: spi@2130000 { 920 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 921 reg = <0x00 0x02130000 0x00 0x400>; 922 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 926 clocks = <&k3_clks 269 1>; 927 status = "disabled"; 928 }; 929 930 main_spi4: spi@2140000 { 931 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 932 reg = <0x00 0x02140000 0x00 0x400>; 933 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 937 clocks = <&k3_clks 270 1>; 938 status = "disabled"; 939 }; 940 941 main_spi5: spi@2150000 { 942 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 943 reg = <0x00 0x02150000 0x00 0x400>; 944 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 948 clocks = <&k3_clks 271 1>; 949 status = "disabled"; 950 }; 951 952 main_spi6: spi@2160000 { 953 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 954 reg = <0x00 0x02160000 0x00 0x400>; 955 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 959 clocks = <&k3_clks 272 1>; 960 status = "disabled"; 961 }; 962 963 main_spi7: spi@2170000 { 964 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 965 reg = <0x00 0x02170000 0x00 0x400>; 966 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 970 clocks = <&k3_clks 273 1>; 971 status = "disabled"; 972 }; 973 974 watchdog0: watchdog@2200000 { 975 compatible = "ti,j7-rti-wdt"; 976 reg = <0x0 0x2200000 0x0 0x100>; 977 clocks = <&k3_clks 252 1>; 978 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 979 assigned-clocks = <&k3_clks 252 1>; 980 assigned-clock-parents = <&k3_clks 252 5>; 981 }; 982 983 watchdog1: watchdog@2210000 { 984 compatible = "ti,j7-rti-wdt"; 985 reg = <0x0 0x2210000 0x0 0x100>; 986 clocks = <&k3_clks 253 1>; 987 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 988 assigned-clocks = <&k3_clks 253 1>; 989 assigned-clock-parents = <&k3_clks 253 5>; 990 }; 991 992 main_timer0: timer@2400000 { 993 compatible = "ti,am654-timer"; 994 reg = <0x00 0x2400000 0x00 0x400>; 995 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&k3_clks 49 1>; 997 clock-names = "fck"; 998 assigned-clocks = <&k3_clks 49 1>; 999 assigned-clock-parents = <&k3_clks 49 2>; 1000 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1001 ti,timer-pwm; 1002 }; 1003 1004 main_timer1: timer@2410000 { 1005 compatible = "ti,am654-timer"; 1006 reg = <0x00 0x2410000 0x00 0x400>; 1007 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&k3_clks 50 1>; 1009 clock-names = "fck"; 1010 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; 1011 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; 1012 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1013 ti,timer-pwm; 1014 }; 1015 1016 main_timer2: timer@2420000 { 1017 compatible = "ti,am654-timer"; 1018 reg = <0x00 0x2420000 0x00 0x400>; 1019 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&k3_clks 51 1>; 1021 clock-names = "fck"; 1022 assigned-clocks = <&k3_clks 51 1>; 1023 assigned-clock-parents = <&k3_clks 51 2>; 1024 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1025 ti,timer-pwm; 1026 }; 1027 1028 main_timer3: timer@2430000 { 1029 compatible = "ti,am654-timer"; 1030 reg = <0x00 0x2430000 0x00 0x400>; 1031 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&k3_clks 52 1>; 1033 clock-names = "fck"; 1034 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; 1035 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; 1036 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1037 ti,timer-pwm; 1038 }; 1039 1040 main_timer4: timer@2440000 { 1041 compatible = "ti,am654-timer"; 1042 reg = <0x00 0x2440000 0x00 0x400>; 1043 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&k3_clks 53 1>; 1045 clock-names = "fck"; 1046 assigned-clocks = <&k3_clks 53 1>; 1047 assigned-clock-parents = <&k3_clks 53 2>; 1048 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1049 ti,timer-pwm; 1050 }; 1051 1052 main_timer5: timer@2450000 { 1053 compatible = "ti,am654-timer"; 1054 reg = <0x00 0x2450000 0x00 0x400>; 1055 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&k3_clks 54 1>; 1057 clock-names = "fck"; 1058 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; 1059 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; 1060 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1061 ti,timer-pwm; 1062 }; 1063 1064 main_timer6: timer@2460000 { 1065 compatible = "ti,am654-timer"; 1066 reg = <0x00 0x2460000 0x00 0x400>; 1067 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&k3_clks 55 1>; 1069 clock-names = "fck"; 1070 assigned-clocks = <&k3_clks 55 1>; 1071 assigned-clock-parents = <&k3_clks 55 2>; 1072 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1073 ti,timer-pwm; 1074 }; 1075 1076 main_timer7: timer@2470000 { 1077 compatible = "ti,am654-timer"; 1078 reg = <0x00 0x2470000 0x00 0x400>; 1079 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&k3_clks 57 1>; 1081 clock-names = "fck"; 1082 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; 1083 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; 1084 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1085 ti,timer-pwm; 1086 }; 1087 1088 main_timer8: timer@2480000 { 1089 compatible = "ti,am654-timer"; 1090 reg = <0x00 0x2480000 0x00 0x400>; 1091 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&k3_clks 58 1>; 1093 clock-names = "fck"; 1094 assigned-clocks = <&k3_clks 58 1>; 1095 assigned-clock-parents = <&k3_clks 58 2>; 1096 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1097 ti,timer-pwm; 1098 }; 1099 1100 main_timer9: timer@2490000 { 1101 compatible = "ti,am654-timer"; 1102 reg = <0x00 0x2490000 0x00 0x400>; 1103 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&k3_clks 59 1>; 1105 clock-names = "fck"; 1106 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; 1107 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; 1108 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1109 ti,timer-pwm; 1110 }; 1111 1112 main_timer10: timer@24a0000 { 1113 compatible = "ti,am654-timer"; 1114 reg = <0x00 0x24a0000 0x00 0x400>; 1115 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&k3_clks 60 1>; 1117 clock-names = "fck"; 1118 assigned-clocks = <&k3_clks 60 1>; 1119 assigned-clock-parents = <&k3_clks 60 2>; 1120 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1121 ti,timer-pwm; 1122 }; 1123 1124 main_timer11: timer@24b0000 { 1125 compatible = "ti,am654-timer"; 1126 reg = <0x00 0x24b0000 0x00 0x400>; 1127 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&k3_clks 62 1>; 1129 clock-names = "fck"; 1130 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; 1131 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; 1132 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1133 ti,timer-pwm; 1134 }; 1135 1136 main_timer12: timer@24c0000 { 1137 compatible = "ti,am654-timer"; 1138 reg = <0x00 0x24c0000 0x00 0x400>; 1139 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&k3_clks 63 1>; 1141 clock-names = "fck"; 1142 assigned-clocks = <&k3_clks 63 1>; 1143 assigned-clock-parents = <&k3_clks 63 2>; 1144 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1145 ti,timer-pwm; 1146 }; 1147 1148 main_timer13: timer@24d0000 { 1149 compatible = "ti,am654-timer"; 1150 reg = <0x00 0x24d0000 0x00 0x400>; 1151 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&k3_clks 64 1>; 1153 clock-names = "fck"; 1154 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; 1155 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; 1156 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1157 ti,timer-pwm; 1158 }; 1159 1160 main_timer14: timer@24e0000 { 1161 compatible = "ti,am654-timer"; 1162 reg = <0x00 0x24e0000 0x00 0x400>; 1163 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&k3_clks 65 1>; 1165 clock-names = "fck"; 1166 assigned-clocks = <&k3_clks 65 1>; 1167 assigned-clock-parents = <&k3_clks 65 2>; 1168 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1169 ti,timer-pwm; 1170 }; 1171 1172 main_timer15: timer@24f0000 { 1173 compatible = "ti,am654-timer"; 1174 reg = <0x00 0x24f0000 0x00 0x400>; 1175 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&k3_clks 66 1>; 1177 clock-names = "fck"; 1178 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; 1179 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; 1180 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1181 ti,timer-pwm; 1182 }; 1183 1184 main_timer16: timer@2500000 { 1185 compatible = "ti,am654-timer"; 1186 reg = <0x00 0x2500000 0x00 0x400>; 1187 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&k3_clks 67 1>; 1189 clock-names = "fck"; 1190 assigned-clocks = <&k3_clks 67 1>; 1191 assigned-clock-parents = <&k3_clks 67 2>; 1192 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1193 ti,timer-pwm; 1194 }; 1195 1196 main_timer17: timer@2510000 { 1197 compatible = "ti,am654-timer"; 1198 reg = <0x00 0x2510000 0x00 0x400>; 1199 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&k3_clks 68 1>; 1201 clock-names = "fck"; 1202 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; 1203 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; 1204 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1205 ti,timer-pwm; 1206 }; 1207 1208 main_timer18: timer@2520000 { 1209 compatible = "ti,am654-timer"; 1210 reg = <0x00 0x2520000 0x00 0x400>; 1211 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&k3_clks 69 1>; 1213 clock-names = "fck"; 1214 assigned-clocks = <&k3_clks 69 1>; 1215 assigned-clock-parents = <&k3_clks 69 2>; 1216 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1217 ti,timer-pwm; 1218 }; 1219 1220 main_timer19: timer@2530000 { 1221 compatible = "ti,am654-timer"; 1222 reg = <0x00 0x2530000 0x00 0x400>; 1223 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&k3_clks 70 1>; 1225 clock-names = "fck"; 1226 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; 1227 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; 1228 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1229 ti,timer-pwm; 1230 }; 1231 1232 main_r5fss0: r5fss@5c00000 { 1233 compatible = "ti,j7200-r5fss"; 1234 ti,cluster-mode = <1>; 1235 #address-cells = <1>; 1236 #size-cells = <1>; 1237 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1238 <0x5d00000 0x00 0x5d00000 0x20000>; 1239 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1240 1241 main_r5fss0_core0: r5f@5c00000 { 1242 compatible = "ti,j7200-r5f"; 1243 reg = <0x5c00000 0x00010000>, 1244 <0x5c10000 0x00010000>; 1245 reg-names = "atcm", "btcm"; 1246 ti,sci = <&dmsc>; 1247 ti,sci-dev-id = <245>; 1248 ti,sci-proc-ids = <0x06 0xff>; 1249 resets = <&k3_reset 245 1>; 1250 firmware-name = "j7200-main-r5f0_0-fw"; 1251 ti,atcm-enable = <1>; 1252 ti,btcm-enable = <1>; 1253 ti,loczrama = <1>; 1254 }; 1255 1256 main_r5fss0_core1: r5f@5d00000 { 1257 compatible = "ti,j7200-r5f"; 1258 reg = <0x5d00000 0x00008000>, 1259 <0x5d10000 0x00008000>; 1260 reg-names = "atcm", "btcm"; 1261 ti,sci = <&dmsc>; 1262 ti,sci-dev-id = <246>; 1263 ti,sci-proc-ids = <0x07 0xff>; 1264 resets = <&k3_reset 246 1>; 1265 firmware-name = "j7200-main-r5f0_1-fw"; 1266 ti,atcm-enable = <1>; 1267 ti,btcm-enable = <1>; 1268 ti,loczrama = <1>; 1269 }; 1270 }; 1271 1272 main_esm: esm@700000 { 1273 compatible = "ti,j721e-esm"; 1274 reg = <0x0 0x700000 0x0 0x1000>; 1275 ti,esm-pins = <656>, <657>; 1276 }; 1277}; 1278