1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 58 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 59 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 60 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 61 62 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 63 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 64 65 gic_its: msi-controller@1820000 { 66 compatible = "arm,gic-v3-its"; 67 reg = <0x00 0x01820000 0x00 0x10000>; 68 socionext,synquacer-pre-its = <0x1000000 0x400000>; 69 msi-controller; 70 #msi-cells = <1>; 71 }; 72 }; 73 74 main_gpio_intr: interrupt-controller@a00000 { 75 compatible = "ti,sci-intr"; 76 reg = <0x00 0x00a00000 0x00 0x800>; 77 ti,intr-trigger-type = <1>; 78 interrupt-controller; 79 interrupt-parent = <&gic500>; 80 #interrupt-cells = <1>; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <131>; 83 ti,interrupt-ranges = <8 392 56>; 84 }; 85 86 main_navss: bus@30000000 { 87 compatible = "simple-mfd"; 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 91 ti,sci-dev-id = <199>; 92 dma-coherent; 93 dma-ranges; 94 95 main_navss_intr: interrupt-controller@310e0000 { 96 compatible = "ti,sci-intr"; 97 reg = <0x00 0x310e0000 0x00 0x4000>; 98 ti,intr-trigger-type = <4>; 99 interrupt-controller; 100 interrupt-parent = <&gic500>; 101 #interrupt-cells = <1>; 102 ti,sci = <&dmsc>; 103 ti,sci-dev-id = <213>; 104 ti,interrupt-ranges = <0 64 64>, 105 <64 448 64>, 106 <128 672 64>; 107 }; 108 109 main_udmass_inta: msi-controller@33d00000 { 110 compatible = "ti,sci-inta"; 111 reg = <0x00 0x33d00000 0x00 0x100000>; 112 interrupt-controller; 113 #interrupt-cells = <0>; 114 interrupt-parent = <&main_navss_intr>; 115 msi-controller; 116 ti,sci = <&dmsc>; 117 ti,sci-dev-id = <209>; 118 ti,interrupt-ranges = <0 0 256>; 119 }; 120 121 secure_proxy_main: mailbox@32c00000 { 122 compatible = "ti,am654-secure-proxy"; 123 #mbox-cells = <1>; 124 reg-names = "target_data", "rt", "scfg"; 125 reg = <0x00 0x32c00000 0x00 0x100000>, 126 <0x00 0x32400000 0x00 0x100000>, 127 <0x00 0x32800000 0x00 0x100000>; 128 interrupt-names = "rx_011"; 129 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 hwspinlock: spinlock@30e00000 { 133 compatible = "ti,am654-hwspinlock"; 134 reg = <0x00 0x30e00000 0x00 0x1000>; 135 #hwlock-cells = <1>; 136 }; 137 138 mailbox0_cluster0: mailbox@31f80000 { 139 compatible = "ti,am654-mailbox"; 140 reg = <0x00 0x31f80000 0x00 0x200>; 141 #mbox-cells = <1>; 142 ti,mbox-num-users = <4>; 143 ti,mbox-num-fifos = <16>; 144 interrupt-parent = <&main_navss_intr>; 145 }; 146 147 mailbox0_cluster1: mailbox@31f81000 { 148 compatible = "ti,am654-mailbox"; 149 reg = <0x00 0x31f81000 0x00 0x200>; 150 #mbox-cells = <1>; 151 ti,mbox-num-users = <4>; 152 ti,mbox-num-fifos = <16>; 153 interrupt-parent = <&main_navss_intr>; 154 }; 155 156 mailbox0_cluster2: mailbox@31f82000 { 157 compatible = "ti,am654-mailbox"; 158 reg = <0x00 0x31f82000 0x00 0x200>; 159 #mbox-cells = <1>; 160 ti,mbox-num-users = <4>; 161 ti,mbox-num-fifos = <16>; 162 interrupt-parent = <&main_navss_intr>; 163 }; 164 165 mailbox0_cluster3: mailbox@31f83000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f83000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 }; 173 174 mailbox0_cluster4: mailbox@31f84000 { 175 compatible = "ti,am654-mailbox"; 176 reg = <0x00 0x31f84000 0x00 0x200>; 177 #mbox-cells = <1>; 178 ti,mbox-num-users = <4>; 179 ti,mbox-num-fifos = <16>; 180 interrupt-parent = <&main_navss_intr>; 181 }; 182 183 mailbox0_cluster5: mailbox@31f85000 { 184 compatible = "ti,am654-mailbox"; 185 reg = <0x00 0x31f85000 0x00 0x200>; 186 #mbox-cells = <1>; 187 ti,mbox-num-users = <4>; 188 ti,mbox-num-fifos = <16>; 189 interrupt-parent = <&main_navss_intr>; 190 }; 191 192 mailbox0_cluster6: mailbox@31f86000 { 193 compatible = "ti,am654-mailbox"; 194 reg = <0x00 0x31f86000 0x00 0x200>; 195 #mbox-cells = <1>; 196 ti,mbox-num-users = <4>; 197 ti,mbox-num-fifos = <16>; 198 interrupt-parent = <&main_navss_intr>; 199 }; 200 201 mailbox0_cluster7: mailbox@31f87000 { 202 compatible = "ti,am654-mailbox"; 203 reg = <0x00 0x31f87000 0x00 0x200>; 204 #mbox-cells = <1>; 205 ti,mbox-num-users = <4>; 206 ti,mbox-num-fifos = <16>; 207 interrupt-parent = <&main_navss_intr>; 208 }; 209 210 mailbox0_cluster8: mailbox@31f88000 { 211 compatible = "ti,am654-mailbox"; 212 reg = <0x00 0x31f88000 0x00 0x200>; 213 #mbox-cells = <1>; 214 ti,mbox-num-users = <4>; 215 ti,mbox-num-fifos = <16>; 216 interrupt-parent = <&main_navss_intr>; 217 }; 218 219 mailbox0_cluster9: mailbox@31f89000 { 220 compatible = "ti,am654-mailbox"; 221 reg = <0x00 0x31f89000 0x00 0x200>; 222 #mbox-cells = <1>; 223 ti,mbox-num-users = <4>; 224 ti,mbox-num-fifos = <16>; 225 interrupt-parent = <&main_navss_intr>; 226 }; 227 228 mailbox0_cluster10: mailbox@31f8a000 { 229 compatible = "ti,am654-mailbox"; 230 reg = <0x00 0x31f8a000 0x00 0x200>; 231 #mbox-cells = <1>; 232 ti,mbox-num-users = <4>; 233 ti,mbox-num-fifos = <16>; 234 interrupt-parent = <&main_navss_intr>; 235 }; 236 237 mailbox0_cluster11: mailbox@31f8b000 { 238 compatible = "ti,am654-mailbox"; 239 reg = <0x00 0x31f8b000 0x00 0x200>; 240 #mbox-cells = <1>; 241 ti,mbox-num-users = <4>; 242 ti,mbox-num-fifos = <16>; 243 interrupt-parent = <&main_navss_intr>; 244 }; 245 246 main_ringacc: ringacc@3c000000 { 247 compatible = "ti,am654-navss-ringacc"; 248 reg = <0x00 0x3c000000 0x00 0x400000>, 249 <0x00 0x38000000 0x00 0x400000>, 250 <0x00 0x31120000 0x00 0x100>, 251 <0x00 0x33000000 0x00 0x40000>; 252 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 253 ti,num-rings = <1024>; 254 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 255 ti,sci = <&dmsc>; 256 ti,sci-dev-id = <211>; 257 msi-parent = <&main_udmass_inta>; 258 }; 259 260 main_udmap: dma-controller@31150000 { 261 compatible = "ti,j721e-navss-main-udmap"; 262 reg = <0x00 0x31150000 0x00 0x100>, 263 <0x00 0x34000000 0x00 0x100000>, 264 <0x00 0x35000000 0x00 0x100000>; 265 reg-names = "gcfg", "rchanrt", "tchanrt"; 266 msi-parent = <&main_udmass_inta>; 267 #dma-cells = <1>; 268 269 ti,sci = <&dmsc>; 270 ti,sci-dev-id = <212>; 271 ti,ringacc = <&main_ringacc>; 272 273 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 274 <0x0f>, /* TX_HCHAN */ 275 <0x10>; /* TX_UHCHAN */ 276 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 277 <0x0b>, /* RX_HCHAN */ 278 <0x0c>; /* RX_UHCHAN */ 279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 280 }; 281 282 cpts@310d0000 { 283 compatible = "ti,j721e-cpts"; 284 reg = <0x00 0x310d0000 0x00 0x400>; 285 reg-names = "cpts"; 286 clocks = <&k3_clks 201 1>; 287 clock-names = "cpts"; 288 interrupts-extended = <&main_navss_intr 391>; 289 interrupt-names = "cpts"; 290 ti,cpts-periodic-outputs = <6>; 291 ti,cpts-ext-ts-inputs = <8>; 292 }; 293 }; 294 295 main_pmx0: pinctrl@11c000 { 296 compatible = "pinctrl-single"; 297 /* Proxy 0 addressing */ 298 reg = <0x00 0x11c000 0x00 0x10c>; 299 #pinctrl-cells = <1>; 300 pinctrl-single,register-width = <32>; 301 pinctrl-single,function-mask = <0xffffffff>; 302 }; 303 304 main_pmx1: pinctrl@11c11c { 305 compatible = "pinctrl-single"; 306 /* Proxy 0 addressing */ 307 reg = <0x00 0x11c11c 0x00 0xc>; 308 #pinctrl-cells = <1>; 309 pinctrl-single,register-width = <32>; 310 pinctrl-single,function-mask = <0xffffffff>; 311 }; 312 313 main_uart0: serial@2800000 { 314 compatible = "ti,j721e-uart", "ti,am654-uart"; 315 reg = <0x00 0x02800000 0x00 0x100>; 316 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 317 clock-frequency = <48000000>; 318 current-speed = <115200>; 319 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 320 clocks = <&k3_clks 146 2>; 321 clock-names = "fclk"; 322 status = "disabled"; 323 }; 324 325 main_uart1: serial@2810000 { 326 compatible = "ti,j721e-uart", "ti,am654-uart"; 327 reg = <0x00 0x02810000 0x00 0x100>; 328 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 329 clock-frequency = <48000000>; 330 current-speed = <115200>; 331 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 332 clocks = <&k3_clks 278 2>; 333 clock-names = "fclk"; 334 status = "disabled"; 335 }; 336 337 main_uart2: serial@2820000 { 338 compatible = "ti,j721e-uart", "ti,am654-uart"; 339 reg = <0x00 0x02820000 0x00 0x100>; 340 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 341 clock-frequency = <48000000>; 342 current-speed = <115200>; 343 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 344 clocks = <&k3_clks 279 2>; 345 clock-names = "fclk"; 346 status = "disabled"; 347 }; 348 349 main_uart3: serial@2830000 { 350 compatible = "ti,j721e-uart", "ti,am654-uart"; 351 reg = <0x00 0x02830000 0x00 0x100>; 352 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 353 clock-frequency = <48000000>; 354 current-speed = <115200>; 355 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 280 2>; 357 clock-names = "fclk"; 358 status = "disabled"; 359 }; 360 361 main_uart4: serial@2840000 { 362 compatible = "ti,j721e-uart", "ti,am654-uart"; 363 reg = <0x00 0x02840000 0x00 0x100>; 364 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 365 clock-frequency = <48000000>; 366 current-speed = <115200>; 367 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 368 clocks = <&k3_clks 281 2>; 369 clock-names = "fclk"; 370 status = "disabled"; 371 }; 372 373 main_uart5: serial@2850000 { 374 compatible = "ti,j721e-uart", "ti,am654-uart"; 375 reg = <0x00 0x02850000 0x00 0x100>; 376 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 377 clock-frequency = <48000000>; 378 current-speed = <115200>; 379 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 380 clocks = <&k3_clks 282 2>; 381 clock-names = "fclk"; 382 status = "disabled"; 383 }; 384 385 main_uart6: serial@2860000 { 386 compatible = "ti,j721e-uart", "ti,am654-uart"; 387 reg = <0x00 0x02860000 0x00 0x100>; 388 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 389 clock-frequency = <48000000>; 390 current-speed = <115200>; 391 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 392 clocks = <&k3_clks 283 2>; 393 clock-names = "fclk"; 394 status = "disabled"; 395 }; 396 397 main_uart7: serial@2870000 { 398 compatible = "ti,j721e-uart", "ti,am654-uart"; 399 reg = <0x00 0x02870000 0x00 0x100>; 400 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 401 clock-frequency = <48000000>; 402 current-speed = <115200>; 403 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 404 clocks = <&k3_clks 284 2>; 405 clock-names = "fclk"; 406 status = "disabled"; 407 }; 408 409 main_uart8: serial@2880000 { 410 compatible = "ti,j721e-uart", "ti,am654-uart"; 411 reg = <0x00 0x02880000 0x00 0x100>; 412 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 413 clock-frequency = <48000000>; 414 current-speed = <115200>; 415 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 285 2>; 417 clock-names = "fclk"; 418 status = "disabled"; 419 }; 420 421 main_uart9: serial@2890000 { 422 compatible = "ti,j721e-uart", "ti,am654-uart"; 423 reg = <0x00 0x02890000 0x00 0x100>; 424 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 425 clock-frequency = <48000000>; 426 current-speed = <115200>; 427 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 428 clocks = <&k3_clks 286 2>; 429 clock-names = "fclk"; 430 status = "disabled"; 431 }; 432 433 main_i2c0: i2c@2000000 { 434 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 435 reg = <0x00 0x2000000 0x00 0x100>; 436 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 clock-names = "fck"; 440 clocks = <&k3_clks 187 1>; 441 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 442 }; 443 444 main_i2c1: i2c@2010000 { 445 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 446 reg = <0x00 0x2010000 0x00 0x100>; 447 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 clock-names = "fck"; 451 clocks = <&k3_clks 188 1>; 452 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 453 }; 454 455 main_i2c2: i2c@2020000 { 456 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 457 reg = <0x00 0x2020000 0x00 0x100>; 458 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clock-names = "fck"; 462 clocks = <&k3_clks 189 1>; 463 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 464 }; 465 466 main_i2c3: i2c@2030000 { 467 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 468 reg = <0x00 0x2030000 0x00 0x100>; 469 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clock-names = "fck"; 473 clocks = <&k3_clks 190 1>; 474 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 475 }; 476 477 main_i2c4: i2c@2040000 { 478 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 479 reg = <0x00 0x2040000 0x00 0x100>; 480 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 clock-names = "fck"; 484 clocks = <&k3_clks 191 1>; 485 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 486 }; 487 488 main_i2c5: i2c@2050000 { 489 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 490 reg = <0x00 0x2050000 0x00 0x100>; 491 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 clock-names = "fck"; 495 clocks = <&k3_clks 192 1>; 496 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 497 }; 498 499 main_i2c6: i2c@2060000 { 500 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 501 reg = <0x00 0x2060000 0x00 0x100>; 502 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 clock-names = "fck"; 506 clocks = <&k3_clks 193 1>; 507 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 508 }; 509 510 main_sdhci0: mmc@4f80000 { 511 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 512 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 513 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 514 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 515 clock-names = "clk_ahb", "clk_xin"; 516 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 517 ti,otap-del-sel-legacy = <0x0>; 518 ti,otap-del-sel-mmc-hs = <0x0>; 519 ti,otap-del-sel-ddr52 = <0x6>; 520 ti,otap-del-sel-hs200 = <0x8>; 521 ti,otap-del-sel-hs400 = <0x5>; 522 ti,itap-del-sel-legacy = <0x10>; 523 ti,itap-del-sel-mmc-hs = <0xa>; 524 ti,strobe-sel = <0x77>; 525 ti,clkbuf-sel = <0x7>; 526 ti,trm-icp = <0x8>; 527 bus-width = <8>; 528 mmc-ddr-1_8v; 529 mmc-hs200-1_8v; 530 mmc-hs400-1_8v; 531 dma-coherent; 532 }; 533 534 main_sdhci1: mmc@4fb0000 { 535 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 536 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 537 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 538 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 539 clock-names = "clk_ahb", "clk_xin"; 540 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 541 ti,otap-del-sel-legacy = <0x0>; 542 ti,otap-del-sel-sd-hs = <0x0>; 543 ti,otap-del-sel-sdr12 = <0xf>; 544 ti,otap-del-sel-sdr25 = <0xf>; 545 ti,otap-del-sel-sdr50 = <0xc>; 546 ti,otap-del-sel-sdr104 = <0x5>; 547 ti,otap-del-sel-ddr50 = <0xc>; 548 ti,itap-del-sel-legacy = <0x0>; 549 ti,itap-del-sel-sd-hs = <0x0>; 550 ti,itap-del-sel-sdr12 = <0x0>; 551 ti,itap-del-sel-sdr25 = <0x0>; 552 ti,clkbuf-sel = <0x7>; 553 ti,trm-icp = <0x8>; 554 dma-coherent; 555 }; 556 557 serdes_wiz0: wiz@5060000 { 558 compatible = "ti,j721e-wiz-10g"; 559 #address-cells = <1>; 560 #size-cells = <1>; 561 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 562 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 563 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 564 num-lanes = <4>; 565 #reset-cells = <1>; 566 ranges = <0x5060000 0x0 0x5060000 0x10000>; 567 568 assigned-clocks = <&k3_clks 292 85>; 569 assigned-clock-parents = <&k3_clks 292 89>; 570 571 wiz0_pll0_refclk: pll0-refclk { 572 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 573 clock-output-names = "wiz0_pll0_refclk"; 574 #clock-cells = <0>; 575 assigned-clocks = <&wiz0_pll0_refclk>; 576 assigned-clock-parents = <&k3_clks 292 85>; 577 }; 578 579 wiz0_pll1_refclk: pll1-refclk { 580 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 581 clock-output-names = "wiz0_pll1_refclk"; 582 #clock-cells = <0>; 583 assigned-clocks = <&wiz0_pll1_refclk>; 584 assigned-clock-parents = <&k3_clks 292 85>; 585 }; 586 587 wiz0_refclk_dig: refclk-dig { 588 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 589 clock-output-names = "wiz0_refclk_dig"; 590 #clock-cells = <0>; 591 assigned-clocks = <&wiz0_refclk_dig>; 592 assigned-clock-parents = <&k3_clks 292 85>; 593 }; 594 595 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 596 clocks = <&wiz0_refclk_dig>; 597 #clock-cells = <0>; 598 }; 599 600 serdes0: serdes@5060000 { 601 compatible = "ti,j721e-serdes-10g"; 602 reg = <0x05060000 0x00010000>; 603 reg-names = "torrent_phy"; 604 resets = <&serdes_wiz0 0>; 605 reset-names = "torrent_reset"; 606 clocks = <&wiz0_pll0_refclk>; 607 clock-names = "refclk"; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 }; 611 }; 612 613 pcie1_rc: pcie@2910000 { 614 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 615 reg = <0x00 0x02910000 0x00 0x1000>, 616 <0x00 0x02917000 0x00 0x400>, 617 <0x00 0x0d800000 0x00 0x00800000>, 618 <0x00 0x18000000 0x00 0x00001000>; 619 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 620 interrupt-names = "link_state"; 621 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 622 device_type = "pci"; 623 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 624 max-link-speed = <3>; 625 num-lanes = <4>; 626 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 627 clocks = <&k3_clks 240 6>; 628 clock-names = "fck"; 629 #address-cells = <3>; 630 #size-cells = <2>; 631 bus-range = <0x0 0xff>; 632 cdns,no-bar-match-nbits = <64>; 633 vendor-id = <0x104c>; 634 device-id = <0xb00f>; 635 msi-map = <0x0 &gic_its 0x0 0x10000>; 636 dma-coherent; 637 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 638 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 639 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 640 }; 641 642 pcie1_ep: pcie-ep@2910000 { 643 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 644 reg = <0x00 0x02910000 0x00 0x1000>, 645 <0x00 0x02917000 0x00 0x400>, 646 <0x00 0x0d800000 0x00 0x00800000>, 647 <0x00 0x18000000 0x00 0x08000000>; 648 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 649 interrupt-names = "link_state"; 650 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 651 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 652 max-link-speed = <3>; 653 num-lanes = <4>; 654 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 655 clocks = <&k3_clks 240 6>; 656 clock-names = "fck"; 657 max-functions = /bits/ 8 <6>; 658 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 659 dma-coherent; 660 }; 661 662 usbss0: cdns-usb@4104000 { 663 compatible = "ti,j721e-usb"; 664 reg = <0x00 0x4104000 0x00 0x100>; 665 dma-coherent; 666 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 667 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 668 clock-names = "ref", "lpm"; 669 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 670 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 671 #address-cells = <2>; 672 #size-cells = <2>; 673 ranges; 674 675 usb0: usb@6000000 { 676 compatible = "cdns,usb3"; 677 reg = <0x00 0x6000000 0x00 0x10000>, 678 <0x00 0x6010000 0x00 0x10000>, 679 <0x00 0x6020000 0x00 0x10000>; 680 reg-names = "otg", "xhci", "dev"; 681 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 682 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 683 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 684 interrupt-names = "host", 685 "peripheral", 686 "otg"; 687 maximum-speed = "super-speed"; 688 dr_mode = "otg"; 689 cdns,phyrst-a-enable; 690 }; 691 }; 692 693 main_gpio0: gpio@600000 { 694 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 695 reg = <0x00 0x00600000 0x00 0x100>; 696 gpio-controller; 697 #gpio-cells = <2>; 698 interrupt-parent = <&main_gpio_intr>; 699 interrupts = <145>, <146>, <147>, <148>, 700 <149>; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 ti,ngpio = <69>; 704 ti,davinci-gpio-unbanked = <0>; 705 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 706 clocks = <&k3_clks 105 0>; 707 clock-names = "gpio"; 708 }; 709 710 main_gpio2: gpio@610000 { 711 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 712 reg = <0x00 0x00610000 0x00 0x100>; 713 gpio-controller; 714 #gpio-cells = <2>; 715 interrupt-parent = <&main_gpio_intr>; 716 interrupts = <154>, <155>, <156>, <157>, 717 <158>; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 ti,ngpio = <69>; 721 ti,davinci-gpio-unbanked = <0>; 722 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 723 clocks = <&k3_clks 107 0>; 724 clock-names = "gpio"; 725 }; 726 727 main_gpio4: gpio@620000 { 728 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 729 reg = <0x00 0x00620000 0x00 0x100>; 730 gpio-controller; 731 #gpio-cells = <2>; 732 interrupt-parent = <&main_gpio_intr>; 733 interrupts = <163>, <164>, <165>, <166>, 734 <167>; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 ti,ngpio = <69>; 738 ti,davinci-gpio-unbanked = <0>; 739 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 740 clocks = <&k3_clks 109 0>; 741 clock-names = "gpio"; 742 }; 743 744 main_gpio6: gpio@630000 { 745 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 746 reg = <0x00 0x00630000 0x00 0x100>; 747 gpio-controller; 748 #gpio-cells = <2>; 749 interrupt-parent = <&main_gpio_intr>; 750 interrupts = <172>, <173>, <174>, <175>, 751 <176>; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 ti,ngpio = <69>; 755 ti,davinci-gpio-unbanked = <0>; 756 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 757 clocks = <&k3_clks 111 0>; 758 clock-names = "gpio"; 759 }; 760 761 watchdog0: watchdog@2200000 { 762 compatible = "ti,j7-rti-wdt"; 763 reg = <0x0 0x2200000 0x0 0x100>; 764 clocks = <&k3_clks 252 1>; 765 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 766 assigned-clocks = <&k3_clks 252 1>; 767 assigned-clock-parents = <&k3_clks 252 5>; 768 }; 769 770 watchdog1: watchdog@2210000 { 771 compatible = "ti,j7-rti-wdt"; 772 reg = <0x0 0x2210000 0x0 0x100>; 773 clocks = <&k3_clks 253 1>; 774 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 775 assigned-clocks = <&k3_clks 253 1>; 776 assigned-clock-parents = <&k3_clks 253 5>; 777 }; 778 779 main_r5fss0: r5fss@5c00000 { 780 compatible = "ti,j7200-r5fss"; 781 ti,cluster-mode = <1>; 782 #address-cells = <1>; 783 #size-cells = <1>; 784 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 785 <0x5d00000 0x00 0x5d00000 0x20000>; 786 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 787 788 main_r5fss0_core0: r5f@5c00000 { 789 compatible = "ti,j7200-r5f"; 790 reg = <0x5c00000 0x00010000>, 791 <0x5c10000 0x00010000>; 792 reg-names = "atcm", "btcm"; 793 ti,sci = <&dmsc>; 794 ti,sci-dev-id = <245>; 795 ti,sci-proc-ids = <0x06 0xff>; 796 resets = <&k3_reset 245 1>; 797 firmware-name = "j7200-main-r5f0_0-fw"; 798 ti,atcm-enable = <1>; 799 ti,btcm-enable = <1>; 800 ti,loczrama = <1>; 801 }; 802 803 main_r5fss0_core1: r5f@5d00000 { 804 compatible = "ti,j7200-r5f"; 805 reg = <0x5d00000 0x00008000>, 806 <0x5d10000 0x00008000>; 807 reg-names = "atcm", "btcm"; 808 ti,sci = <&dmsc>; 809 ti,sci-dev-id = <246>; 810 ti,sci-proc-ids = <0x07 0xff>; 811 resets = <&k3_reset 246 1>; 812 firmware-name = "j7200-main-r5f0_1-fw"; 813 ti,atcm-enable = <1>; 814 ti,btcm-enable = <1>; 815 ti,loczrama = <1>; 816 }; 817 }; 818}; 819