1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 30 31 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: msi-controller@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 main_gpio_intr: interrupt-controller0 { 44 compatible = "ti,sci-intr"; 45 ti,intr-trigger-type = <1>; 46 interrupt-controller; 47 interrupt-parent = <&gic500>; 48 #interrupt-cells = <1>; 49 ti,sci = <&dmsc>; 50 ti,sci-dev-id = <131>; 51 ti,interrupt-ranges = <8 392 56>; 52 }; 53 54 main_navss: bus@30000000 { 55 compatible = "simple-mfd"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 59 ti,sci-dev-id = <199>; 60 61 main_navss_intr: interrupt-controller1 { 62 compatible = "ti,sci-intr"; 63 ti,intr-trigger-type = <4>; 64 interrupt-controller; 65 interrupt-parent = <&gic500>; 66 #interrupt-cells = <1>; 67 ti,sci = <&dmsc>; 68 ti,sci-dev-id = <213>; 69 ti,interrupt-ranges = <0 64 64>, 70 <64 448 64>, 71 <128 672 64>; 72 }; 73 74 main_udmass_inta: msi-controller@33d00000 { 75 compatible = "ti,sci-inta"; 76 reg = <0x00 0x33d00000 0x00 0x100000>; 77 interrupt-controller; 78 #interrupt-cells = <0>; 79 interrupt-parent = <&main_navss_intr>; 80 msi-controller; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <209>; 83 ti,interrupt-ranges = <0 0 256>; 84 }; 85 86 secure_proxy_main: mailbox@32c00000 { 87 compatible = "ti,am654-secure-proxy"; 88 #mbox-cells = <1>; 89 reg-names = "target_data", "rt", "scfg"; 90 reg = <0x00 0x32c00000 0x00 0x100000>, 91 <0x00 0x32400000 0x00 0x100000>, 92 <0x00 0x32800000 0x00 0x100000>; 93 interrupt-names = "rx_011"; 94 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 95 }; 96 }; 97 98 main_pmx0: pinctrl@11c000 { 99 compatible = "pinctrl-single"; 100 /* Proxy 0 addressing */ 101 reg = <0x00 0x11c000 0x00 0x2b4>; 102 #pinctrl-cells = <1>; 103 pinctrl-single,register-width = <32>; 104 pinctrl-single,function-mask = <0xffffffff>; 105 }; 106 107 main_uart0: serial@2800000 { 108 compatible = "ti,j721e-uart", "ti,am654-uart"; 109 reg = <0x00 0x02800000 0x00 0x100>; 110 reg-shift = <2>; 111 reg-io-width = <4>; 112 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 113 clock-frequency = <48000000>; 114 current-speed = <115200>; 115 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 116 clocks = <&k3_clks 146 2>; 117 clock-names = "fclk"; 118 }; 119 120 main_uart1: serial@2810000 { 121 compatible = "ti,j721e-uart", "ti,am654-uart"; 122 reg = <0x00 0x02810000 0x00 0x100>; 123 reg-shift = <2>; 124 reg-io-width = <4>; 125 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 126 clock-frequency = <48000000>; 127 current-speed = <115200>; 128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 129 clocks = <&k3_clks 278 2>; 130 clock-names = "fclk"; 131 }; 132 133 main_uart2: serial@2820000 { 134 compatible = "ti,j721e-uart", "ti,am654-uart"; 135 reg = <0x00 0x02820000 0x00 0x100>; 136 reg-shift = <2>; 137 reg-io-width = <4>; 138 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 139 clock-frequency = <48000000>; 140 current-speed = <115200>; 141 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 142 clocks = <&k3_clks 279 2>; 143 clock-names = "fclk"; 144 }; 145 146 main_uart3: serial@2830000 { 147 compatible = "ti,j721e-uart", "ti,am654-uart"; 148 reg = <0x00 0x02830000 0x00 0x100>; 149 reg-shift = <2>; 150 reg-io-width = <4>; 151 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 152 clock-frequency = <48000000>; 153 current-speed = <115200>; 154 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 155 clocks = <&k3_clks 280 2>; 156 clock-names = "fclk"; 157 }; 158 159 main_uart4: serial@2840000 { 160 compatible = "ti,j721e-uart", "ti,am654-uart"; 161 reg = <0x00 0x02840000 0x00 0x100>; 162 reg-shift = <2>; 163 reg-io-width = <4>; 164 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 165 clock-frequency = <48000000>; 166 current-speed = <115200>; 167 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 168 clocks = <&k3_clks 281 2>; 169 clock-names = "fclk"; 170 }; 171 172 main_uart5: serial@2850000 { 173 compatible = "ti,j721e-uart", "ti,am654-uart"; 174 reg = <0x00 0x02850000 0x00 0x100>; 175 reg-shift = <2>; 176 reg-io-width = <4>; 177 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 178 clock-frequency = <48000000>; 179 current-speed = <115200>; 180 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 181 clocks = <&k3_clks 282 2>; 182 clock-names = "fclk"; 183 }; 184 185 main_uart6: serial@2860000 { 186 compatible = "ti,j721e-uart", "ti,am654-uart"; 187 reg = <0x00 0x02860000 0x00 0x100>; 188 reg-shift = <2>; 189 reg-io-width = <4>; 190 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 191 clock-frequency = <48000000>; 192 current-speed = <115200>; 193 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 194 clocks = <&k3_clks 283 2>; 195 clock-names = "fclk"; 196 }; 197 198 main_uart7: serial@2870000 { 199 compatible = "ti,j721e-uart", "ti,am654-uart"; 200 reg = <0x00 0x02870000 0x00 0x100>; 201 reg-shift = <2>; 202 reg-io-width = <4>; 203 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 204 clock-frequency = <48000000>; 205 current-speed = <115200>; 206 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 207 clocks = <&k3_clks 284 2>; 208 clock-names = "fclk"; 209 }; 210 211 main_uart8: serial@2880000 { 212 compatible = "ti,j721e-uart", "ti,am654-uart"; 213 reg = <0x00 0x02880000 0x00 0x100>; 214 reg-shift = <2>; 215 reg-io-width = <4>; 216 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 217 clock-frequency = <48000000>; 218 current-speed = <115200>; 219 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 220 clocks = <&k3_clks 285 2>; 221 clock-names = "fclk"; 222 }; 223 224 main_uart9: serial@2890000 { 225 compatible = "ti,j721e-uart", "ti,am654-uart"; 226 reg = <0x00 0x02890000 0x00 0x100>; 227 reg-shift = <2>; 228 reg-io-width = <4>; 229 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 230 clock-frequency = <48000000>; 231 current-speed = <115200>; 232 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 233 clocks = <&k3_clks 286 2>; 234 clock-names = "fclk"; 235 }; 236}; 237