1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 scm_conf: scm-conf@100000 { 22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 23 reg = <0x00 0x00100000 0x00 0x1c000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges = <0x00 0x00 0x00100000 0x1c000>; 27 28 serdes_ln_ctrl: serdes-ln-ctrl@4080 { 29 compatible = "mmio-mux"; 30 #mux-control-cells = <1>; 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 33 }; 34 35 usb_serdes_mux: mux-controller@4000 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 39 }; 40 }; 41 42 gic500: interrupt-controller@1800000 { 43 compatible = "arm,gic-v3"; 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 #interrupt-cells = <3>; 48 interrupt-controller; 49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 50 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 51 52 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 53 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 54 55 gic_its: msi-controller@1820000 { 56 compatible = "arm,gic-v3-its"; 57 reg = <0x00 0x01820000 0x00 0x10000>; 58 socionext,synquacer-pre-its = <0x1000000 0x400000>; 59 msi-controller; 60 #msi-cells = <1>; 61 }; 62 }; 63 64 main_gpio_intr: interrupt-controller0 { 65 compatible = "ti,sci-intr"; 66 ti,intr-trigger-type = <1>; 67 interrupt-controller; 68 interrupt-parent = <&gic500>; 69 #interrupt-cells = <1>; 70 ti,sci = <&dmsc>; 71 ti,sci-dev-id = <131>; 72 ti,interrupt-ranges = <8 392 56>; 73 }; 74 75 main_navss: bus@30000000 { 76 compatible = "simple-mfd"; 77 #address-cells = <2>; 78 #size-cells = <2>; 79 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 80 ti,sci-dev-id = <199>; 81 82 main_navss_intr: interrupt-controller1 { 83 compatible = "ti,sci-intr"; 84 ti,intr-trigger-type = <4>; 85 interrupt-controller; 86 interrupt-parent = <&gic500>; 87 #interrupt-cells = <1>; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <213>; 90 ti,interrupt-ranges = <0 64 64>, 91 <64 448 64>, 92 <128 672 64>; 93 }; 94 95 main_udmass_inta: msi-controller@33d00000 { 96 compatible = "ti,sci-inta"; 97 reg = <0x00 0x33d00000 0x00 0x100000>; 98 interrupt-controller; 99 #interrupt-cells = <0>; 100 interrupt-parent = <&main_navss_intr>; 101 msi-controller; 102 ti,sci = <&dmsc>; 103 ti,sci-dev-id = <209>; 104 ti,interrupt-ranges = <0 0 256>; 105 }; 106 107 secure_proxy_main: mailbox@32c00000 { 108 compatible = "ti,am654-secure-proxy"; 109 #mbox-cells = <1>; 110 reg-names = "target_data", "rt", "scfg"; 111 reg = <0x00 0x32c00000 0x00 0x100000>, 112 <0x00 0x32400000 0x00 0x100000>, 113 <0x00 0x32800000 0x00 0x100000>; 114 interrupt-names = "rx_011"; 115 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 118 main_ringacc: ringacc@3c000000 { 119 compatible = "ti,am654-navss-ringacc"; 120 reg = <0x00 0x3c000000 0x00 0x400000>, 121 <0x00 0x38000000 0x00 0x400000>, 122 <0x00 0x31120000 0x00 0x100>, 123 <0x00 0x33000000 0x00 0x40000>; 124 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 125 ti,num-rings = <1024>; 126 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 127 ti,sci = <&dmsc>; 128 ti,sci-dev-id = <211>; 129 msi-parent = <&main_udmass_inta>; 130 }; 131 132 main_udmap: dma-controller@31150000 { 133 compatible = "ti,j721e-navss-main-udmap"; 134 reg = <0x00 0x31150000 0x00 0x100>, 135 <0x00 0x34000000 0x00 0x100000>, 136 <0x00 0x35000000 0x00 0x100000>; 137 reg-names = "gcfg", "rchanrt", "tchanrt"; 138 msi-parent = <&main_udmass_inta>; 139 #dma-cells = <1>; 140 141 ti,sci = <&dmsc>; 142 ti,sci-dev-id = <212>; 143 ti,ringacc = <&main_ringacc>; 144 145 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 146 <0x0f>, /* TX_HCHAN */ 147 <0x10>; /* TX_UHCHAN */ 148 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 149 <0x0b>, /* RX_HCHAN */ 150 <0x0c>; /* RX_UHCHAN */ 151 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 152 }; 153 154 cpts@310d0000 { 155 compatible = "ti,j721e-cpts"; 156 reg = <0x00 0x310d0000 0x00 0x400>; 157 reg-names = "cpts"; 158 clocks = <&k3_clks 201 1>; 159 clock-names = "cpts"; 160 interrupts-extended = <&main_navss_intr 391>; 161 interrupt-names = "cpts"; 162 ti,cpts-periodic-outputs = <6>; 163 ti,cpts-ext-ts-inputs = <8>; 164 }; 165 }; 166 167 main_pmx0: pinctrl@11c000 { 168 compatible = "pinctrl-single"; 169 /* Proxy 0 addressing */ 170 reg = <0x00 0x11c000 0x00 0x2b4>; 171 #pinctrl-cells = <1>; 172 pinctrl-single,register-width = <32>; 173 pinctrl-single,function-mask = <0xffffffff>; 174 }; 175 176 main_uart0: serial@2800000 { 177 compatible = "ti,j721e-uart", "ti,am654-uart"; 178 reg = <0x00 0x02800000 0x00 0x100>; 179 reg-shift = <2>; 180 reg-io-width = <4>; 181 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 182 clock-frequency = <48000000>; 183 current-speed = <115200>; 184 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 185 clocks = <&k3_clks 146 2>; 186 clock-names = "fclk"; 187 }; 188 189 main_uart1: serial@2810000 { 190 compatible = "ti,j721e-uart", "ti,am654-uart"; 191 reg = <0x00 0x02810000 0x00 0x100>; 192 reg-shift = <2>; 193 reg-io-width = <4>; 194 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 195 clock-frequency = <48000000>; 196 current-speed = <115200>; 197 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 198 clocks = <&k3_clks 278 2>; 199 clock-names = "fclk"; 200 }; 201 202 main_uart2: serial@2820000 { 203 compatible = "ti,j721e-uart", "ti,am654-uart"; 204 reg = <0x00 0x02820000 0x00 0x100>; 205 reg-shift = <2>; 206 reg-io-width = <4>; 207 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 208 clock-frequency = <48000000>; 209 current-speed = <115200>; 210 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 211 clocks = <&k3_clks 279 2>; 212 clock-names = "fclk"; 213 }; 214 215 main_uart3: serial@2830000 { 216 compatible = "ti,j721e-uart", "ti,am654-uart"; 217 reg = <0x00 0x02830000 0x00 0x100>; 218 reg-shift = <2>; 219 reg-io-width = <4>; 220 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 221 clock-frequency = <48000000>; 222 current-speed = <115200>; 223 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 224 clocks = <&k3_clks 280 2>; 225 clock-names = "fclk"; 226 }; 227 228 main_uart4: serial@2840000 { 229 compatible = "ti,j721e-uart", "ti,am654-uart"; 230 reg = <0x00 0x02840000 0x00 0x100>; 231 reg-shift = <2>; 232 reg-io-width = <4>; 233 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 234 clock-frequency = <48000000>; 235 current-speed = <115200>; 236 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 237 clocks = <&k3_clks 281 2>; 238 clock-names = "fclk"; 239 }; 240 241 main_uart5: serial@2850000 { 242 compatible = "ti,j721e-uart", "ti,am654-uart"; 243 reg = <0x00 0x02850000 0x00 0x100>; 244 reg-shift = <2>; 245 reg-io-width = <4>; 246 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 247 clock-frequency = <48000000>; 248 current-speed = <115200>; 249 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 250 clocks = <&k3_clks 282 2>; 251 clock-names = "fclk"; 252 }; 253 254 main_uart6: serial@2860000 { 255 compatible = "ti,j721e-uart", "ti,am654-uart"; 256 reg = <0x00 0x02860000 0x00 0x100>; 257 reg-shift = <2>; 258 reg-io-width = <4>; 259 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <48000000>; 261 current-speed = <115200>; 262 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 283 2>; 264 clock-names = "fclk"; 265 }; 266 267 main_uart7: serial@2870000 { 268 compatible = "ti,j721e-uart", "ti,am654-uart"; 269 reg = <0x00 0x02870000 0x00 0x100>; 270 reg-shift = <2>; 271 reg-io-width = <4>; 272 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 273 clock-frequency = <48000000>; 274 current-speed = <115200>; 275 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 276 clocks = <&k3_clks 284 2>; 277 clock-names = "fclk"; 278 }; 279 280 main_uart8: serial@2880000 { 281 compatible = "ti,j721e-uart", "ti,am654-uart"; 282 reg = <0x00 0x02880000 0x00 0x100>; 283 reg-shift = <2>; 284 reg-io-width = <4>; 285 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 286 clock-frequency = <48000000>; 287 current-speed = <115200>; 288 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 289 clocks = <&k3_clks 285 2>; 290 clock-names = "fclk"; 291 }; 292 293 main_uart9: serial@2890000 { 294 compatible = "ti,j721e-uart", "ti,am654-uart"; 295 reg = <0x00 0x02890000 0x00 0x100>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 299 clock-frequency = <48000000>; 300 current-speed = <115200>; 301 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 302 clocks = <&k3_clks 286 2>; 303 clock-names = "fclk"; 304 }; 305 306 main_i2c0: i2c@2000000 { 307 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 308 reg = <0x00 0x2000000 0x00 0x100>; 309 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 clock-names = "fck"; 313 clocks = <&k3_clks 187 1>; 314 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 315 }; 316 317 main_i2c1: i2c@2010000 { 318 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 319 reg = <0x00 0x2010000 0x00 0x100>; 320 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 clock-names = "fck"; 324 clocks = <&k3_clks 188 1>; 325 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 326 }; 327 328 main_i2c2: i2c@2020000 { 329 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 330 reg = <0x00 0x2020000 0x00 0x100>; 331 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 clock-names = "fck"; 335 clocks = <&k3_clks 189 1>; 336 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 337 }; 338 339 main_i2c3: i2c@2030000 { 340 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 341 reg = <0x00 0x2030000 0x00 0x100>; 342 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 clock-names = "fck"; 346 clocks = <&k3_clks 190 1>; 347 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 348 }; 349 350 main_i2c4: i2c@2040000 { 351 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 352 reg = <0x00 0x2040000 0x00 0x100>; 353 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clock-names = "fck"; 357 clocks = <&k3_clks 191 1>; 358 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 359 }; 360 361 main_i2c5: i2c@2050000 { 362 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 363 reg = <0x00 0x2050000 0x00 0x100>; 364 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 clock-names = "fck"; 368 clocks = <&k3_clks 192 1>; 369 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 370 }; 371 372 main_i2c6: i2c@2060000 { 373 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 374 reg = <0x00 0x2060000 0x00 0x100>; 375 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clock-names = "fck"; 379 clocks = <&k3_clks 193 1>; 380 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 381 }; 382 383 main_sdhci0: mmc@4f80000 { 384 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 385 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 386 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 387 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 388 clock-names = "clk_xin", "clk_ahb"; 389 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; 390 ti,otap-del-sel-legacy = <0x0>; 391 ti,otap-del-sel-mmc-hs = <0x0>; 392 ti,otap-del-sel-ddr52 = <0x6>; 393 ti,otap-del-sel-hs200 = <0x8>; 394 ti,otap-del-sel-hs400 = <0x0>; 395 ti,strobe-sel = <0x77>; 396 ti,trm-icp = <0x8>; 397 bus-width = <8>; 398 mmc-ddr-1_8v; 399 dma-coherent; 400 }; 401 402 main_sdhci1: mmc@4fb0000 { 403 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 404 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 405 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 406 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 407 clock-names = "clk_xin", "clk_ahb"; 408 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; 409 ti,otap-del-sel-legacy = <0x0>; 410 ti,otap-del-sel-sd-hs = <0x0>; 411 ti,otap-del-sel-sdr12 = <0xf>; 412 ti,otap-del-sel-sdr25 = <0xf>; 413 ti,otap-del-sel-sdr50 = <0xc>; 414 ti,otap-del-sel-sdr104 = <0x5>; 415 ti,otap-del-sel-ddr50 = <0xc>; 416 no-1-8-v; 417 dma-coherent; 418 }; 419}; 420