1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 cpsw0_phy_gmii_sel: phy@4044 { 43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 44 ti,qsgmii-main-ports = <1>; 45 reg = <0x4044 0x10>; 46 #phy-cells = <1>; 47 }; 48 49 usb_serdes_mux: mux-controller@4000 { 50 compatible = "mmio-mux"; 51 #mux-control-cells = <1>; 52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 53 }; 54 }; 55 56 gic500: interrupt-controller@1800000 { 57 compatible = "arm,gic-v3"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 #interrupt-cells = <3>; 62 interrupt-controller; 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 64 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 68 69 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 main_gpio_intr: interrupt-controller@a00000 { 82 compatible = "ti,sci-intr"; 83 reg = <0x00 0x00a00000 0x00 0x800>; 84 ti,intr-trigger-type = <1>; 85 interrupt-controller; 86 interrupt-parent = <&gic500>; 87 #interrupt-cells = <1>; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <131>; 90 ti,interrupt-ranges = <8 392 56>; 91 }; 92 93 main_navss: bus@30000000 { 94 compatible = "simple-mfd"; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 98 ti,sci-dev-id = <199>; 99 dma-coherent; 100 dma-ranges; 101 102 main_navss_intr: interrupt-controller@310e0000 { 103 compatible = "ti,sci-intr"; 104 reg = <0x00 0x310e0000 0x00 0x4000>; 105 ti,intr-trigger-type = <4>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 #interrupt-cells = <1>; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <213>; 111 ti,interrupt-ranges = <0 64 64>, 112 <64 448 64>, 113 <128 672 64>; 114 }; 115 116 main_udmass_inta: msi-controller@33d00000 { 117 compatible = "ti,sci-inta"; 118 reg = <0x00 0x33d00000 0x00 0x100000>; 119 interrupt-controller; 120 #interrupt-cells = <0>; 121 interrupt-parent = <&main_navss_intr>; 122 msi-controller; 123 ti,sci = <&dmsc>; 124 ti,sci-dev-id = <209>; 125 ti,interrupt-ranges = <0 0 256>; 126 }; 127 128 secure_proxy_main: mailbox@32c00000 { 129 compatible = "ti,am654-secure-proxy"; 130 #mbox-cells = <1>; 131 reg-names = "target_data", "rt", "scfg"; 132 reg = <0x00 0x32c00000 0x00 0x100000>, 133 <0x00 0x32400000 0x00 0x100000>, 134 <0x00 0x32800000 0x00 0x100000>; 135 interrupt-names = "rx_011"; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 hwspinlock: spinlock@30e00000 { 140 compatible = "ti,am654-hwspinlock"; 141 reg = <0x00 0x30e00000 0x00 0x1000>; 142 #hwlock-cells = <1>; 143 }; 144 145 mailbox0_cluster0: mailbox@31f80000 { 146 compatible = "ti,am654-mailbox"; 147 reg = <0x00 0x31f80000 0x00 0x200>; 148 #mbox-cells = <1>; 149 ti,mbox-num-users = <4>; 150 ti,mbox-num-fifos = <16>; 151 interrupt-parent = <&main_navss_intr>; 152 status = "disabled"; 153 }; 154 155 mailbox0_cluster1: mailbox@31f81000 { 156 compatible = "ti,am654-mailbox"; 157 reg = <0x00 0x31f81000 0x00 0x200>; 158 #mbox-cells = <1>; 159 ti,mbox-num-users = <4>; 160 ti,mbox-num-fifos = <16>; 161 interrupt-parent = <&main_navss_intr>; 162 status = "disabled"; 163 }; 164 165 mailbox0_cluster2: mailbox@31f82000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f82000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 status = "disabled"; 173 }; 174 175 mailbox0_cluster3: mailbox@31f83000 { 176 compatible = "ti,am654-mailbox"; 177 reg = <0x00 0x31f83000 0x00 0x200>; 178 #mbox-cells = <1>; 179 ti,mbox-num-users = <4>; 180 ti,mbox-num-fifos = <16>; 181 interrupt-parent = <&main_navss_intr>; 182 status = "disabled"; 183 }; 184 185 mailbox0_cluster4: mailbox@31f84000 { 186 compatible = "ti,am654-mailbox"; 187 reg = <0x00 0x31f84000 0x00 0x200>; 188 #mbox-cells = <1>; 189 ti,mbox-num-users = <4>; 190 ti,mbox-num-fifos = <16>; 191 interrupt-parent = <&main_navss_intr>; 192 status = "disabled"; 193 }; 194 195 mailbox0_cluster5: mailbox@31f85000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f85000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 status = "disabled"; 203 }; 204 205 mailbox0_cluster6: mailbox@31f86000 { 206 compatible = "ti,am654-mailbox"; 207 reg = <0x00 0x31f86000 0x00 0x200>; 208 #mbox-cells = <1>; 209 ti,mbox-num-users = <4>; 210 ti,mbox-num-fifos = <16>; 211 interrupt-parent = <&main_navss_intr>; 212 status = "disabled"; 213 }; 214 215 mailbox0_cluster7: mailbox@31f87000 { 216 compatible = "ti,am654-mailbox"; 217 reg = <0x00 0x31f87000 0x00 0x200>; 218 #mbox-cells = <1>; 219 ti,mbox-num-users = <4>; 220 ti,mbox-num-fifos = <16>; 221 interrupt-parent = <&main_navss_intr>; 222 status = "disabled"; 223 }; 224 225 mailbox0_cluster8: mailbox@31f88000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f88000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 status = "disabled"; 233 }; 234 235 mailbox0_cluster9: mailbox@31f89000 { 236 compatible = "ti,am654-mailbox"; 237 reg = <0x00 0x31f89000 0x00 0x200>; 238 #mbox-cells = <1>; 239 ti,mbox-num-users = <4>; 240 ti,mbox-num-fifos = <16>; 241 interrupt-parent = <&main_navss_intr>; 242 status = "disabled"; 243 }; 244 245 mailbox0_cluster10: mailbox@31f8a000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f8a000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster11: mailbox@31f8b000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f8b000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 main_ringacc: ringacc@3c000000 { 266 compatible = "ti,am654-navss-ringacc"; 267 reg = <0x00 0x3c000000 0x00 0x400000>, 268 <0x00 0x38000000 0x00 0x400000>, 269 <0x00 0x31120000 0x00 0x100>, 270 <0x00 0x33000000 0x00 0x40000>; 271 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 272 ti,num-rings = <1024>; 273 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 274 ti,sci = <&dmsc>; 275 ti,sci-dev-id = <211>; 276 msi-parent = <&main_udmass_inta>; 277 }; 278 279 main_udmap: dma-controller@31150000 { 280 compatible = "ti,j721e-navss-main-udmap"; 281 reg = <0x00 0x31150000 0x00 0x100>, 282 <0x00 0x34000000 0x00 0x100000>, 283 <0x00 0x35000000 0x00 0x100000>; 284 reg-names = "gcfg", "rchanrt", "tchanrt"; 285 msi-parent = <&main_udmass_inta>; 286 #dma-cells = <1>; 287 288 ti,sci = <&dmsc>; 289 ti,sci-dev-id = <212>; 290 ti,ringacc = <&main_ringacc>; 291 292 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 293 <0x0f>, /* TX_HCHAN */ 294 <0x10>; /* TX_UHCHAN */ 295 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 296 <0x0b>, /* RX_HCHAN */ 297 <0x0c>; /* RX_UHCHAN */ 298 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 299 }; 300 301 cpts@310d0000 { 302 compatible = "ti,j721e-cpts"; 303 reg = <0x00 0x310d0000 0x00 0x400>; 304 reg-names = "cpts"; 305 clocks = <&k3_clks 201 1>; 306 clock-names = "cpts"; 307 interrupts-extended = <&main_navss_intr 391>; 308 interrupt-names = "cpts"; 309 ti,cpts-periodic-outputs = <6>; 310 ti,cpts-ext-ts-inputs = <8>; 311 }; 312 }; 313 314 cpsw0: ethernet@c000000 { 315 compatible = "ti,j7200-cpswxg-nuss"; 316 #address-cells = <2>; 317 #size-cells = <2>; 318 reg = <0x00 0xc000000 0x00 0x200000>; 319 reg-names = "cpsw_nuss"; 320 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 321 clocks = <&k3_clks 19 33>; 322 clock-names = "fck"; 323 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 324 325 dmas = <&main_udmap 0xca00>, 326 <&main_udmap 0xca01>, 327 <&main_udmap 0xca02>, 328 <&main_udmap 0xca03>, 329 <&main_udmap 0xca04>, 330 <&main_udmap 0xca05>, 331 <&main_udmap 0xca06>, 332 <&main_udmap 0xca07>, 333 <&main_udmap 0x4a00>; 334 dma-names = "tx0", "tx1", "tx2", "tx3", 335 "tx4", "tx5", "tx6", "tx7", 336 "rx"; 337 338 status = "disabled"; 339 340 ethernet-ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 cpsw0_port1: port@1 { 344 reg = <1>; 345 ti,mac-only; 346 label = "port1"; 347 status = "disabled"; 348 }; 349 350 cpsw0_port2: port@2 { 351 reg = <2>; 352 ti,mac-only; 353 label = "port2"; 354 status = "disabled"; 355 }; 356 357 cpsw0_port3: port@3 { 358 reg = <3>; 359 ti,mac-only; 360 label = "port3"; 361 status = "disabled"; 362 }; 363 364 cpsw0_port4: port@4 { 365 reg = <4>; 366 ti,mac-only; 367 label = "port4"; 368 status = "disabled"; 369 }; 370 }; 371 372 cpsw5g_mdio: mdio@f00 { 373 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 374 reg = <0x00 0xf00 0x00 0x100>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clocks = <&k3_clks 19 33>; 378 clock-names = "fck"; 379 bus_freq = <1000000>; 380 status = "disabled"; 381 }; 382 383 cpts@3d000 { 384 compatible = "ti,j721e-cpts"; 385 reg = <0x00 0x3d000 0x00 0x400>; 386 clocks = <&k3_clks 19 16>; 387 clock-names = "cpts"; 388 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-names = "cpts"; 390 ti,cpts-ext-ts-inputs = <4>; 391 ti,cpts-periodic-outputs = <2>; 392 }; 393 }; 394 395 main_pmx0: pinctrl@11c000 { 396 compatible = "pinctrl-single"; 397 /* Proxy 0 addressing */ 398 reg = <0x00 0x11c000 0x00 0x10c>; 399 #pinctrl-cells = <1>; 400 pinctrl-single,register-width = <32>; 401 pinctrl-single,function-mask = <0xffffffff>; 402 }; 403 404 main_pmx1: pinctrl@11c11c { 405 compatible = "pinctrl-single"; 406 /* Proxy 0 addressing */ 407 reg = <0x00 0x11c11c 0x00 0xc>; 408 #pinctrl-cells = <1>; 409 pinctrl-single,register-width = <32>; 410 pinctrl-single,function-mask = <0xffffffff>; 411 }; 412 413 main_uart0: serial@2800000 { 414 compatible = "ti,j721e-uart", "ti,am654-uart"; 415 reg = <0x00 0x02800000 0x00 0x100>; 416 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 417 clock-frequency = <48000000>; 418 current-speed = <115200>; 419 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 146 2>; 421 clock-names = "fclk"; 422 status = "disabled"; 423 }; 424 425 main_uart1: serial@2810000 { 426 compatible = "ti,j721e-uart", "ti,am654-uart"; 427 reg = <0x00 0x02810000 0x00 0x100>; 428 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 429 clock-frequency = <48000000>; 430 current-speed = <115200>; 431 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 432 clocks = <&k3_clks 278 2>; 433 clock-names = "fclk"; 434 status = "disabled"; 435 }; 436 437 main_uart2: serial@2820000 { 438 compatible = "ti,j721e-uart", "ti,am654-uart"; 439 reg = <0x00 0x02820000 0x00 0x100>; 440 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 441 clock-frequency = <48000000>; 442 current-speed = <115200>; 443 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 444 clocks = <&k3_clks 279 2>; 445 clock-names = "fclk"; 446 status = "disabled"; 447 }; 448 449 main_uart3: serial@2830000 { 450 compatible = "ti,j721e-uart", "ti,am654-uart"; 451 reg = <0x00 0x02830000 0x00 0x100>; 452 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 453 clock-frequency = <48000000>; 454 current-speed = <115200>; 455 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 280 2>; 457 clock-names = "fclk"; 458 status = "disabled"; 459 }; 460 461 main_uart4: serial@2840000 { 462 compatible = "ti,j721e-uart", "ti,am654-uart"; 463 reg = <0x00 0x02840000 0x00 0x100>; 464 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 465 clock-frequency = <48000000>; 466 current-speed = <115200>; 467 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 468 clocks = <&k3_clks 281 2>; 469 clock-names = "fclk"; 470 status = "disabled"; 471 }; 472 473 main_uart5: serial@2850000 { 474 compatible = "ti,j721e-uart", "ti,am654-uart"; 475 reg = <0x00 0x02850000 0x00 0x100>; 476 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 477 clock-frequency = <48000000>; 478 current-speed = <115200>; 479 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 480 clocks = <&k3_clks 282 2>; 481 clock-names = "fclk"; 482 status = "disabled"; 483 }; 484 485 main_uart6: serial@2860000 { 486 compatible = "ti,j721e-uart", "ti,am654-uart"; 487 reg = <0x00 0x02860000 0x00 0x100>; 488 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 489 clock-frequency = <48000000>; 490 current-speed = <115200>; 491 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 492 clocks = <&k3_clks 283 2>; 493 clock-names = "fclk"; 494 status = "disabled"; 495 }; 496 497 main_uart7: serial@2870000 { 498 compatible = "ti,j721e-uart", "ti,am654-uart"; 499 reg = <0x00 0x02870000 0x00 0x100>; 500 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 501 clock-frequency = <48000000>; 502 current-speed = <115200>; 503 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 504 clocks = <&k3_clks 284 2>; 505 clock-names = "fclk"; 506 status = "disabled"; 507 }; 508 509 main_uart8: serial@2880000 { 510 compatible = "ti,j721e-uart", "ti,am654-uart"; 511 reg = <0x00 0x02880000 0x00 0x100>; 512 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 513 clock-frequency = <48000000>; 514 current-speed = <115200>; 515 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 516 clocks = <&k3_clks 285 2>; 517 clock-names = "fclk"; 518 status = "disabled"; 519 }; 520 521 main_uart9: serial@2890000 { 522 compatible = "ti,j721e-uart", "ti,am654-uart"; 523 reg = <0x00 0x02890000 0x00 0x100>; 524 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 525 clock-frequency = <48000000>; 526 current-speed = <115200>; 527 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 528 clocks = <&k3_clks 286 2>; 529 clock-names = "fclk"; 530 status = "disabled"; 531 }; 532 533 main_i2c0: i2c@2000000 { 534 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 535 reg = <0x00 0x2000000 0x00 0x100>; 536 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 clock-names = "fck"; 540 clocks = <&k3_clks 187 1>; 541 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 542 status = "disabled"; 543 }; 544 545 main_i2c1: i2c@2010000 { 546 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 547 reg = <0x00 0x2010000 0x00 0x100>; 548 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clock-names = "fck"; 552 clocks = <&k3_clks 188 1>; 553 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 554 status = "disabled"; 555 }; 556 557 main_i2c2: i2c@2020000 { 558 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 559 reg = <0x00 0x2020000 0x00 0x100>; 560 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clock-names = "fck"; 564 clocks = <&k3_clks 189 1>; 565 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 566 status = "disabled"; 567 }; 568 569 main_i2c3: i2c@2030000 { 570 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 571 reg = <0x00 0x2030000 0x00 0x100>; 572 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clock-names = "fck"; 576 clocks = <&k3_clks 190 1>; 577 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 578 status = "disabled"; 579 }; 580 581 main_i2c4: i2c@2040000 { 582 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 583 reg = <0x00 0x2040000 0x00 0x100>; 584 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 clock-names = "fck"; 588 clocks = <&k3_clks 191 1>; 589 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 590 status = "disabled"; 591 }; 592 593 main_i2c5: i2c@2050000 { 594 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 595 reg = <0x00 0x2050000 0x00 0x100>; 596 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 clock-names = "fck"; 600 clocks = <&k3_clks 192 1>; 601 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 602 status = "disabled"; 603 }; 604 605 main_i2c6: i2c@2060000 { 606 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 607 reg = <0x00 0x2060000 0x00 0x100>; 608 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 clock-names = "fck"; 612 clocks = <&k3_clks 193 1>; 613 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 614 status = "disabled"; 615 }; 616 617 main_sdhci0: mmc@4f80000 { 618 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 619 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 620 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 621 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 622 clock-names = "clk_ahb", "clk_xin"; 623 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 624 ti,otap-del-sel-legacy = <0x0>; 625 ti,otap-del-sel-mmc-hs = <0x0>; 626 ti,otap-del-sel-ddr52 = <0x6>; 627 ti,otap-del-sel-hs200 = <0x8>; 628 ti,otap-del-sel-hs400 = <0x5>; 629 ti,itap-del-sel-legacy = <0x10>; 630 ti,itap-del-sel-mmc-hs = <0xa>; 631 ti,strobe-sel = <0x77>; 632 ti,clkbuf-sel = <0x7>; 633 ti,trm-icp = <0x8>; 634 bus-width = <8>; 635 mmc-ddr-1_8v; 636 mmc-hs200-1_8v; 637 mmc-hs400-1_8v; 638 dma-coherent; 639 }; 640 641 main_sdhci1: mmc@4fb0000 { 642 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 643 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 644 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 645 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 646 clock-names = "clk_ahb", "clk_xin"; 647 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 648 ti,otap-del-sel-legacy = <0x0>; 649 ti,otap-del-sel-sd-hs = <0x0>; 650 ti,otap-del-sel-sdr12 = <0xf>; 651 ti,otap-del-sel-sdr25 = <0xf>; 652 ti,otap-del-sel-sdr50 = <0xc>; 653 ti,otap-del-sel-sdr104 = <0x5>; 654 ti,otap-del-sel-ddr50 = <0xc>; 655 ti,itap-del-sel-legacy = <0x0>; 656 ti,itap-del-sel-sd-hs = <0x0>; 657 ti,itap-del-sel-sdr12 = <0x0>; 658 ti,itap-del-sel-sdr25 = <0x0>; 659 ti,clkbuf-sel = <0x7>; 660 ti,trm-icp = <0x8>; 661 dma-coherent; 662 }; 663 664 serdes_wiz0: wiz@5060000 { 665 compatible = "ti,j721e-wiz-10g"; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 669 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 670 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 671 num-lanes = <4>; 672 #reset-cells = <1>; 673 ranges = <0x5060000 0x0 0x5060000 0x10000>; 674 675 assigned-clocks = <&k3_clks 292 85>; 676 assigned-clock-parents = <&k3_clks 292 89>; 677 678 wiz0_pll0_refclk: pll0-refclk { 679 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 680 clock-output-names = "wiz0_pll0_refclk"; 681 #clock-cells = <0>; 682 assigned-clocks = <&wiz0_pll0_refclk>; 683 assigned-clock-parents = <&k3_clks 292 85>; 684 }; 685 686 wiz0_pll1_refclk: pll1-refclk { 687 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 688 clock-output-names = "wiz0_pll1_refclk"; 689 #clock-cells = <0>; 690 assigned-clocks = <&wiz0_pll1_refclk>; 691 assigned-clock-parents = <&k3_clks 292 85>; 692 }; 693 694 wiz0_refclk_dig: refclk-dig { 695 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 696 clock-output-names = "wiz0_refclk_dig"; 697 #clock-cells = <0>; 698 assigned-clocks = <&wiz0_refclk_dig>; 699 assigned-clock-parents = <&k3_clks 292 85>; 700 }; 701 702 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 703 clocks = <&wiz0_refclk_dig>; 704 #clock-cells = <0>; 705 }; 706 707 serdes0: serdes@5060000 { 708 compatible = "ti,j721e-serdes-10g"; 709 reg = <0x05060000 0x00010000>; 710 reg-names = "torrent_phy"; 711 resets = <&serdes_wiz0 0>; 712 reset-names = "torrent_reset"; 713 clocks = <&wiz0_pll0_refclk>; 714 clock-names = "refclk"; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 }; 718 }; 719 720 pcie1_rc: pcie@2910000 { 721 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 722 reg = <0x00 0x02910000 0x00 0x1000>, 723 <0x00 0x02917000 0x00 0x400>, 724 <0x00 0x0d800000 0x00 0x00800000>, 725 <0x00 0x18000000 0x00 0x00001000>; 726 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 727 interrupt-names = "link_state"; 728 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 729 device_type = "pci"; 730 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 731 max-link-speed = <3>; 732 num-lanes = <4>; 733 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 734 clocks = <&k3_clks 240 6>; 735 clock-names = "fck"; 736 #address-cells = <3>; 737 #size-cells = <2>; 738 bus-range = <0x0 0xff>; 739 cdns,no-bar-match-nbits = <64>; 740 vendor-id = <0x104c>; 741 device-id = <0xb00f>; 742 msi-map = <0x0 &gic_its 0x0 0x10000>; 743 dma-coherent; 744 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 745 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 746 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 747 }; 748 749 pcie1_ep: pcie-ep@2910000 { 750 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 751 reg = <0x00 0x02910000 0x00 0x1000>, 752 <0x00 0x02917000 0x00 0x400>, 753 <0x00 0x0d800000 0x00 0x00800000>, 754 <0x00 0x18000000 0x00 0x08000000>; 755 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 756 interrupt-names = "link_state"; 757 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 758 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 759 max-link-speed = <3>; 760 num-lanes = <4>; 761 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 762 clocks = <&k3_clks 240 6>; 763 clock-names = "fck"; 764 max-functions = /bits/ 8 <6>; 765 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 766 dma-coherent; 767 }; 768 769 usbss0: cdns-usb@4104000 { 770 compatible = "ti,j721e-usb"; 771 reg = <0x00 0x4104000 0x00 0x100>; 772 dma-coherent; 773 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 774 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 775 clock-names = "ref", "lpm"; 776 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 777 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges; 781 782 usb0: usb@6000000 { 783 compatible = "cdns,usb3"; 784 reg = <0x00 0x6000000 0x00 0x10000>, 785 <0x00 0x6010000 0x00 0x10000>, 786 <0x00 0x6020000 0x00 0x10000>; 787 reg-names = "otg", "xhci", "dev"; 788 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 789 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 790 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 791 interrupt-names = "host", 792 "peripheral", 793 "otg"; 794 maximum-speed = "super-speed"; 795 dr_mode = "otg"; 796 cdns,phyrst-a-enable; 797 }; 798 }; 799 800 main_gpio0: gpio@600000 { 801 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 802 reg = <0x00 0x00600000 0x00 0x100>; 803 gpio-controller; 804 #gpio-cells = <2>; 805 interrupt-parent = <&main_gpio_intr>; 806 interrupts = <145>, <146>, <147>, <148>, 807 <149>; 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 ti,ngpio = <69>; 811 ti,davinci-gpio-unbanked = <0>; 812 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 813 clocks = <&k3_clks 105 0>; 814 clock-names = "gpio"; 815 }; 816 817 main_gpio2: gpio@610000 { 818 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 819 reg = <0x00 0x00610000 0x00 0x100>; 820 gpio-controller; 821 #gpio-cells = <2>; 822 interrupt-parent = <&main_gpio_intr>; 823 interrupts = <154>, <155>, <156>, <157>, 824 <158>; 825 interrupt-controller; 826 #interrupt-cells = <2>; 827 ti,ngpio = <69>; 828 ti,davinci-gpio-unbanked = <0>; 829 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 830 clocks = <&k3_clks 107 0>; 831 clock-names = "gpio"; 832 }; 833 834 main_gpio4: gpio@620000 { 835 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 836 reg = <0x00 0x00620000 0x00 0x100>; 837 gpio-controller; 838 #gpio-cells = <2>; 839 interrupt-parent = <&main_gpio_intr>; 840 interrupts = <163>, <164>, <165>, <166>, 841 <167>; 842 interrupt-controller; 843 #interrupt-cells = <2>; 844 ti,ngpio = <69>; 845 ti,davinci-gpio-unbanked = <0>; 846 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 847 clocks = <&k3_clks 109 0>; 848 clock-names = "gpio"; 849 }; 850 851 main_gpio6: gpio@630000 { 852 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 853 reg = <0x00 0x00630000 0x00 0x100>; 854 gpio-controller; 855 #gpio-cells = <2>; 856 interrupt-parent = <&main_gpio_intr>; 857 interrupts = <172>, <173>, <174>, <175>, 858 <176>; 859 interrupt-controller; 860 #interrupt-cells = <2>; 861 ti,ngpio = <69>; 862 ti,davinci-gpio-unbanked = <0>; 863 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 864 clocks = <&k3_clks 111 0>; 865 clock-names = "gpio"; 866 }; 867 868 main_spi0: spi@2100000 { 869 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 870 reg = <0x00 0x02100000 0x00 0x400>; 871 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 875 clocks = <&k3_clks 266 1>; 876 status = "disabled"; 877 }; 878 879 main_spi1: spi@2110000 { 880 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 881 reg = <0x00 0x02110000 0x00 0x400>; 882 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 886 clocks = <&k3_clks 267 1>; 887 status = "disabled"; 888 }; 889 890 main_spi2: spi@2120000 { 891 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 892 reg = <0x00 0x02120000 0x00 0x400>; 893 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 897 clocks = <&k3_clks 268 1>; 898 status = "disabled"; 899 }; 900 901 main_spi3: spi@2130000 { 902 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 903 reg = <0x00 0x02130000 0x00 0x400>; 904 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 908 clocks = <&k3_clks 269 1>; 909 status = "disabled"; 910 }; 911 912 main_spi4: spi@2140000 { 913 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 914 reg = <0x00 0x02140000 0x00 0x400>; 915 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 919 clocks = <&k3_clks 270 1>; 920 status = "disabled"; 921 }; 922 923 main_spi5: spi@2150000 { 924 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 925 reg = <0x00 0x02150000 0x00 0x400>; 926 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&k3_clks 271 1>; 931 status = "disabled"; 932 }; 933 934 main_spi6: spi@2160000 { 935 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 936 reg = <0x00 0x02160000 0x00 0x400>; 937 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 941 clocks = <&k3_clks 272 1>; 942 status = "disabled"; 943 }; 944 945 main_spi7: spi@2170000 { 946 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 947 reg = <0x00 0x02170000 0x00 0x400>; 948 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 952 clocks = <&k3_clks 273 1>; 953 status = "disabled"; 954 }; 955 956 watchdog0: watchdog@2200000 { 957 compatible = "ti,j7-rti-wdt"; 958 reg = <0x0 0x2200000 0x0 0x100>; 959 clocks = <&k3_clks 252 1>; 960 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 961 assigned-clocks = <&k3_clks 252 1>; 962 assigned-clock-parents = <&k3_clks 252 5>; 963 }; 964 965 watchdog1: watchdog@2210000 { 966 compatible = "ti,j7-rti-wdt"; 967 reg = <0x0 0x2210000 0x0 0x100>; 968 clocks = <&k3_clks 253 1>; 969 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 970 assigned-clocks = <&k3_clks 253 1>; 971 assigned-clock-parents = <&k3_clks 253 5>; 972 }; 973 974 main_r5fss0: r5fss@5c00000 { 975 compatible = "ti,j7200-r5fss"; 976 ti,cluster-mode = <1>; 977 #address-cells = <1>; 978 #size-cells = <1>; 979 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 980 <0x5d00000 0x00 0x5d00000 0x20000>; 981 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 982 983 main_r5fss0_core0: r5f@5c00000 { 984 compatible = "ti,j7200-r5f"; 985 reg = <0x5c00000 0x00010000>, 986 <0x5c10000 0x00010000>; 987 reg-names = "atcm", "btcm"; 988 ti,sci = <&dmsc>; 989 ti,sci-dev-id = <245>; 990 ti,sci-proc-ids = <0x06 0xff>; 991 resets = <&k3_reset 245 1>; 992 firmware-name = "j7200-main-r5f0_0-fw"; 993 ti,atcm-enable = <1>; 994 ti,btcm-enable = <1>; 995 ti,loczrama = <1>; 996 }; 997 998 main_r5fss0_core1: r5f@5d00000 { 999 compatible = "ti,j7200-r5f"; 1000 reg = <0x5d00000 0x00008000>, 1001 <0x5d10000 0x00008000>; 1002 reg-names = "atcm", "btcm"; 1003 ti,sci = <&dmsc>; 1004 ti,sci-dev-id = <246>; 1005 ti,sci-proc-ids = <0x07 0xff>; 1006 resets = <&k3_reset 246 1>; 1007 firmware-name = "j7200-main-r5f0_1-fw"; 1008 ti,atcm-enable = <1>; 1009 ti,btcm-enable = <1>; 1010 ti,loczrama = <1>; 1011 }; 1012 }; 1013}; 1014