1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 30 31 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: msi-controller@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 main_gpio_intr: interrupt-controller0 { 44 compatible = "ti,sci-intr"; 45 ti,intr-trigger-type = <1>; 46 interrupt-controller; 47 interrupt-parent = <&gic500>; 48 #interrupt-cells = <1>; 49 ti,sci = <&dmsc>; 50 ti,sci-dev-id = <131>; 51 ti,interrupt-ranges = <8 392 56>; 52 }; 53 54 main_navss: bus@30000000 { 55 compatible = "simple-mfd"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 59 ti,sci-dev-id = <199>; 60 61 main_navss_intr: interrupt-controller1 { 62 compatible = "ti,sci-intr"; 63 ti,intr-trigger-type = <4>; 64 interrupt-controller; 65 interrupt-parent = <&gic500>; 66 #interrupt-cells = <1>; 67 ti,sci = <&dmsc>; 68 ti,sci-dev-id = <213>; 69 ti,interrupt-ranges = <0 64 64>, 70 <64 448 64>, 71 <128 672 64>; 72 }; 73 74 main_udmass_inta: msi-controller@33d00000 { 75 compatible = "ti,sci-inta"; 76 reg = <0x00 0x33d00000 0x00 0x100000>; 77 interrupt-controller; 78 #interrupt-cells = <0>; 79 interrupt-parent = <&main_navss_intr>; 80 msi-controller; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <209>; 83 ti,interrupt-ranges = <0 0 256>; 84 }; 85 86 secure_proxy_main: mailbox@32c00000 { 87 compatible = "ti,am654-secure-proxy"; 88 #mbox-cells = <1>; 89 reg-names = "target_data", "rt", "scfg"; 90 reg = <0x00 0x32c00000 0x00 0x100000>, 91 <0x00 0x32400000 0x00 0x100000>, 92 <0x00 0x32800000 0x00 0x100000>; 93 interrupt-names = "rx_011"; 94 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 95 }; 96 97 main_ringacc: ringacc@3c000000 { 98 compatible = "ti,am654-navss-ringacc"; 99 reg = <0x00 0x3c000000 0x00 0x400000>, 100 <0x00 0x38000000 0x00 0x400000>, 101 <0x00 0x31120000 0x00 0x100>, 102 <0x00 0x33000000 0x00 0x40000>; 103 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 104 ti,num-rings = <1024>; 105 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 106 ti,sci = <&dmsc>; 107 ti,sci-dev-id = <211>; 108 msi-parent = <&main_udmass_inta>; 109 }; 110 111 main_udmap: dma-controller@31150000 { 112 compatible = "ti,j721e-navss-main-udmap"; 113 reg = <0x00 0x31150000 0x00 0x100>, 114 <0x00 0x34000000 0x00 0x100000>, 115 <0x00 0x35000000 0x00 0x100000>; 116 reg-names = "gcfg", "rchanrt", "tchanrt"; 117 msi-parent = <&main_udmass_inta>; 118 #dma-cells = <1>; 119 120 ti,sci = <&dmsc>; 121 ti,sci-dev-id = <212>; 122 ti,ringacc = <&main_ringacc>; 123 124 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 125 <0x0f>, /* TX_HCHAN */ 126 <0x10>; /* TX_UHCHAN */ 127 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 128 <0x0b>, /* RX_HCHAN */ 129 <0x0c>; /* RX_UHCHAN */ 130 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 131 }; 132 133 cpts@310d0000 { 134 compatible = "ti,j721e-cpts"; 135 reg = <0x00 0x310d0000 0x00 0x400>; 136 reg-names = "cpts"; 137 clocks = <&k3_clks 201 1>; 138 clock-names = "cpts"; 139 interrupts-extended = <&main_navss_intr 391>; 140 interrupt-names = "cpts"; 141 ti,cpts-periodic-outputs = <6>; 142 ti,cpts-ext-ts-inputs = <8>; 143 }; 144 }; 145 146 main_pmx0: pinctrl@11c000 { 147 compatible = "pinctrl-single"; 148 /* Proxy 0 addressing */ 149 reg = <0x00 0x11c000 0x00 0x2b4>; 150 #pinctrl-cells = <1>; 151 pinctrl-single,register-width = <32>; 152 pinctrl-single,function-mask = <0xffffffff>; 153 }; 154 155 main_uart0: serial@2800000 { 156 compatible = "ti,j721e-uart", "ti,am654-uart"; 157 reg = <0x00 0x02800000 0x00 0x100>; 158 reg-shift = <2>; 159 reg-io-width = <4>; 160 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 161 clock-frequency = <48000000>; 162 current-speed = <115200>; 163 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 164 clocks = <&k3_clks 146 2>; 165 clock-names = "fclk"; 166 }; 167 168 main_uart1: serial@2810000 { 169 compatible = "ti,j721e-uart", "ti,am654-uart"; 170 reg = <0x00 0x02810000 0x00 0x100>; 171 reg-shift = <2>; 172 reg-io-width = <4>; 173 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 174 clock-frequency = <48000000>; 175 current-speed = <115200>; 176 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 177 clocks = <&k3_clks 278 2>; 178 clock-names = "fclk"; 179 }; 180 181 main_uart2: serial@2820000 { 182 compatible = "ti,j721e-uart", "ti,am654-uart"; 183 reg = <0x00 0x02820000 0x00 0x100>; 184 reg-shift = <2>; 185 reg-io-width = <4>; 186 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 187 clock-frequency = <48000000>; 188 current-speed = <115200>; 189 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 190 clocks = <&k3_clks 279 2>; 191 clock-names = "fclk"; 192 }; 193 194 main_uart3: serial@2830000 { 195 compatible = "ti,j721e-uart", "ti,am654-uart"; 196 reg = <0x00 0x02830000 0x00 0x100>; 197 reg-shift = <2>; 198 reg-io-width = <4>; 199 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 200 clock-frequency = <48000000>; 201 current-speed = <115200>; 202 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 203 clocks = <&k3_clks 280 2>; 204 clock-names = "fclk"; 205 }; 206 207 main_uart4: serial@2840000 { 208 compatible = "ti,j721e-uart", "ti,am654-uart"; 209 reg = <0x00 0x02840000 0x00 0x100>; 210 reg-shift = <2>; 211 reg-io-width = <4>; 212 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 213 clock-frequency = <48000000>; 214 current-speed = <115200>; 215 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 216 clocks = <&k3_clks 281 2>; 217 clock-names = "fclk"; 218 }; 219 220 main_uart5: serial@2850000 { 221 compatible = "ti,j721e-uart", "ti,am654-uart"; 222 reg = <0x00 0x02850000 0x00 0x100>; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 226 clock-frequency = <48000000>; 227 current-speed = <115200>; 228 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 229 clocks = <&k3_clks 282 2>; 230 clock-names = "fclk"; 231 }; 232 233 main_uart6: serial@2860000 { 234 compatible = "ti,j721e-uart", "ti,am654-uart"; 235 reg = <0x00 0x02860000 0x00 0x100>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 239 clock-frequency = <48000000>; 240 current-speed = <115200>; 241 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 242 clocks = <&k3_clks 283 2>; 243 clock-names = "fclk"; 244 }; 245 246 main_uart7: serial@2870000 { 247 compatible = "ti,j721e-uart", "ti,am654-uart"; 248 reg = <0x00 0x02870000 0x00 0x100>; 249 reg-shift = <2>; 250 reg-io-width = <4>; 251 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 252 clock-frequency = <48000000>; 253 current-speed = <115200>; 254 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 255 clocks = <&k3_clks 284 2>; 256 clock-names = "fclk"; 257 }; 258 259 main_uart8: serial@2880000 { 260 compatible = "ti,j721e-uart", "ti,am654-uart"; 261 reg = <0x00 0x02880000 0x00 0x100>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 265 clock-frequency = <48000000>; 266 current-speed = <115200>; 267 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 268 clocks = <&k3_clks 285 2>; 269 clock-names = "fclk"; 270 }; 271 272 main_uart9: serial@2890000 { 273 compatible = "ti,j721e-uart", "ti,am654-uart"; 274 reg = <0x00 0x02890000 0x00 0x100>; 275 reg-shift = <2>; 276 reg-io-width = <4>; 277 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 278 clock-frequency = <48000000>; 279 current-speed = <115200>; 280 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 281 clocks = <&k3_clks 286 2>; 282 clock-names = "fclk"; 283 }; 284 285 main_i2c0: i2c@2000000 { 286 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 287 reg = <0x00 0x2000000 0x00 0x100>; 288 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 clock-names = "fck"; 292 clocks = <&k3_clks 187 1>; 293 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 294 }; 295 296 main_i2c1: i2c@2010000 { 297 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 298 reg = <0x00 0x2010000 0x00 0x100>; 299 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 clock-names = "fck"; 303 clocks = <&k3_clks 188 1>; 304 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 305 }; 306 307 main_i2c2: i2c@2020000 { 308 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 309 reg = <0x00 0x2020000 0x00 0x100>; 310 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 clock-names = "fck"; 314 clocks = <&k3_clks 189 1>; 315 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 316 }; 317 318 main_i2c3: i2c@2030000 { 319 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 320 reg = <0x00 0x2030000 0x00 0x100>; 321 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 clock-names = "fck"; 325 clocks = <&k3_clks 190 1>; 326 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 327 }; 328 329 main_i2c4: i2c@2040000 { 330 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 331 reg = <0x00 0x2040000 0x00 0x100>; 332 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 clock-names = "fck"; 336 clocks = <&k3_clks 191 1>; 337 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 338 }; 339 340 main_i2c5: i2c@2050000 { 341 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 342 reg = <0x00 0x2050000 0x00 0x100>; 343 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clock-names = "fck"; 347 clocks = <&k3_clks 192 1>; 348 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 349 }; 350 351 main_i2c6: i2c@2060000 { 352 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 353 reg = <0x00 0x2060000 0x00 0x100>; 354 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 clock-names = "fck"; 358 clocks = <&k3_clks 193 1>; 359 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 360 }; 361 362 main_sdhci0: mmc@4f80000 { 363 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 364 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 365 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 366 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 367 clock-names = "clk_xin", "clk_ahb"; 368 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>; 369 ti,otap-del-sel-legacy = <0x0>; 370 ti,otap-del-sel-mmc-hs = <0x0>; 371 ti,otap-del-sel-ddr52 = <0x6>; 372 ti,otap-del-sel-hs200 = <0x8>; 373 ti,otap-del-sel-hs400 = <0x0>; 374 ti,strobe-sel = <0x77>; 375 ti,trm-icp = <0x8>; 376 bus-width = <8>; 377 mmc-ddr-1_8v; 378 dma-coherent; 379 }; 380 381 main_sdhci1: mmc@4fb0000 { 382 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 383 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 384 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 385 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 386 clock-names = "clk_xin", "clk_ahb"; 387 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>; 388 ti,otap-del-sel-legacy = <0x0>; 389 ti,otap-del-sel-sd-hs = <0x0>; 390 ti,otap-del-sel-sdr12 = <0xf>; 391 ti,otap-del-sel-sdr25 = <0xf>; 392 ti,otap-del-sel-sdr50 = <0xc>; 393 ti,otap-del-sel-sdr104 = <0x5>; 394 ti,otap-del-sel-ddr50 = <0xc>; 395 no-1-8-v; 396 dma-coherent; 397 }; 398}; 399