1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x100000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x100000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01900000 0x00 0x100000>; /* GICR */ 30 31 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: msi-controller@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 main_gpio_intr: interrupt-controller0 { 44 compatible = "ti,sci-intr"; 45 ti,intr-trigger-type = <1>; 46 interrupt-controller; 47 interrupt-parent = <&gic500>; 48 #interrupt-cells = <1>; 49 ti,sci = <&dmsc>; 50 ti,sci-dev-id = <131>; 51 ti,interrupt-ranges = <8 392 56>; 52 }; 53 54 main_navss: bus@30000000 { 55 compatible = "simple-mfd"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 59 ti,sci-dev-id = <199>; 60 61 main_navss_intr: interrupt-controller1 { 62 compatible = "ti,sci-intr"; 63 ti,intr-trigger-type = <4>; 64 interrupt-controller; 65 interrupt-parent = <&gic500>; 66 #interrupt-cells = <1>; 67 ti,sci = <&dmsc>; 68 ti,sci-dev-id = <213>; 69 ti,interrupt-ranges = <0 64 64>, 70 <64 448 64>, 71 <128 672 64>; 72 }; 73 74 main_udmass_inta: msi-controller@33d00000 { 75 compatible = "ti,sci-inta"; 76 reg = <0x00 0x33d00000 0x00 0x100000>; 77 interrupt-controller; 78 #interrupt-cells = <0>; 79 interrupt-parent = <&main_navss_intr>; 80 msi-controller; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <209>; 83 ti,interrupt-ranges = <0 0 256>; 84 }; 85 86 secure_proxy_main: mailbox@32c00000 { 87 compatible = "ti,am654-secure-proxy"; 88 #mbox-cells = <1>; 89 reg-names = "target_data", "rt", "scfg"; 90 reg = <0x00 0x32c00000 0x00 0x100000>, 91 <0x00 0x32400000 0x00 0x100000>, 92 <0x00 0x32800000 0x00 0x100000>; 93 interrupt-names = "rx_011"; 94 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 95 }; 96 97 main_ringacc: ringacc@3c000000 { 98 compatible = "ti,am654-navss-ringacc"; 99 reg = <0x00 0x3c000000 0x00 0x400000>, 100 <0x00 0x38000000 0x00 0x400000>, 101 <0x00 0x31120000 0x00 0x100>, 102 <0x00 0x33000000 0x00 0x40000>; 103 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 104 ti,num-rings = <1024>; 105 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 106 ti,sci = <&dmsc>; 107 ti,sci-dev-id = <211>; 108 msi-parent = <&main_udmass_inta>; 109 }; 110 111 main_udmap: dma-controller@31150000 { 112 compatible = "ti,j721e-navss-main-udmap"; 113 reg = <0x00 0x31150000 0x00 0x100>, 114 <0x00 0x34000000 0x00 0x100000>, 115 <0x00 0x35000000 0x00 0x100000>; 116 reg-names = "gcfg", "rchanrt", "tchanrt"; 117 msi-parent = <&main_udmass_inta>; 118 #dma-cells = <1>; 119 120 ti,sci = <&dmsc>; 121 ti,sci-dev-id = <212>; 122 ti,ringacc = <&main_ringacc>; 123 124 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 125 <0x0f>, /* TX_HCHAN */ 126 <0x10>; /* TX_UHCHAN */ 127 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 128 <0x0b>, /* RX_HCHAN */ 129 <0x0c>; /* RX_UHCHAN */ 130 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 131 }; 132 }; 133 134 main_pmx0: pinctrl@11c000 { 135 compatible = "pinctrl-single"; 136 /* Proxy 0 addressing */ 137 reg = <0x00 0x11c000 0x00 0x2b4>; 138 #pinctrl-cells = <1>; 139 pinctrl-single,register-width = <32>; 140 pinctrl-single,function-mask = <0xffffffff>; 141 }; 142 143 main_uart0: serial@2800000 { 144 compatible = "ti,j721e-uart", "ti,am654-uart"; 145 reg = <0x00 0x02800000 0x00 0x100>; 146 reg-shift = <2>; 147 reg-io-width = <4>; 148 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 149 clock-frequency = <48000000>; 150 current-speed = <115200>; 151 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 152 clocks = <&k3_clks 146 2>; 153 clock-names = "fclk"; 154 }; 155 156 main_uart1: serial@2810000 { 157 compatible = "ti,j721e-uart", "ti,am654-uart"; 158 reg = <0x00 0x02810000 0x00 0x100>; 159 reg-shift = <2>; 160 reg-io-width = <4>; 161 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 162 clock-frequency = <48000000>; 163 current-speed = <115200>; 164 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 165 clocks = <&k3_clks 278 2>; 166 clock-names = "fclk"; 167 }; 168 169 main_uart2: serial@2820000 { 170 compatible = "ti,j721e-uart", "ti,am654-uart"; 171 reg = <0x00 0x02820000 0x00 0x100>; 172 reg-shift = <2>; 173 reg-io-width = <4>; 174 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 175 clock-frequency = <48000000>; 176 current-speed = <115200>; 177 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 178 clocks = <&k3_clks 279 2>; 179 clock-names = "fclk"; 180 }; 181 182 main_uart3: serial@2830000 { 183 compatible = "ti,j721e-uart", "ti,am654-uart"; 184 reg = <0x00 0x02830000 0x00 0x100>; 185 reg-shift = <2>; 186 reg-io-width = <4>; 187 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 188 clock-frequency = <48000000>; 189 current-speed = <115200>; 190 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 191 clocks = <&k3_clks 280 2>; 192 clock-names = "fclk"; 193 }; 194 195 main_uart4: serial@2840000 { 196 compatible = "ti,j721e-uart", "ti,am654-uart"; 197 reg = <0x00 0x02840000 0x00 0x100>; 198 reg-shift = <2>; 199 reg-io-width = <4>; 200 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 201 clock-frequency = <48000000>; 202 current-speed = <115200>; 203 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 204 clocks = <&k3_clks 281 2>; 205 clock-names = "fclk"; 206 }; 207 208 main_uart5: serial@2850000 { 209 compatible = "ti,j721e-uart", "ti,am654-uart"; 210 reg = <0x00 0x02850000 0x00 0x100>; 211 reg-shift = <2>; 212 reg-io-width = <4>; 213 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 214 clock-frequency = <48000000>; 215 current-speed = <115200>; 216 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 217 clocks = <&k3_clks 282 2>; 218 clock-names = "fclk"; 219 }; 220 221 main_uart6: serial@2860000 { 222 compatible = "ti,j721e-uart", "ti,am654-uart"; 223 reg = <0x00 0x02860000 0x00 0x100>; 224 reg-shift = <2>; 225 reg-io-width = <4>; 226 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 227 clock-frequency = <48000000>; 228 current-speed = <115200>; 229 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 230 clocks = <&k3_clks 283 2>; 231 clock-names = "fclk"; 232 }; 233 234 main_uart7: serial@2870000 { 235 compatible = "ti,j721e-uart", "ti,am654-uart"; 236 reg = <0x00 0x02870000 0x00 0x100>; 237 reg-shift = <2>; 238 reg-io-width = <4>; 239 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 240 clock-frequency = <48000000>; 241 current-speed = <115200>; 242 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 243 clocks = <&k3_clks 284 2>; 244 clock-names = "fclk"; 245 }; 246 247 main_uart8: serial@2880000 { 248 compatible = "ti,j721e-uart", "ti,am654-uart"; 249 reg = <0x00 0x02880000 0x00 0x100>; 250 reg-shift = <2>; 251 reg-io-width = <4>; 252 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 253 clock-frequency = <48000000>; 254 current-speed = <115200>; 255 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 256 clocks = <&k3_clks 285 2>; 257 clock-names = "fclk"; 258 }; 259 260 main_uart9: serial@2890000 { 261 compatible = "ti,j721e-uart", "ti,am654-uart"; 262 reg = <0x00 0x02890000 0x00 0x100>; 263 reg-shift = <2>; 264 reg-io-width = <4>; 265 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 266 clock-frequency = <48000000>; 267 current-speed = <115200>; 268 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 269 clocks = <&k3_clks 286 2>; 270 clock-names = "fclk"; 271 }; 272}; 273