1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	chosen {
16		stdout-path = "serial2:115200n8";
17		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
18	};
19};
20
21&wkup_pmx0 {
22	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
23		pinctrl-single,pins = <
24			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
25			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
26			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
27			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
28			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
29			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
30			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
31			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
32			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
33			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
34			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
35			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
36		>;
37	};
38
39	mcu_mdio_pins_default: mcu-mdio1-pins-default {
40		pinctrl-single,pins = <
41			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
42			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
43		>;
44	};
45};
46
47&main_pmx0 {
48	main_i2c1_pins_default: main-i2c1-pins-default {
49		pinctrl-single,pins = <
50			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
51			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
52		>;
53	};
54
55	main_mmc1_pins_default: main-mmc1-pins-default {
56		pinctrl-single,pins = <
57			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
58			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
59			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
60			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
61			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
62			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
63			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
64			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
65		>;
66	};
67
68	main_usbss0_pins_default: main-usbss0-pins-default {
69		pinctrl-single,pins = <
70			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
71		>;
72	};
73};
74
75&wkup_uart0 {
76	/* Wakeup UART is used by System firmware */
77	status = "reserved";
78};
79
80&main_uart0 {
81	/* Shared with ATF on this platform */
82	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
83};
84
85&main_uart2 {
86	/* MAIN UART 2 is used by R5F firmware */
87	status = "reserved";
88};
89
90&main_uart3 {
91	/* UART not brought out */
92	status = "disabled";
93};
94
95&main_uart4 {
96	/* UART not brought out */
97	status = "disabled";
98};
99
100&main_uart5 {
101	/* UART not brought out */
102	status = "disabled";
103};
104
105&main_uart6 {
106	/* UART not brought out */
107	status = "disabled";
108};
109
110&main_uart7 {
111	/* UART not brought out */
112	status = "disabled";
113};
114
115&main_uart8 {
116	/* UART not brought out */
117	status = "disabled";
118};
119
120&main_uart9 {
121	/* UART not brought out */
122	status = "disabled";
123};
124
125&main_gpio2 {
126	status = "disabled";
127};
128
129&main_gpio4 {
130	status = "disabled";
131};
132
133&main_gpio6 {
134	status = "disabled";
135};
136
137&wkup_gpio1 {
138	status = "disabled";
139};
140
141&mcu_cpsw {
142	pinctrl-names = "default";
143	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
144};
145
146&davinci_mdio {
147	phy0: ethernet-phy@0 {
148		reg = <0>;
149		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
150		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
151	};
152};
153
154&cpsw_port1 {
155	phy-mode = "rgmii-rxid";
156	phy-handle = <&phy0>;
157};
158
159&main_i2c0 {
160	exp1: gpio@20 {
161		compatible = "ti,tca6416";
162		reg = <0x20>;
163		gpio-controller;
164		#gpio-cells = <2>;
165	};
166
167	exp2: gpio@22 {
168		compatible = "ti,tca6424";
169		reg = <0x22>;
170		gpio-controller;
171		#gpio-cells = <2>;
172	};
173};
174
175/*
176 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
177 * swapped on the CPB.
178 *
179 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
180 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
181 */
182&main_i2c1 {
183	pinctrl-names = "default";
184	pinctrl-0 = <&main_i2c1_pins_default>;
185	clock-frequency = <400000>;
186
187	exp3: gpio@20 {
188		compatible = "ti,tca6408";
189		reg = <0x20>;
190		gpio-controller;
191		#gpio-cells = <2>;
192		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
193				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
194				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
195	};
196};
197
198&main_sdhci0 {
199	/* eMMC */
200	non-removable;
201	ti,driver-strength-ohm = <50>;
202	disable-wp;
203};
204
205&main_sdhci1 {
206	/* SD card */
207	pinctrl-0 = <&main_mmc1_pins_default>;
208	pinctrl-names = "default";
209	ti,driver-strength-ohm = <50>;
210	disable-wp;
211};
212
213&serdes_ln_ctrl {
214	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
215		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
216};
217
218&usb_serdes_mux {
219	idle-states = <1>; /* USB0 to SERDES lane 3 */
220};
221
222&usbss0 {
223	pinctrl-names = "default";
224	pinctrl-0 = <&main_usbss0_pins_default>;
225	ti,vbus-divider;
226	ti,usb2-only;
227};
228
229&usb0 {
230	dr_mode = "otg";
231	maximum-speed = "high-speed";
232};
233
234&tscadc0 {
235	adc {
236		ti,adc-channels = <0 1 2 3 4 5 6 7>;
237	};
238};
239
240&serdes_refclk {
241	clock-frequency = <100000000>;
242};
243
244&serdes0 {
245	serdes0_pcie_link: phy@0 {
246		reg = <0>;
247		cdns,num-lanes = <2>;
248		#phy-cells = <0>;
249		cdns,phy-type = <PHY_TYPE_PCIE>;
250		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
251	};
252
253	serdes0_qsgmii_link: phy@1 {
254		reg = <2>;
255		cdns,num-lanes = <1>;
256		#phy-cells = <0>;
257		cdns,phy-type = <PHY_TYPE_QSGMII>;
258		resets = <&serdes_wiz0 3>;
259	};
260};
261
262&pcie1_rc {
263	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
264	phys = <&serdes0_pcie_link>;
265	phy-names = "pcie-phy";
266	num-lanes = <2>;
267};
268
269&pcie1_ep {
270	phys = <&serdes0_pcie_link>;
271	phy-names = "pcie-phy";
272	num-lanes = <2>;
273	status = "disabled";
274};
275