1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy.h> 12 13#include "k3-serdes.h" 14 15/ { 16 compatible = "ti,j7200-evm", "ti,j7200"; 17 model = "Texas Instruments J7200 EVM"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 serial5 = &main_uart3; 25 mmc0 = &main_sdhci0; 26 mmc1 = &main_sdhci1; 27 }; 28 29 chosen { 30 stdout-path = "serial2:115200n8"; 31 }; 32 33 evm_12v0: fixedregulator-evm12v0 { 34 /* main supply */ 35 compatible = "regulator-fixed"; 36 regulator-name = "evm_12v0"; 37 regulator-min-microvolt = <12000000>; 38 regulator-max-microvolt = <12000000>; 39 regulator-always-on; 40 regulator-boot-on; 41 }; 42 43 vsys_3v3: fixedregulator-vsys3v3 { 44 /* Output of LM5140 */ 45 compatible = "regulator-fixed"; 46 regulator-name = "vsys_3v3"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 vin-supply = <&evm_12v0>; 50 regulator-always-on; 51 regulator-boot-on; 52 }; 53 54 vsys_5v0: fixedregulator-vsys5v0 { 55 /* Output of LM5140 */ 56 compatible = "regulator-fixed"; 57 regulator-name = "vsys_5v0"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 vin-supply = <&evm_12v0>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 vdd_mmc1: fixedregulator-sd { 66 /* Output of TPS22918 */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vdd_mmc1"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 regulator-boot-on; 72 enable-active-high; 73 vin-supply = <&vsys_3v3>; 74 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 75 }; 76 77 vdd_sd_dv: gpio-regulator-TLV71033 { 78 /* Output of TLV71033 */ 79 compatible = "regulator-gpio"; 80 regulator-name = "tlv71033"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&vdd_sd_dv_pins_default>; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 vin-supply = <&vsys_5v0>; 87 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 88 states = <1800000 0x0>, 89 <3300000 0x1>; 90 }; 91}; 92 93&wkup_pmx0 { 94}; 95 96&wkup_pmx2 { 97 mcu_uart0_pins_default: mcu-uart0-default-pins { 98 pinctrl-single,pins = < 99 J721E_WKUP_IOPAD(0x90, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ 100 J721E_WKUP_IOPAD(0x94, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ 101 J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ 102 J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ 103 >; 104 }; 105 106 wkup_uart0_pins_default: wkup-uart0-default-pins { 107 pinctrl-single,pins = < 108 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 109 J721E_WKUP_IOPAD(0x4c, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 110 >; 111 }; 112 113 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 114 pinctrl-single,pins = < 115 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 116 J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 117 J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 118 J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 119 J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 120 J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 121 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 122 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 123 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 124 J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 125 J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 126 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 127 >; 128 }; 129 130 wkup_gpio_pins_default: wkup-gpio-default-pins { 131 pinctrl-single,pins = < 132 J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 133 >; 134 }; 135 136 mcu_mdio_pins_default: mcu-mdio1-default-pins { 137 pinctrl-single,pins = < 138 J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 139 J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 140 >; 141 }; 142}; 143 144&main_pmx0 { 145 main_uart0_pins_default: main-uart0-default-pins { 146 pinctrl-single,pins = < 147 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 148 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 149 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 150 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 151 >; 152 }; 153 154 main_uart1_pins_default: main-uart1-default-pins { 155 pinctrl-single,pins = < 156 J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ 157 J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ 158 >; 159 }; 160 161 main_uart3_pins_default: main-uart3-default-pins { 162 pinctrl-single,pins = < 163 J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ 164 J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ 165 >; 166 }; 167 168 main_i2c1_pins_default: main-i2c1-default-pins { 169 pinctrl-single,pins = < 170 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 171 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 172 >; 173 }; 174 175 main_mmc1_pins_default: main-mmc1-default-pins { 176 pinctrl-single,pins = < 177 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 178 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 179 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 180 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 181 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 182 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 183 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 184 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 185 >; 186 }; 187 188 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 189 pinctrl-single,pins = < 190 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 191 >; 192 }; 193}; 194 195&main_pmx1 { 196 main_usbss0_pins_default: main-usbss0-default-pins { 197 pinctrl-single,pins = < 198 J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 199 >; 200 }; 201}; 202 203&wkup_uart0 { 204 /* Wakeup UART is used by System firmware */ 205 status = "reserved"; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&wkup_uart0_pins_default>; 208}; 209 210&mcu_uart0 { 211 status = "okay"; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&mcu_uart0_pins_default>; 214 clock-frequency = <96000000>; 215}; 216 217&main_uart0 { 218 status = "okay"; 219 /* Shared with ATF on this platform */ 220 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&main_uart0_pins_default>; 223}; 224 225&main_uart1 { 226 status = "okay"; 227 /* Default pinmux */ 228 pinctrl-names = "default"; 229 pinctrl-0 = <&main_uart1_pins_default>; 230}; 231 232&main_uart2 { 233 /* MAIN UART 2 is used by R5F firmware */ 234 status = "reserved"; 235}; 236 237&main_uart3 { 238 /* Shared with MCAN Interface */ 239 status = "okay"; 240 pinctrl-names = "default"; 241 pinctrl-0 = <&main_uart3_pins_default>; 242}; 243 244&main_gpio0 { 245 status = "okay"; 246}; 247 248&wkup_gpio0 { 249 status = "okay"; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&wkup_gpio_pins_default>; 252}; 253 254&mcu_cpsw { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 257}; 258 259&davinci_mdio { 260 phy0: ethernet-phy@0 { 261 reg = <0>; 262 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 263 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 264 }; 265}; 266 267&cpsw_port1 { 268 phy-mode = "rgmii-rxid"; 269 phy-handle = <&phy0>; 270}; 271 272&main_i2c0 { 273 status = "okay"; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&main_i2c0_pins_default>; 276 clock-frequency = <400000>; 277 278 exp1: gpio@20 { 279 compatible = "ti,tca6416"; 280 reg = <0x20>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 }; 284 285 exp2: gpio@22 { 286 compatible = "ti,tca6424"; 287 reg = <0x22>; 288 gpio-controller; 289 #gpio-cells = <2>; 290 }; 291}; 292 293/* 294 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 295 * swapped on the CPB. 296 * 297 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 298 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 299 */ 300&main_i2c1 { 301 status = "okay"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&main_i2c1_pins_default>; 304 clock-frequency = <400000>; 305 306 exp3: gpio@20 { 307 compatible = "ti,tca6408"; 308 reg = <0x20>; 309 gpio-controller; 310 #gpio-cells = <2>; 311 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 312 "UB926_LOCK", "UB926_PWR_SW_CNTRL", 313 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 314 }; 315}; 316 317&main_sdhci0 { 318 /* eMMC */ 319 status = "okay"; 320 non-removable; 321 ti,driver-strength-ohm = <50>; 322 disable-wp; 323}; 324 325&main_sdhci1 { 326 /* SD card */ 327 status = "okay"; 328 pinctrl-0 = <&main_mmc1_pins_default>; 329 pinctrl-names = "default"; 330 vmmc-supply = <&vdd_mmc1>; 331 vqmmc-supply = <&vdd_sd_dv>; 332 ti,driver-strength-ohm = <50>; 333 disable-wp; 334}; 335 336&serdes_ln_ctrl { 337 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 338 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 339}; 340 341&usb_serdes_mux { 342 idle-states = <1>; /* USB0 to SERDES lane 3 */ 343}; 344 345&usbss0 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&main_usbss0_pins_default>; 348 ti,vbus-divider; 349 ti,usb2-only; 350}; 351 352&usb0 { 353 dr_mode = "otg"; 354 maximum-speed = "high-speed"; 355}; 356 357&tscadc0 { 358 adc { 359 ti,adc-channels = <0 1 2 3 4 5 6 7>; 360 }; 361}; 362 363&serdes_refclk { 364 clock-frequency = <100000000>; 365}; 366 367&serdes0 { 368 serdes0_pcie_link: phy@0 { 369 reg = <0>; 370 cdns,num-lanes = <2>; 371 #phy-cells = <0>; 372 cdns,phy-type = <PHY_TYPE_PCIE>; 373 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 374 }; 375 376 serdes0_qsgmii_link: phy@1 { 377 reg = <2>; 378 cdns,num-lanes = <1>; 379 #phy-cells = <0>; 380 cdns,phy-type = <PHY_TYPE_QSGMII>; 381 resets = <&serdes_wiz0 3>; 382 }; 383}; 384 385&pcie1_rc { 386 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 387 phys = <&serdes0_pcie_link>; 388 phy-names = "pcie-phy"; 389 num-lanes = <2>; 390}; 391 392&pcie1_ep { 393 phys = <&serdes0_pcie_link>; 394 phy-names = "pcie-phy"; 395 num-lanes = <2>; 396 status = "disabled"; 397}; 398