1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/mux/ti-serdes.h> 12#include <dt-bindings/phy/phy.h> 13 14/ { 15 compatible = "ti,j7200-evm", "ti,j7200"; 16 model = "Texas Instruments J7200 EVM"; 17 18 aliases { 19 serial0 = &wkup_uart0; 20 serial1 = &mcu_uart0; 21 serial2 = &main_uart0; 22 serial3 = &main_uart1; 23 serial5 = &main_uart3; 24 mmc0 = &main_sdhci0; 25 mmc1 = &main_sdhci1; 26 }; 27 28 chosen { 29 stdout-path = "serial2:115200n8"; 30 }; 31 32 evm_12v0: fixedregulator-evm12v0 { 33 /* main supply */ 34 compatible = "regulator-fixed"; 35 regulator-name = "evm_12v0"; 36 regulator-min-microvolt = <12000000>; 37 regulator-max-microvolt = <12000000>; 38 regulator-always-on; 39 regulator-boot-on; 40 }; 41 42 vsys_3v3: fixedregulator-vsys3v3 { 43 /* Output of LM5140 */ 44 compatible = "regulator-fixed"; 45 regulator-name = "vsys_3v3"; 46 regulator-min-microvolt = <3300000>; 47 regulator-max-microvolt = <3300000>; 48 vin-supply = <&evm_12v0>; 49 regulator-always-on; 50 regulator-boot-on; 51 }; 52 53 vsys_5v0: fixedregulator-vsys5v0 { 54 /* Output of LM5140 */ 55 compatible = "regulator-fixed"; 56 regulator-name = "vsys_5v0"; 57 regulator-min-microvolt = <5000000>; 58 regulator-max-microvolt = <5000000>; 59 vin-supply = <&evm_12v0>; 60 regulator-always-on; 61 regulator-boot-on; 62 }; 63 64 vdd_mmc1: fixedregulator-sd { 65 /* Output of TPS22918 */ 66 compatible = "regulator-fixed"; 67 regulator-name = "vdd_mmc1"; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 regulator-boot-on; 71 enable-active-high; 72 vin-supply = <&vsys_3v3>; 73 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 74 }; 75 76 vdd_sd_dv: gpio-regulator-TLV71033 { 77 /* Output of TLV71033 */ 78 compatible = "regulator-gpio"; 79 regulator-name = "tlv71033"; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&vdd_sd_dv_pins_default>; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <3300000>; 84 regulator-boot-on; 85 vin-supply = <&vsys_5v0>; 86 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 87 states = <1800000 0x0>, 88 <3300000 0x1>; 89 }; 90}; 91 92&wkup_pmx0 { 93 mcu_uart0_pins_default: mcu-uart0-pins-default { 94 pinctrl-single,pins = < 95 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ 96 J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ 97 J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ 98 J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ 99 >; 100 }; 101 102 wkup_uart0_pins_default: wkup-uart0-pins-default { 103 pinctrl-single,pins = < 104 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 105 J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 106 >; 107 }; 108}; 109 110&wkup_pmx2 { 111 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 112 pinctrl-single,pins = < 113 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 114 J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 115 J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 116 J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 117 J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 118 J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 119 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 120 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 121 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 122 J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 123 J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 124 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 125 >; 126 }; 127 128 wkup_gpio_pins_default: wkup-gpio-pins-default { 129 pinctrl-single,pins = < 130 J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 131 >; 132 }; 133 134 mcu_mdio_pins_default: mcu-mdio1-pins-default { 135 pinctrl-single,pins = < 136 J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 137 J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 138 >; 139 }; 140}; 141 142&main_pmx0 { 143 main_uart0_pins_default: main-uart0-pins-default { 144 pinctrl-single,pins = < 145 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 146 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 147 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 148 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 149 >; 150 }; 151 152 main_uart1_pins_default: main-uart1-pins-default { 153 pinctrl-single,pins = < 154 J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ 155 J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ 156 >; 157 }; 158 159 main_uart3_pins_default: main-uart3-pins-default { 160 pinctrl-single,pins = < 161 J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ 162 J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ 163 >; 164 }; 165 166 main_i2c1_pins_default: main-i2c1-pins-default { 167 pinctrl-single,pins = < 168 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 169 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 170 >; 171 }; 172 173 main_mmc1_pins_default: main-mmc1-pins-default { 174 pinctrl-single,pins = < 175 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 176 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 177 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 178 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 179 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 180 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 181 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 182 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 183 >; 184 }; 185 186 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 187 pinctrl-single,pins = < 188 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 189 >; 190 }; 191}; 192 193&main_pmx1 { 194 main_usbss0_pins_default: main-usbss0-pins-default { 195 pinctrl-single,pins = < 196 J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 197 >; 198 }; 199}; 200 201&wkup_uart0 { 202 /* Wakeup UART is used by System firmware */ 203 status = "reserved"; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&wkup_uart0_pins_default>; 206}; 207 208&mcu_uart0 { 209 status = "okay"; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&mcu_uart0_pins_default>; 212 clock-frequency = <96000000>; 213}; 214 215&main_uart0 { 216 status = "okay"; 217 /* Shared with ATF on this platform */ 218 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&main_uart0_pins_default>; 221}; 222 223&main_uart1 { 224 status = "okay"; 225 /* Default pinmux */ 226 pinctrl-names = "default"; 227 pinctrl-0 = <&main_uart1_pins_default>; 228}; 229 230&main_uart2 { 231 /* MAIN UART 2 is used by R5F firmware */ 232 status = "reserved"; 233}; 234 235&main_uart3 { 236 /* Shared with MCAN Interface */ 237 status = "okay"; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&main_uart3_pins_default>; 240}; 241 242&main_gpio2 { 243 status = "disabled"; 244}; 245 246&main_gpio4 { 247 status = "disabled"; 248}; 249 250&main_gpio6 { 251 status = "disabled"; 252}; 253 254&wkup_gpio0 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&wkup_gpio_pins_default>; 257}; 258 259&wkup_gpio1 { 260 status = "disabled"; 261}; 262 263&mcu_cpsw { 264 pinctrl-names = "default"; 265 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 266}; 267 268&davinci_mdio { 269 phy0: ethernet-phy@0 { 270 reg = <0>; 271 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 272 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 273 }; 274}; 275 276&cpsw_port1 { 277 phy-mode = "rgmii-rxid"; 278 phy-handle = <&phy0>; 279}; 280 281&main_i2c0 { 282 status = "okay"; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&main_i2c0_pins_default>; 285 clock-frequency = <400000>; 286 287 exp1: gpio@20 { 288 compatible = "ti,tca6416"; 289 reg = <0x20>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 }; 293 294 exp2: gpio@22 { 295 compatible = "ti,tca6424"; 296 reg = <0x22>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 }; 300}; 301 302/* 303 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 304 * swapped on the CPB. 305 * 306 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 307 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 308 */ 309&main_i2c1 { 310 status = "okay"; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&main_i2c1_pins_default>; 313 clock-frequency = <400000>; 314 315 exp3: gpio@20 { 316 compatible = "ti,tca6408"; 317 reg = <0x20>; 318 gpio-controller; 319 #gpio-cells = <2>; 320 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 321 "UB926_LOCK", "UB926_PWR_SW_CNTRL", 322 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 323 }; 324}; 325 326&main_sdhci0 { 327 /* eMMC */ 328 non-removable; 329 ti,driver-strength-ohm = <50>; 330 disable-wp; 331}; 332 333&main_sdhci1 { 334 /* SD card */ 335 pinctrl-0 = <&main_mmc1_pins_default>; 336 pinctrl-names = "default"; 337 vmmc-supply = <&vdd_mmc1>; 338 vqmmc-supply = <&vdd_sd_dv>; 339 ti,driver-strength-ohm = <50>; 340 disable-wp; 341}; 342 343&serdes_ln_ctrl { 344 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 345 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 346}; 347 348&usb_serdes_mux { 349 idle-states = <1>; /* USB0 to SERDES lane 3 */ 350}; 351 352&usbss0 { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&main_usbss0_pins_default>; 355 ti,vbus-divider; 356 ti,usb2-only; 357}; 358 359&usb0 { 360 dr_mode = "otg"; 361 maximum-speed = "high-speed"; 362}; 363 364&tscadc0 { 365 adc { 366 ti,adc-channels = <0 1 2 3 4 5 6 7>; 367 }; 368}; 369 370&serdes_refclk { 371 clock-frequency = <100000000>; 372}; 373 374&serdes0 { 375 serdes0_pcie_link: phy@0 { 376 reg = <0>; 377 cdns,num-lanes = <2>; 378 #phy-cells = <0>; 379 cdns,phy-type = <PHY_TYPE_PCIE>; 380 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 381 }; 382 383 serdes0_qsgmii_link: phy@1 { 384 reg = <2>; 385 cdns,num-lanes = <1>; 386 #phy-cells = <0>; 387 cdns,phy-type = <PHY_TYPE_QSGMII>; 388 resets = <&serdes_wiz0 3>; 389 }; 390}; 391 392&pcie1_rc { 393 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 394 phys = <&serdes0_pcie_link>; 395 phy-names = "pcie-phy"; 396 num-lanes = <2>; 397}; 398 399&pcie1_ep { 400 phys = <&serdes0_pcie_link>; 401 phy-names = "pcie-phy"; 402 num-lanes = <2>; 403 status = "disabled"; 404}; 405