1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	compatible = "ti,j7200-evm", "ti,j7200";
16	model = "Texas Instruments J7200 EVM";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20	};
21
22	evm_12v0: fixedregulator-evm12v0 {
23		/* main supply */
24		compatible = "regulator-fixed";
25		regulator-name = "evm_12v0";
26		regulator-min-microvolt = <12000000>;
27		regulator-max-microvolt = <12000000>;
28		regulator-always-on;
29		regulator-boot-on;
30	};
31
32	vsys_3v3: fixedregulator-vsys3v3 {
33		/* Output of LM5140 */
34		compatible = "regulator-fixed";
35		regulator-name = "vsys_3v3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		vin-supply = <&evm_12v0>;
39		regulator-always-on;
40		regulator-boot-on;
41	};
42
43	vsys_5v0: fixedregulator-vsys5v0 {
44		/* Output of LM5140 */
45		compatible = "regulator-fixed";
46		regulator-name = "vsys_5v0";
47		regulator-min-microvolt = <5000000>;
48		regulator-max-microvolt = <5000000>;
49		vin-supply = <&evm_12v0>;
50		regulator-always-on;
51		regulator-boot-on;
52	};
53
54	vdd_mmc1: fixedregulator-sd {
55		/* Output of TPS22918 */
56		compatible = "regulator-fixed";
57		regulator-name = "vdd_mmc1";
58		regulator-min-microvolt = <3300000>;
59		regulator-max-microvolt = <3300000>;
60		regulator-boot-on;
61		enable-active-high;
62		vin-supply = <&vsys_3v3>;
63		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
64	};
65
66	vdd_sd_dv: gpio-regulator-TLV71033 {
67		/* Output of TLV71033 */
68		compatible = "regulator-gpio";
69		regulator-name = "tlv71033";
70		pinctrl-names = "default";
71		pinctrl-0 = <&vdd_sd_dv_pins_default>;
72		regulator-min-microvolt = <1800000>;
73		regulator-max-microvolt = <3300000>;
74		regulator-boot-on;
75		vin-supply = <&vsys_5v0>;
76		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
77		states = <1800000 0x0>,
78			 <3300000 0x1>;
79	};
80};
81
82&wkup_pmx2 {
83	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
84		pinctrl-single,pins = <
85			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
86			J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
87			J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
88			J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
89			J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
90			J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
91			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
92			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
93			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
94			J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
95			J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
96			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
97		>;
98	};
99
100	wkup_gpio_pins_default: wkup-gpio-pins-default {
101		pinctrl-single,pins = <
102			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
103		>;
104	};
105
106	mcu_mdio_pins_default: mcu-mdio1-pins-default {
107		pinctrl-single,pins = <
108			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
109			J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
110		>;
111	};
112};
113
114&main_pmx0 {
115	main_i2c0_pins_default: main-i2c0-pins-default {
116		pinctrl-single,pins = <
117			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
118			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
119		>;
120	};
121
122	main_i2c1_pins_default: main-i2c1-pins-default {
123		pinctrl-single,pins = <
124			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
125			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
126		>;
127	};
128
129	main_mmc1_pins_default: main-mmc1-pins-default {
130		pinctrl-single,pins = <
131			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
132			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
133			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
134			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
135			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
136			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
137			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
138			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
139		>;
140	};
141
142	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
143		pinctrl-single,pins = <
144			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
145		>;
146	};
147};
148
149&main_pmx1 {
150	main_usbss0_pins_default: main-usbss0-pins-default {
151		pinctrl-single,pins = <
152			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
153		>;
154	};
155};
156
157&wkup_uart0 {
158	/* Wakeup UART is used by System firmware */
159	status = "reserved";
160};
161
162&mcu_uart0 {
163	status = "okay";
164	/* Default pinmux */
165};
166
167&main_uart0 {
168	status = "okay";
169	/* Shared with ATF on this platform */
170	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
171};
172
173&main_uart1 {
174	status = "okay";
175	/* Default pinmux */
176};
177
178&main_uart2 {
179	/* MAIN UART 2 is used by R5F firmware */
180	status = "reserved";
181};
182
183&main_gpio2 {
184	status = "disabled";
185};
186
187&main_gpio4 {
188	status = "disabled";
189};
190
191&main_gpio6 {
192	status = "disabled";
193};
194
195&wkup_gpio0 {
196	pinctrl-names = "default";
197	pinctrl-0 = <&wkup_gpio_pins_default>;
198};
199
200&wkup_gpio1 {
201	status = "disabled";
202};
203
204&mcu_cpsw {
205	pinctrl-names = "default";
206	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
207};
208
209&davinci_mdio {
210	phy0: ethernet-phy@0 {
211		reg = <0>;
212		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
213		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
214	};
215};
216
217&cpsw_port1 {
218	phy-mode = "rgmii-rxid";
219	phy-handle = <&phy0>;
220};
221
222&main_i2c0 {
223	status = "okay";
224	pinctrl-names = "default";
225	pinctrl-0 = <&main_i2c0_pins_default>;
226	clock-frequency = <400000>;
227
228	exp1: gpio@20 {
229		compatible = "ti,tca6416";
230		reg = <0x20>;
231		gpio-controller;
232		#gpio-cells = <2>;
233	};
234
235	exp2: gpio@22 {
236		compatible = "ti,tca6424";
237		reg = <0x22>;
238		gpio-controller;
239		#gpio-cells = <2>;
240	};
241};
242
243/*
244 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
245 * swapped on the CPB.
246 *
247 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
248 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
249 */
250&main_i2c1 {
251	status = "okay";
252	pinctrl-names = "default";
253	pinctrl-0 = <&main_i2c1_pins_default>;
254	clock-frequency = <400000>;
255
256	exp3: gpio@20 {
257		compatible = "ti,tca6408";
258		reg = <0x20>;
259		gpio-controller;
260		#gpio-cells = <2>;
261		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
262				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
263				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
264	};
265};
266
267&main_sdhci0 {
268	/* eMMC */
269	non-removable;
270	ti,driver-strength-ohm = <50>;
271	disable-wp;
272};
273
274&main_sdhci1 {
275	/* SD card */
276	pinctrl-0 = <&main_mmc1_pins_default>;
277	pinctrl-names = "default";
278	vmmc-supply = <&vdd_mmc1>;
279	vqmmc-supply = <&vdd_sd_dv>;
280	ti,driver-strength-ohm = <50>;
281	disable-wp;
282};
283
284&serdes_ln_ctrl {
285	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
286		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
287};
288
289&usb_serdes_mux {
290	idle-states = <1>; /* USB0 to SERDES lane 3 */
291};
292
293&usbss0 {
294	pinctrl-names = "default";
295	pinctrl-0 = <&main_usbss0_pins_default>;
296	ti,vbus-divider;
297	ti,usb2-only;
298};
299
300&usb0 {
301	dr_mode = "otg";
302	maximum-speed = "high-speed";
303};
304
305&tscadc0 {
306	adc {
307		ti,adc-channels = <0 1 2 3 4 5 6 7>;
308	};
309};
310
311&serdes_refclk {
312	clock-frequency = <100000000>;
313};
314
315&serdes0 {
316	serdes0_pcie_link: phy@0 {
317		reg = <0>;
318		cdns,num-lanes = <2>;
319		#phy-cells = <0>;
320		cdns,phy-type = <PHY_TYPE_PCIE>;
321		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
322	};
323
324	serdes0_qsgmii_link: phy@1 {
325		reg = <2>;
326		cdns,num-lanes = <1>;
327		#phy-cells = <0>;
328		cdns,phy-type = <PHY_TYPE_QSGMII>;
329		resets = <&serdes_wiz0 3>;
330	};
331};
332
333&pcie1_rc {
334	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
335	phys = <&serdes0_pcie_link>;
336	phy-names = "pcie-phy";
337	num-lanes = <2>;
338};
339
340&pcie1_ep {
341	phys = <&serdes0_pcie_link>;
342	phy-names = "pcie-phy";
343	num-lanes = <2>;
344	status = "disabled";
345};
346