1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	compatible = "ti,j7200-evm", "ti,j7200";
16	model = "Texas Instruments J7200 EVM";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20	};
21
22	evm_12v0: fixedregulator-evm12v0 {
23		/* main supply */
24		compatible = "regulator-fixed";
25		regulator-name = "evm_12v0";
26		regulator-min-microvolt = <12000000>;
27		regulator-max-microvolt = <12000000>;
28		regulator-always-on;
29		regulator-boot-on;
30	};
31
32	vsys_3v3: fixedregulator-vsys3v3 {
33		/* Output of LM5140 */
34		compatible = "regulator-fixed";
35		regulator-name = "vsys_3v3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		vin-supply = <&evm_12v0>;
39		regulator-always-on;
40		regulator-boot-on;
41	};
42
43	vsys_5v0: fixedregulator-vsys5v0 {
44		/* Output of LM5140 */
45		compatible = "regulator-fixed";
46		regulator-name = "vsys_5v0";
47		regulator-min-microvolt = <5000000>;
48		regulator-max-microvolt = <5000000>;
49		vin-supply = <&evm_12v0>;
50		regulator-always-on;
51		regulator-boot-on;
52	};
53
54	vdd_mmc1: fixedregulator-sd {
55		/* Output of TPS22918 */
56		compatible = "regulator-fixed";
57		regulator-name = "vdd_mmc1";
58		regulator-min-microvolt = <3300000>;
59		regulator-max-microvolt = <3300000>;
60		regulator-boot-on;
61		enable-active-high;
62		vin-supply = <&vsys_3v3>;
63		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
64	};
65
66	vdd_sd_dv: gpio-regulator-TLV71033 {
67		/* Output of TLV71033 */
68		compatible = "regulator-gpio";
69		regulator-name = "tlv71033";
70		pinctrl-names = "default";
71		pinctrl-0 = <&vdd_sd_dv_pins_default>;
72		regulator-min-microvolt = <1800000>;
73		regulator-max-microvolt = <3300000>;
74		regulator-boot-on;
75		vin-supply = <&vsys_5v0>;
76		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
77		states = <1800000 0x0>,
78			 <3300000 0x1>;
79	};
80};
81
82&wkup_pmx2 {
83	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
84		pinctrl-single,pins = <
85			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
86			J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
87			J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
88			J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
89			J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
90			J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
91			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
92			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
93			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
94			J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
95			J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
96			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
97		>;
98	};
99
100	wkup_gpio_pins_default: wkup-gpio-pins-default {
101		pinctrl-single,pins = <
102			J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
103		>;
104	};
105
106	mcu_mdio_pins_default: mcu-mdio1-pins-default {
107		pinctrl-single,pins = <
108			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
109			J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
110		>;
111	};
112};
113
114&main_pmx0 {
115	main_i2c1_pins_default: main-i2c1-pins-default {
116		pinctrl-single,pins = <
117			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
118			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
119		>;
120	};
121
122	main_mmc1_pins_default: main-mmc1-pins-default {
123		pinctrl-single,pins = <
124			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
125			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
126			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
127			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
128			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
129			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
130			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
131			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
132		>;
133	};
134
135	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
136		pinctrl-single,pins = <
137			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
138		>;
139	};
140};
141
142&main_pmx1 {
143	main_usbss0_pins_default: main-usbss0-pins-default {
144		pinctrl-single,pins = <
145			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
146		>;
147	};
148};
149
150&wkup_uart0 {
151	/* Wakeup UART is used by System firmware */
152	status = "reserved";
153};
154
155&mcu_uart0 {
156	status = "okay";
157	/* Default pinmux */
158};
159
160&main_uart0 {
161	status = "okay";
162	/* Shared with ATF on this platform */
163	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
164};
165
166&main_uart1 {
167	status = "okay";
168	/* Default pinmux */
169};
170
171&main_uart2 {
172	/* MAIN UART 2 is used by R5F firmware */
173	status = "reserved";
174};
175
176&main_gpio2 {
177	status = "disabled";
178};
179
180&main_gpio4 {
181	status = "disabled";
182};
183
184&main_gpio6 {
185	status = "disabled";
186};
187
188&wkup_gpio0 {
189	pinctrl-names = "default";
190	pinctrl-0 = <&wkup_gpio_pins_default>;
191};
192
193&wkup_gpio1 {
194	status = "disabled";
195};
196
197&mcu_cpsw {
198	pinctrl-names = "default";
199	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
200};
201
202&davinci_mdio {
203	phy0: ethernet-phy@0 {
204		reg = <0>;
205		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
206		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
207	};
208};
209
210&cpsw_port1 {
211	phy-mode = "rgmii-rxid";
212	phy-handle = <&phy0>;
213};
214
215&main_i2c0 {
216	status = "okay";
217	pinctrl-names = "default";
218	pinctrl-0 = <&main_i2c0_pins_default>;
219	clock-frequency = <400000>;
220
221	exp1: gpio@20 {
222		compatible = "ti,tca6416";
223		reg = <0x20>;
224		gpio-controller;
225		#gpio-cells = <2>;
226	};
227
228	exp2: gpio@22 {
229		compatible = "ti,tca6424";
230		reg = <0x22>;
231		gpio-controller;
232		#gpio-cells = <2>;
233	};
234};
235
236/*
237 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
238 * swapped on the CPB.
239 *
240 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
241 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
242 */
243&main_i2c1 {
244	status = "okay";
245	pinctrl-names = "default";
246	pinctrl-0 = <&main_i2c1_pins_default>;
247	clock-frequency = <400000>;
248
249	exp3: gpio@20 {
250		compatible = "ti,tca6408";
251		reg = <0x20>;
252		gpio-controller;
253		#gpio-cells = <2>;
254		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
255				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
256				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
257	};
258};
259
260&main_sdhci0 {
261	/* eMMC */
262	non-removable;
263	ti,driver-strength-ohm = <50>;
264	disable-wp;
265};
266
267&main_sdhci1 {
268	/* SD card */
269	pinctrl-0 = <&main_mmc1_pins_default>;
270	pinctrl-names = "default";
271	vmmc-supply = <&vdd_mmc1>;
272	vqmmc-supply = <&vdd_sd_dv>;
273	ti,driver-strength-ohm = <50>;
274	disable-wp;
275};
276
277&serdes_ln_ctrl {
278	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
279		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
280};
281
282&usb_serdes_mux {
283	idle-states = <1>; /* USB0 to SERDES lane 3 */
284};
285
286&usbss0 {
287	pinctrl-names = "default";
288	pinctrl-0 = <&main_usbss0_pins_default>;
289	ti,vbus-divider;
290	ti,usb2-only;
291};
292
293&usb0 {
294	dr_mode = "otg";
295	maximum-speed = "high-speed";
296};
297
298&tscadc0 {
299	adc {
300		ti,adc-channels = <0 1 2 3 4 5 6 7>;
301	};
302};
303
304&serdes_refclk {
305	clock-frequency = <100000000>;
306};
307
308&serdes0 {
309	serdes0_pcie_link: phy@0 {
310		reg = <0>;
311		cdns,num-lanes = <2>;
312		#phy-cells = <0>;
313		cdns,phy-type = <PHY_TYPE_PCIE>;
314		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
315	};
316
317	serdes0_qsgmii_link: phy@1 {
318		reg = <2>;
319		cdns,num-lanes = <1>;
320		#phy-cells = <0>;
321		cdns,phy-type = <PHY_TYPE_QSGMII>;
322		resets = <&serdes_wiz0 3>;
323	};
324};
325
326&pcie1_rc {
327	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
328	phys = <&serdes0_pcie_link>;
329	phy-names = "pcie-phy";
330	num-lanes = <2>;
331};
332
333&pcie1_ep {
334	phys = <&serdes0_pcie_link>;
335	phy-names = "pcie-phy";
336	num-lanes = <2>;
337	status = "disabled";
338};
339