1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	compatible = "ti,j7200-evm", "ti,j7200";
16	model = "Texas Instruments J7200 EVM";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20	};
21
22	evm_12v0: fixedregulator-evm12v0 {
23		/* main supply */
24		compatible = "regulator-fixed";
25		regulator-name = "evm_12v0";
26		regulator-min-microvolt = <12000000>;
27		regulator-max-microvolt = <12000000>;
28		regulator-always-on;
29		regulator-boot-on;
30	};
31
32	vsys_3v3: fixedregulator-vsys3v3 {
33		/* Output of LM5140 */
34		compatible = "regulator-fixed";
35		regulator-name = "vsys_3v3";
36		regulator-min-microvolt = <3300000>;
37		regulator-max-microvolt = <3300000>;
38		vin-supply = <&evm_12v0>;
39		regulator-always-on;
40		regulator-boot-on;
41	};
42
43	vsys_5v0: fixedregulator-vsys5v0 {
44		/* Output of LM5140 */
45		compatible = "regulator-fixed";
46		regulator-name = "vsys_5v0";
47		regulator-min-microvolt = <5000000>;
48		regulator-max-microvolt = <5000000>;
49		vin-supply = <&evm_12v0>;
50		regulator-always-on;
51		regulator-boot-on;
52	};
53
54	vdd_mmc1: fixedregulator-sd {
55		/* Output of TPS22918 */
56		compatible = "regulator-fixed";
57		regulator-name = "vdd_mmc1";
58		regulator-min-microvolt = <3300000>;
59		regulator-max-microvolt = <3300000>;
60		regulator-boot-on;
61		enable-active-high;
62		vin-supply = <&vsys_3v3>;
63		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
64	};
65
66	vdd_sd_dv: gpio-regulator-TLV71033 {
67		/* Output of TLV71033 */
68		compatible = "regulator-gpio";
69		regulator-name = "tlv71033";
70		pinctrl-names = "default";
71		pinctrl-0 = <&vdd_sd_dv_pins_default>;
72		regulator-min-microvolt = <1800000>;
73		regulator-max-microvolt = <3300000>;
74		regulator-boot-on;
75		vin-supply = <&vsys_5v0>;
76		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
77		states = <1800000 0x0>,
78			 <3300000 0x1>;
79	};
80};
81
82&wkup_pmx2 {
83	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
84		pinctrl-single,pins = <
85			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
86			J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
87			J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
88			J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
89			J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
90			J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
91			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
92			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
93			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
94			J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
95			J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
96			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
97		>;
98	};
99
100	mcu_mdio_pins_default: mcu-mdio1-pins-default {
101		pinctrl-single,pins = <
102			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
103			J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
104		>;
105	};
106};
107
108&main_pmx0 {
109	main_i2c0_pins_default: main-i2c0-pins-default {
110		pinctrl-single,pins = <
111			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
112			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
113		>;
114	};
115
116	main_i2c1_pins_default: main-i2c1-pins-default {
117		pinctrl-single,pins = <
118			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
119			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
120		>;
121	};
122
123	main_mmc1_pins_default: main-mmc1-pins-default {
124		pinctrl-single,pins = <
125			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
126			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
127			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
128			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
129			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
130			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
131			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
132			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
133		>;
134	};
135
136	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
137		pinctrl-single,pins = <
138			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
139		>;
140	};
141};
142
143&main_pmx1 {
144	main_usbss0_pins_default: main-usbss0-pins-default {
145		pinctrl-single,pins = <
146			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
147		>;
148	};
149};
150
151&wkup_uart0 {
152	/* Wakeup UART is used by System firmware */
153	status = "reserved";
154};
155
156&mcu_uart0 {
157	status = "okay";
158	/* Default pinmux */
159};
160
161&main_uart0 {
162	status = "okay";
163	/* Shared with ATF on this platform */
164	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
165};
166
167&main_uart1 {
168	status = "okay";
169	/* Default pinmux */
170};
171
172&main_uart2 {
173	/* MAIN UART 2 is used by R5F firmware */
174	status = "reserved";
175};
176
177&main_gpio2 {
178	status = "disabled";
179};
180
181&main_gpio4 {
182	status = "disabled";
183};
184
185&main_gpio6 {
186	status = "disabled";
187};
188
189&wkup_gpio1 {
190	status = "disabled";
191};
192
193&mcu_cpsw {
194	pinctrl-names = "default";
195	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
196};
197
198&davinci_mdio {
199	phy0: ethernet-phy@0 {
200		reg = <0>;
201		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
202		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
203	};
204};
205
206&cpsw_port1 {
207	phy-mode = "rgmii-rxid";
208	phy-handle = <&phy0>;
209};
210
211&main_i2c0 {
212	status = "okay";
213	pinctrl-names = "default";
214	pinctrl-0 = <&main_i2c0_pins_default>;
215	clock-frequency = <400000>;
216
217	exp1: gpio@20 {
218		compatible = "ti,tca6416";
219		reg = <0x20>;
220		gpio-controller;
221		#gpio-cells = <2>;
222	};
223
224	exp2: gpio@22 {
225		compatible = "ti,tca6424";
226		reg = <0x22>;
227		gpio-controller;
228		#gpio-cells = <2>;
229	};
230};
231
232/*
233 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
234 * swapped on the CPB.
235 *
236 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
237 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
238 */
239&main_i2c1 {
240	status = "okay";
241	pinctrl-names = "default";
242	pinctrl-0 = <&main_i2c1_pins_default>;
243	clock-frequency = <400000>;
244
245	exp3: gpio@20 {
246		compatible = "ti,tca6408";
247		reg = <0x20>;
248		gpio-controller;
249		#gpio-cells = <2>;
250		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
251				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
252				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
253	};
254};
255
256&main_sdhci0 {
257	/* eMMC */
258	non-removable;
259	ti,driver-strength-ohm = <50>;
260	disable-wp;
261};
262
263&main_sdhci1 {
264	/* SD card */
265	pinctrl-0 = <&main_mmc1_pins_default>;
266	pinctrl-names = "default";
267	vmmc-supply = <&vdd_mmc1>;
268	vqmmc-supply = <&vdd_sd_dv>;
269	ti,driver-strength-ohm = <50>;
270	disable-wp;
271};
272
273&serdes_ln_ctrl {
274	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
275		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
276};
277
278&usb_serdes_mux {
279	idle-states = <1>; /* USB0 to SERDES lane 3 */
280};
281
282&usbss0 {
283	pinctrl-names = "default";
284	pinctrl-0 = <&main_usbss0_pins_default>;
285	ti,vbus-divider;
286	ti,usb2-only;
287};
288
289&usb0 {
290	dr_mode = "otg";
291	maximum-speed = "high-speed";
292};
293
294&tscadc0 {
295	adc {
296		ti,adc-channels = <0 1 2 3 4 5 6 7>;
297	};
298};
299
300&serdes_refclk {
301	clock-frequency = <100000000>;
302};
303
304&serdes0 {
305	serdes0_pcie_link: phy@0 {
306		reg = <0>;
307		cdns,num-lanes = <2>;
308		#phy-cells = <0>;
309		cdns,phy-type = <PHY_TYPE_PCIE>;
310		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
311	};
312
313	serdes0_qsgmii_link: phy@1 {
314		reg = <2>;
315		cdns,num-lanes = <1>;
316		#phy-cells = <0>;
317		cdns,phy-type = <PHY_TYPE_QSGMII>;
318		resets = <&serdes_wiz0 3>;
319	};
320};
321
322&pcie1_rc {
323	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
324	phys = <&serdes0_pcie_link>;
325	phy-names = "pcie-phy";
326	num-lanes = <2>;
327};
328
329&pcie1_ep {
330	phys = <&serdes0_pcie_link>;
331	phy-names = "pcie-phy";
332	num-lanes = <2>;
333	status = "disabled";
334};
335