1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	chosen {
16		stdout-path = "serial2:115200n8";
17		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
18	};
19};
20
21&wkup_pmx0 {
22	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
23		pinctrl-single,pins = <
24			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
25			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
26			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
27			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
28			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
29			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
30			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
31			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
32			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
33			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
34			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
35			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
36		>;
37	};
38
39	mcu_mdio_pins_default: mcu-mdio1-pins-default {
40		pinctrl-single,pins = <
41			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
42			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
43		>;
44	};
45};
46
47&main_pmx0 {
48	main_i2c1_pins_default: main-i2c1-pins-default {
49		pinctrl-single,pins = <
50			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
51			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
52		>;
53	};
54
55	main_mmc1_pins_default: main-mmc1-pins-default {
56		pinctrl-single,pins = <
57			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
58			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
59			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
60			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
61			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
62			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
63			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
64			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
65		>;
66	};
67
68	main_usbss0_pins_default: main-usbss0-pins-default {
69		pinctrl-single,pins = <
70			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
71		>;
72	};
73};
74
75&wkup_uart0 {
76	/* Wakeup UART is used by System firmware */
77	status = "reserved";
78};
79
80&main_uart0 {
81	/* Shared with ATF on this platform */
82	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
83};
84
85&main_uart2 {
86	/* MAIN UART 2 is used by R5F firmware */
87	status = "reserved";
88};
89
90&main_uart3 {
91	/* UART not brought out */
92	status = "disabled";
93};
94
95&main_uart4 {
96	/* UART not brought out */
97	status = "disabled";
98};
99
100&main_uart5 {
101	/* UART not brought out */
102	status = "disabled";
103};
104
105&main_uart6 {
106	/* UART not brought out */
107	status = "disabled";
108};
109
110&main_uart7 {
111	/* UART not brought out */
112	status = "disabled";
113};
114
115&main_uart8 {
116	/* UART not brought out */
117	status = "disabled";
118};
119
120&main_uart9 {
121	/* UART not brought out */
122	status = "disabled";
123};
124
125&mcu_cpsw {
126	pinctrl-names = "default";
127	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
128};
129
130&davinci_mdio {
131	phy0: ethernet-phy@0 {
132		reg = <0>;
133		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
134		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
135	};
136};
137
138&cpsw_port1 {
139	phy-mode = "rgmii-rxid";
140	phy-handle = <&phy0>;
141};
142
143&main_i2c0 {
144	exp1: gpio@20 {
145		compatible = "ti,tca6416";
146		reg = <0x20>;
147		gpio-controller;
148		#gpio-cells = <2>;
149	};
150
151	exp2: gpio@22 {
152		compatible = "ti,tca6424";
153		reg = <0x22>;
154		gpio-controller;
155		#gpio-cells = <2>;
156	};
157};
158
159/*
160 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
161 * swapped on the CPB.
162 *
163 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
164 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
165 */
166&main_i2c1 {
167	pinctrl-names = "default";
168	pinctrl-0 = <&main_i2c1_pins_default>;
169	clock-frequency = <400000>;
170
171	exp3: gpio@20 {
172		compatible = "ti,tca6408";
173		reg = <0x20>;
174		gpio-controller;
175		#gpio-cells = <2>;
176		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
177				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
178				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
179	};
180};
181
182&main_sdhci0 {
183	/* eMMC */
184	non-removable;
185	ti,driver-strength-ohm = <50>;
186	disable-wp;
187};
188
189&main_sdhci1 {
190	/* SD card */
191	pinctrl-0 = <&main_mmc1_pins_default>;
192	pinctrl-names = "default";
193	ti,driver-strength-ohm = <50>;
194	disable-wp;
195};
196
197&serdes_ln_ctrl {
198	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
199		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
200};
201
202&usb_serdes_mux {
203	idle-states = <1>; /* USB0 to SERDES lane 3 */
204};
205
206&usbss0 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&main_usbss0_pins_default>;
209	ti,vbus-divider;
210	ti,usb2-only;
211};
212
213&usb0 {
214	dr_mode = "otg";
215	maximum-speed = "high-speed";
216};
217
218&tscadc0 {
219	adc {
220		ti,adc-channels = <0 1 2 3 4 5 6 7>;
221	};
222};
223
224&serdes_refclk {
225	clock-frequency = <100000000>;
226};
227
228&serdes0 {
229	serdes0_pcie_link: phy@0 {
230		reg = <0>;
231		cdns,num-lanes = <2>;
232		#phy-cells = <0>;
233		cdns,phy-type = <PHY_TYPE_PCIE>;
234		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
235	};
236
237	serdes0_qsgmii_link: phy@1 {
238		reg = <2>;
239		cdns,num-lanes = <1>;
240		#phy-cells = <0>;
241		cdns,phy-type = <PHY_TYPE_QSGMII>;
242		resets = <&serdes_wiz0 3>;
243	};
244};
245
246&pcie1_rc {
247	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
248	phys = <&serdes0_pcie_link>;
249	phy-names = "pcie-phy";
250	num-lanes = <2>;
251};
252
253&pcie1_ep {
254	phys = <&serdes0_pcie_link>;
255	phy-names = "pcie-phy";
256	num-lanes = <2>;
257	status = "disabled";
258};
259