1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/mux/ti-serdes.h> 12#include <dt-bindings/phy/phy.h> 13 14/ { 15 compatible = "ti,j7200-evm", "ti,j7200"; 16 model = "Texas Instruments J7200 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 evm_12v0: fixedregulator-evm12v0 { 23 /* main supply */ 24 compatible = "regulator-fixed"; 25 regulator-name = "evm_12v0"; 26 regulator-min-microvolt = <12000000>; 27 regulator-max-microvolt = <12000000>; 28 regulator-always-on; 29 regulator-boot-on; 30 }; 31 32 vsys_3v3: fixedregulator-vsys3v3 { 33 /* Output of LM5140 */ 34 compatible = "regulator-fixed"; 35 regulator-name = "vsys_3v3"; 36 regulator-min-microvolt = <3300000>; 37 regulator-max-microvolt = <3300000>; 38 vin-supply = <&evm_12v0>; 39 regulator-always-on; 40 regulator-boot-on; 41 }; 42 43 vsys_5v0: fixedregulator-vsys5v0 { 44 /* Output of LM5140 */ 45 compatible = "regulator-fixed"; 46 regulator-name = "vsys_5v0"; 47 regulator-min-microvolt = <5000000>; 48 regulator-max-microvolt = <5000000>; 49 vin-supply = <&evm_12v0>; 50 regulator-always-on; 51 regulator-boot-on; 52 }; 53 54 vdd_mmc1: fixedregulator-sd { 55 /* Output of TPS22918 */ 56 compatible = "regulator-fixed"; 57 regulator-name = "vdd_mmc1"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 regulator-boot-on; 61 enable-active-high; 62 vin-supply = <&vsys_3v3>; 63 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 64 }; 65 66 vdd_sd_dv: gpio-regulator-TLV71033 { 67 /* Output of TLV71033 */ 68 compatible = "regulator-gpio"; 69 regulator-name = "tlv71033"; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&vdd_sd_dv_pins_default>; 72 regulator-min-microvolt = <1800000>; 73 regulator-max-microvolt = <3300000>; 74 regulator-boot-on; 75 vin-supply = <&vsys_5v0>; 76 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 77 states = <1800000 0x0>, 78 <3300000 0x1>; 79 }; 80}; 81 82&wkup_pmx0 { 83 mcu_uart0_pins_default: mcu-uart0-pins-default { 84 pinctrl-single,pins = < 85 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ 86 J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ 87 J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ 88 J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ 89 >; 90 }; 91 92 wkup_uart0_pins_default: wkup-uart0-pins-default { 93 pinctrl-single,pins = < 94 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 95 J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 96 >; 97 }; 98}; 99 100&wkup_pmx2 { 101 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 102 pinctrl-single,pins = < 103 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 104 J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 105 J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 106 J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 107 J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 108 J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 109 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 110 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 111 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 112 J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 113 J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 114 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 115 >; 116 }; 117 118 wkup_gpio_pins_default: wkup-gpio-pins-default { 119 pinctrl-single,pins = < 120 J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 121 >; 122 }; 123 124 mcu_mdio_pins_default: mcu-mdio1-pins-default { 125 pinctrl-single,pins = < 126 J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 127 J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 128 >; 129 }; 130}; 131 132&main_pmx0 { 133 main_uart0_pins_default: main-uart0-pins-default { 134 pinctrl-single,pins = < 135 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 136 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 137 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 138 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 139 >; 140 }; 141 142 main_uart1_pins_default: main-uart1-pins-default { 143 pinctrl-single,pins = < 144 J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ 145 J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ 146 >; 147 }; 148 149 main_uart3_pins_default: main-uart3-pins-default { 150 pinctrl-single,pins = < 151 J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ 152 J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ 153 >; 154 }; 155 156 main_i2c1_pins_default: main-i2c1-pins-default { 157 pinctrl-single,pins = < 158 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 159 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 160 >; 161 }; 162 163 main_mmc1_pins_default: main-mmc1-pins-default { 164 pinctrl-single,pins = < 165 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 166 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 167 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 168 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 169 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 170 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 171 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 172 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 173 >; 174 }; 175 176 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 177 pinctrl-single,pins = < 178 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 179 >; 180 }; 181}; 182 183&main_pmx1 { 184 main_usbss0_pins_default: main-usbss0-pins-default { 185 pinctrl-single,pins = < 186 J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 187 >; 188 }; 189}; 190 191&wkup_uart0 { 192 /* Wakeup UART is used by System firmware */ 193 status = "reserved"; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&wkup_uart0_pins_default>; 196}; 197 198&mcu_uart0 { 199 status = "okay"; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&mcu_uart0_pins_default>; 202 clock-frequency = <96000000>; 203}; 204 205&main_uart0 { 206 status = "okay"; 207 /* Shared with ATF on this platform */ 208 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&main_uart0_pins_default>; 211}; 212 213&main_uart1 { 214 status = "okay"; 215 /* Default pinmux */ 216 pinctrl-names = "default"; 217 pinctrl-0 = <&main_uart1_pins_default>; 218}; 219 220&main_uart2 { 221 /* MAIN UART 2 is used by R5F firmware */ 222 status = "reserved"; 223}; 224 225&main_uart3 { 226 /* Shared with MCAN Interface */ 227 status = "okay"; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&main_uart3_pins_default>; 230}; 231 232&main_gpio2 { 233 status = "disabled"; 234}; 235 236&main_gpio4 { 237 status = "disabled"; 238}; 239 240&main_gpio6 { 241 status = "disabled"; 242}; 243 244&wkup_gpio0 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&wkup_gpio_pins_default>; 247}; 248 249&wkup_gpio1 { 250 status = "disabled"; 251}; 252 253&mcu_cpsw { 254 pinctrl-names = "default"; 255 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 256}; 257 258&davinci_mdio { 259 phy0: ethernet-phy@0 { 260 reg = <0>; 261 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 262 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 263 }; 264}; 265 266&cpsw_port1 { 267 phy-mode = "rgmii-rxid"; 268 phy-handle = <&phy0>; 269}; 270 271&main_i2c0 { 272 status = "okay"; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&main_i2c0_pins_default>; 275 clock-frequency = <400000>; 276 277 exp1: gpio@20 { 278 compatible = "ti,tca6416"; 279 reg = <0x20>; 280 gpio-controller; 281 #gpio-cells = <2>; 282 }; 283 284 exp2: gpio@22 { 285 compatible = "ti,tca6424"; 286 reg = <0x22>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 }; 290}; 291 292/* 293 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 294 * swapped on the CPB. 295 * 296 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 297 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 298 */ 299&main_i2c1 { 300 status = "okay"; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&main_i2c1_pins_default>; 303 clock-frequency = <400000>; 304 305 exp3: gpio@20 { 306 compatible = "ti,tca6408"; 307 reg = <0x20>; 308 gpio-controller; 309 #gpio-cells = <2>; 310 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 311 "UB926_LOCK", "UB926_PWR_SW_CNTRL", 312 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 313 }; 314}; 315 316&main_sdhci0 { 317 /* eMMC */ 318 non-removable; 319 ti,driver-strength-ohm = <50>; 320 disable-wp; 321}; 322 323&main_sdhci1 { 324 /* SD card */ 325 pinctrl-0 = <&main_mmc1_pins_default>; 326 pinctrl-names = "default"; 327 vmmc-supply = <&vdd_mmc1>; 328 vqmmc-supply = <&vdd_sd_dv>; 329 ti,driver-strength-ohm = <50>; 330 disable-wp; 331}; 332 333&serdes_ln_ctrl { 334 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 335 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 336}; 337 338&usb_serdes_mux { 339 idle-states = <1>; /* USB0 to SERDES lane 3 */ 340}; 341 342&usbss0 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&main_usbss0_pins_default>; 345 ti,vbus-divider; 346 ti,usb2-only; 347}; 348 349&usb0 { 350 dr_mode = "otg"; 351 maximum-speed = "high-speed"; 352}; 353 354&tscadc0 { 355 adc { 356 ti,adc-channels = <0 1 2 3 4 5 6 7>; 357 }; 358}; 359 360&serdes_refclk { 361 clock-frequency = <100000000>; 362}; 363 364&serdes0 { 365 serdes0_pcie_link: phy@0 { 366 reg = <0>; 367 cdns,num-lanes = <2>; 368 #phy-cells = <0>; 369 cdns,phy-type = <PHY_TYPE_PCIE>; 370 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 371 }; 372 373 serdes0_qsgmii_link: phy@1 { 374 reg = <2>; 375 cdns,num-lanes = <1>; 376 #phy-cells = <0>; 377 cdns,phy-type = <PHY_TYPE_QSGMII>; 378 resets = <&serdes_wiz0 3>; 379 }; 380}; 381 382&pcie1_rc { 383 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 384 phys = <&serdes0_pcie_link>; 385 phy-names = "pcie-phy"; 386 num-lanes = <2>; 387}; 388 389&pcie1_ep { 390 phys = <&serdes0_pcie_link>; 391 phy-names = "pcie-phy"; 392 num-lanes = <2>; 393 status = "disabled"; 394}; 395