1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	chosen {
16		stdout-path = "serial2:115200n8";
17		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
18	};
19
20	evm_12v0: fixedregulator-evm12v0 {
21		/* main supply */
22		compatible = "regulator-fixed";
23		regulator-name = "evm_12v0";
24		regulator-min-microvolt = <12000000>;
25		regulator-max-microvolt = <12000000>;
26		regulator-always-on;
27		regulator-boot-on;
28	};
29
30	vsys_3v3: fixedregulator-vsys3v3 {
31		/* Output of LM5140 */
32		compatible = "regulator-fixed";
33		regulator-name = "vsys_3v3";
34		regulator-min-microvolt = <3300000>;
35		regulator-max-microvolt = <3300000>;
36		vin-supply = <&evm_12v0>;
37		regulator-always-on;
38		regulator-boot-on;
39	};
40
41	vsys_5v0: fixedregulator-vsys5v0 {
42		/* Output of LM5140 */
43		compatible = "regulator-fixed";
44		regulator-name = "vsys_5v0";
45		regulator-min-microvolt = <5000000>;
46		regulator-max-microvolt = <5000000>;
47		vin-supply = <&evm_12v0>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51
52	vdd_mmc1: fixedregulator-sd {
53		/* Output of TPS22918 */
54		compatible = "regulator-fixed";
55		regulator-name = "vdd_mmc1";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-boot-on;
59		enable-active-high;
60		vin-supply = <&vsys_3v3>;
61		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
62	};
63
64	vdd_sd_dv: gpio-regulator-TLV71033 {
65		/* Output of TLV71033 */
66		compatible = "regulator-gpio";
67		regulator-name = "tlv71033";
68		pinctrl-names = "default";
69		pinctrl-0 = <&vdd_sd_dv_pins_default>;
70		regulator-min-microvolt = <1800000>;
71		regulator-max-microvolt = <3300000>;
72		regulator-boot-on;
73		vin-supply = <&vsys_5v0>;
74		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
75		states = <1800000 0x0>,
76			 <3300000 0x1>;
77	};
78};
79
80&wkup_pmx0 {
81	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
82		pinctrl-single,pins = <
83			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
84			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
85			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
86			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
87			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
88			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
89			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
90			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
91			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
92			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
93			J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
94			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
95		>;
96	};
97
98	mcu_mdio_pins_default: mcu-mdio1-pins-default {
99		pinctrl-single,pins = <
100			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
101			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
102		>;
103	};
104};
105
106&main_pmx0 {
107	main_i2c0_pins_default: main-i2c0-pins-default {
108		pinctrl-single,pins = <
109			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
110			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
111		>;
112	};
113
114	main_i2c1_pins_default: main-i2c1-pins-default {
115		pinctrl-single,pins = <
116			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
117			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
118		>;
119	};
120
121	main_mmc1_pins_default: main-mmc1-pins-default {
122		pinctrl-single,pins = <
123			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
124			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
125			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
126			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
127			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
128			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
129			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
130			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
131		>;
132	};
133
134	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
135		pinctrl-single,pins = <
136			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
137		>;
138	};
139};
140
141&main_pmx1 {
142	main_usbss0_pins_default: main-usbss0-pins-default {
143		pinctrl-single,pins = <
144			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
145		>;
146	};
147};
148
149&wkup_uart0 {
150	/* Wakeup UART is used by System firmware */
151	status = "reserved";
152};
153
154&main_uart0 {
155	/* Shared with ATF on this platform */
156	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
157};
158
159&main_uart2 {
160	/* MAIN UART 2 is used by R5F firmware */
161	status = "reserved";
162};
163
164&main_uart3 {
165	/* UART not brought out */
166	status = "disabled";
167};
168
169&main_uart4 {
170	/* UART not brought out */
171	status = "disabled";
172};
173
174&main_uart5 {
175	/* UART not brought out */
176	status = "disabled";
177};
178
179&main_uart6 {
180	/* UART not brought out */
181	status = "disabled";
182};
183
184&main_uart7 {
185	/* UART not brought out */
186	status = "disabled";
187};
188
189&main_uart8 {
190	/* UART not brought out */
191	status = "disabled";
192};
193
194&main_uart9 {
195	/* UART not brought out */
196	status = "disabled";
197};
198
199&main_gpio2 {
200	status = "disabled";
201};
202
203&main_gpio4 {
204	status = "disabled";
205};
206
207&main_gpio6 {
208	status = "disabled";
209};
210
211&wkup_gpio1 {
212	status = "disabled";
213};
214
215&mcu_cpsw {
216	pinctrl-names = "default";
217	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
218};
219
220&davinci_mdio {
221	phy0: ethernet-phy@0 {
222		reg = <0>;
223		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
224		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
225	};
226};
227
228&cpsw_port1 {
229	phy-mode = "rgmii-rxid";
230	phy-handle = <&phy0>;
231};
232
233&main_i2c0 {
234	pinctrl-names = "default";
235	pinctrl-0 = <&main_i2c0_pins_default>;
236	clock-frequency = <400000>;
237
238	exp1: gpio@20 {
239		compatible = "ti,tca6416";
240		reg = <0x20>;
241		gpio-controller;
242		#gpio-cells = <2>;
243	};
244
245	exp2: gpio@22 {
246		compatible = "ti,tca6424";
247		reg = <0x22>;
248		gpio-controller;
249		#gpio-cells = <2>;
250	};
251};
252
253/*
254 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
255 * swapped on the CPB.
256 *
257 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
258 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
259 */
260&main_i2c1 {
261	pinctrl-names = "default";
262	pinctrl-0 = <&main_i2c1_pins_default>;
263	clock-frequency = <400000>;
264
265	exp3: gpio@20 {
266		compatible = "ti,tca6408";
267		reg = <0x20>;
268		gpio-controller;
269		#gpio-cells = <2>;
270		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
271				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
272				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
273	};
274};
275
276&main_sdhci0 {
277	/* eMMC */
278	non-removable;
279	ti,driver-strength-ohm = <50>;
280	disable-wp;
281};
282
283&main_sdhci1 {
284	/* SD card */
285	pinctrl-0 = <&main_mmc1_pins_default>;
286	pinctrl-names = "default";
287	vmmc-supply = <&vdd_mmc1>;
288	vqmmc-supply = <&vdd_sd_dv>;
289	ti,driver-strength-ohm = <50>;
290	disable-wp;
291};
292
293&serdes_ln_ctrl {
294	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
295		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
296};
297
298&usb_serdes_mux {
299	idle-states = <1>; /* USB0 to SERDES lane 3 */
300};
301
302&usbss0 {
303	pinctrl-names = "default";
304	pinctrl-0 = <&main_usbss0_pins_default>;
305	ti,vbus-divider;
306	ti,usb2-only;
307};
308
309&usb0 {
310	dr_mode = "otg";
311	maximum-speed = "high-speed";
312};
313
314&tscadc0 {
315	adc {
316		ti,adc-channels = <0 1 2 3 4 5 6 7>;
317	};
318};
319
320&serdes_refclk {
321	clock-frequency = <100000000>;
322};
323
324&serdes0 {
325	serdes0_pcie_link: phy@0 {
326		reg = <0>;
327		cdns,num-lanes = <2>;
328		#phy-cells = <0>;
329		cdns,phy-type = <PHY_TYPE_PCIE>;
330		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
331	};
332
333	serdes0_qsgmii_link: phy@1 {
334		reg = <2>;
335		cdns,num-lanes = <1>;
336		#phy-cells = <0>;
337		cdns,phy-type = <PHY_TYPE_QSGMII>;
338		resets = <&serdes_wiz0 3>;
339	};
340};
341
342&pcie1_rc {
343	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
344	phys = <&serdes0_pcie_link>;
345	phy-names = "pcie-phy";
346	num-lanes = <2>;
347};
348
349&pcie1_ep {
350	phys = <&serdes0_pcie_link>;
351	phy-names = "pcie-phy";
352	num-lanes = <2>;
353	status = "disabled";
354};
355