1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	compatible = "ti,j7200-evm", "ti,j7200";
16	model = "Texas Instruments J7200 EVM";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
21	};
22
23	evm_12v0: fixedregulator-evm12v0 {
24		/* main supply */
25		compatible = "regulator-fixed";
26		regulator-name = "evm_12v0";
27		regulator-min-microvolt = <12000000>;
28		regulator-max-microvolt = <12000000>;
29		regulator-always-on;
30		regulator-boot-on;
31	};
32
33	vsys_3v3: fixedregulator-vsys3v3 {
34		/* Output of LM5140 */
35		compatible = "regulator-fixed";
36		regulator-name = "vsys_3v3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		vin-supply = <&evm_12v0>;
40		regulator-always-on;
41		regulator-boot-on;
42	};
43
44	vsys_5v0: fixedregulator-vsys5v0 {
45		/* Output of LM5140 */
46		compatible = "regulator-fixed";
47		regulator-name = "vsys_5v0";
48		regulator-min-microvolt = <5000000>;
49		regulator-max-microvolt = <5000000>;
50		vin-supply = <&evm_12v0>;
51		regulator-always-on;
52		regulator-boot-on;
53	};
54
55	vdd_mmc1: fixedregulator-sd {
56		/* Output of TPS22918 */
57		compatible = "regulator-fixed";
58		regulator-name = "vdd_mmc1";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61		regulator-boot-on;
62		enable-active-high;
63		vin-supply = <&vsys_3v3>;
64		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
65	};
66
67	vdd_sd_dv: gpio-regulator-TLV71033 {
68		/* Output of TLV71033 */
69		compatible = "regulator-gpio";
70		regulator-name = "tlv71033";
71		pinctrl-names = "default";
72		pinctrl-0 = <&vdd_sd_dv_pins_default>;
73		regulator-min-microvolt = <1800000>;
74		regulator-max-microvolt = <3300000>;
75		regulator-boot-on;
76		vin-supply = <&vsys_5v0>;
77		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
78		states = <1800000 0x0>,
79			 <3300000 0x1>;
80	};
81};
82
83&wkup_pmx0 {
84	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
85		pinctrl-single,pins = <
86			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
87			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
88			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
89			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
90			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
91			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
92			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
93			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
94			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
95			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
96			J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
97			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
98		>;
99	};
100
101	mcu_mdio_pins_default: mcu-mdio1-pins-default {
102		pinctrl-single,pins = <
103			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
104			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
105		>;
106	};
107};
108
109&main_pmx0 {
110	main_i2c0_pins_default: main-i2c0-pins-default {
111		pinctrl-single,pins = <
112			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
113			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
114		>;
115	};
116
117	main_i2c1_pins_default: main-i2c1-pins-default {
118		pinctrl-single,pins = <
119			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
120			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
121		>;
122	};
123
124	main_mmc1_pins_default: main-mmc1-pins-default {
125		pinctrl-single,pins = <
126			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
127			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
128			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
129			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
130			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
131			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
132			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
133			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
134		>;
135	};
136
137	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
138		pinctrl-single,pins = <
139			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
140		>;
141	};
142};
143
144&main_pmx1 {
145	main_usbss0_pins_default: main-usbss0-pins-default {
146		pinctrl-single,pins = <
147			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
148		>;
149	};
150};
151
152&wkup_uart0 {
153	/* Wakeup UART is used by System firmware */
154	status = "reserved";
155};
156
157&main_uart0 {
158	/* Shared with ATF on this platform */
159	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
160};
161
162&main_uart2 {
163	/* MAIN UART 2 is used by R5F firmware */
164	status = "reserved";
165};
166
167&main_uart3 {
168	/* UART not brought out */
169	status = "disabled";
170};
171
172&main_uart4 {
173	/* UART not brought out */
174	status = "disabled";
175};
176
177&main_uart5 {
178	/* UART not brought out */
179	status = "disabled";
180};
181
182&main_uart6 {
183	/* UART not brought out */
184	status = "disabled";
185};
186
187&main_uart7 {
188	/* UART not brought out */
189	status = "disabled";
190};
191
192&main_uart8 {
193	/* UART not brought out */
194	status = "disabled";
195};
196
197&main_uart9 {
198	/* UART not brought out */
199	status = "disabled";
200};
201
202&main_gpio2 {
203	status = "disabled";
204};
205
206&main_gpio4 {
207	status = "disabled";
208};
209
210&main_gpio6 {
211	status = "disabled";
212};
213
214&wkup_gpio1 {
215	status = "disabled";
216};
217
218&mcu_cpsw {
219	pinctrl-names = "default";
220	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
221};
222
223&davinci_mdio {
224	phy0: ethernet-phy@0 {
225		reg = <0>;
226		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
227		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
228	};
229};
230
231&cpsw_port1 {
232	phy-mode = "rgmii-rxid";
233	phy-handle = <&phy0>;
234};
235
236&main_i2c0 {
237	pinctrl-names = "default";
238	pinctrl-0 = <&main_i2c0_pins_default>;
239	clock-frequency = <400000>;
240
241	exp1: gpio@20 {
242		compatible = "ti,tca6416";
243		reg = <0x20>;
244		gpio-controller;
245		#gpio-cells = <2>;
246	};
247
248	exp2: gpio@22 {
249		compatible = "ti,tca6424";
250		reg = <0x22>;
251		gpio-controller;
252		#gpio-cells = <2>;
253	};
254};
255
256/*
257 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
258 * swapped on the CPB.
259 *
260 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
261 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
262 */
263&main_i2c1 {
264	pinctrl-names = "default";
265	pinctrl-0 = <&main_i2c1_pins_default>;
266	clock-frequency = <400000>;
267
268	exp3: gpio@20 {
269		compatible = "ti,tca6408";
270		reg = <0x20>;
271		gpio-controller;
272		#gpio-cells = <2>;
273		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
274				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
275				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
276	};
277};
278
279&main_sdhci0 {
280	/* eMMC */
281	non-removable;
282	ti,driver-strength-ohm = <50>;
283	disable-wp;
284};
285
286&main_sdhci1 {
287	/* SD card */
288	pinctrl-0 = <&main_mmc1_pins_default>;
289	pinctrl-names = "default";
290	vmmc-supply = <&vdd_mmc1>;
291	vqmmc-supply = <&vdd_sd_dv>;
292	ti,driver-strength-ohm = <50>;
293	disable-wp;
294};
295
296&serdes_ln_ctrl {
297	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
298		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
299};
300
301&usb_serdes_mux {
302	idle-states = <1>; /* USB0 to SERDES lane 3 */
303};
304
305&usbss0 {
306	pinctrl-names = "default";
307	pinctrl-0 = <&main_usbss0_pins_default>;
308	ti,vbus-divider;
309	ti,usb2-only;
310};
311
312&usb0 {
313	dr_mode = "otg";
314	maximum-speed = "high-speed";
315};
316
317&tscadc0 {
318	adc {
319		ti,adc-channels = <0 1 2 3 4 5 6 7>;
320	};
321};
322
323&serdes_refclk {
324	clock-frequency = <100000000>;
325};
326
327&serdes0 {
328	serdes0_pcie_link: phy@0 {
329		reg = <0>;
330		cdns,num-lanes = <2>;
331		#phy-cells = <0>;
332		cdns,phy-type = <PHY_TYPE_PCIE>;
333		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
334	};
335
336	serdes0_qsgmii_link: phy@1 {
337		reg = <2>;
338		cdns,num-lanes = <1>;
339		#phy-cells = <0>;
340		cdns,phy-type = <PHY_TYPE_QSGMII>;
341		resets = <&serdes_wiz0 3>;
342	};
343};
344
345&pcie1_rc {
346	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
347	phys = <&serdes0_pcie_link>;
348	phy-names = "pcie-phy";
349	num-lanes = <2>;
350};
351
352&pcie1_ep {
353	phys = <&serdes0_pcie_link>;
354	phy-names = "pcie-phy";
355	num-lanes = <2>;
356	status = "disabled";
357};
358