1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/phy/phy.h> 12 13#include "k3-serdes.h" 14 15/ { 16 compatible = "ti,j7200-evm", "ti,j7200"; 17 model = "Texas Instruments J7200 EVM"; 18 19 aliases { 20 serial0 = &wkup_uart0; 21 serial1 = &mcu_uart0; 22 serial2 = &main_uart0; 23 serial3 = &main_uart1; 24 serial5 = &main_uart3; 25 mmc0 = &main_sdhci0; 26 mmc1 = &main_sdhci1; 27 }; 28 29 chosen { 30 stdout-path = "serial2:115200n8"; 31 }; 32 33 evm_12v0: fixedregulator-evm12v0 { 34 /* main supply */ 35 compatible = "regulator-fixed"; 36 regulator-name = "evm_12v0"; 37 regulator-min-microvolt = <12000000>; 38 regulator-max-microvolt = <12000000>; 39 regulator-always-on; 40 regulator-boot-on; 41 }; 42 43 vsys_3v3: fixedregulator-vsys3v3 { 44 /* Output of LM5140 */ 45 compatible = "regulator-fixed"; 46 regulator-name = "vsys_3v3"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 vin-supply = <&evm_12v0>; 50 regulator-always-on; 51 regulator-boot-on; 52 }; 53 54 vsys_5v0: fixedregulator-vsys5v0 { 55 /* Output of LM5140 */ 56 compatible = "regulator-fixed"; 57 regulator-name = "vsys_5v0"; 58 regulator-min-microvolt = <5000000>; 59 regulator-max-microvolt = <5000000>; 60 vin-supply = <&evm_12v0>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 vdd_mmc1: fixedregulator-sd { 66 /* Output of TPS22918 */ 67 compatible = "regulator-fixed"; 68 regulator-name = "vdd_mmc1"; 69 regulator-min-microvolt = <3300000>; 70 regulator-max-microvolt = <3300000>; 71 regulator-boot-on; 72 enable-active-high; 73 vin-supply = <&vsys_3v3>; 74 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 75 }; 76 77 vdd_sd_dv: gpio-regulator-TLV71033 { 78 /* Output of TLV71033 */ 79 compatible = "regulator-gpio"; 80 regulator-name = "tlv71033"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&vdd_sd_dv_pins_default>; 83 regulator-min-microvolt = <1800000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 vin-supply = <&vsys_5v0>; 87 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 88 states = <1800000 0x0>, 89 <3300000 0x1>; 90 }; 91}; 92 93&wkup_pmx0 { 94 mcu_uart0_pins_default: mcu-uart0-default-pins { 95 pinctrl-single,pins = < 96 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ 97 J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ 98 J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ 99 J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ 100 >; 101 }; 102 103 wkup_uart0_pins_default: wkup-uart0-default-pins { 104 pinctrl-single,pins = < 105 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 106 J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 107 >; 108 }; 109}; 110 111&wkup_pmx2 { 112 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 113 pinctrl-single,pins = < 114 J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 115 J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 116 J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 117 J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 118 J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 119 J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 120 J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 121 J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 122 J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 123 J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 124 J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 125 J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 126 >; 127 }; 128 129 wkup_gpio_pins_default: wkup-gpio-default-pins { 130 pinctrl-single,pins = < 131 J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 132 >; 133 }; 134 135 mcu_mdio_pins_default: mcu-mdio1-default-pins { 136 pinctrl-single,pins = < 137 J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 138 J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 139 >; 140 }; 141}; 142 143&main_pmx0 { 144 main_uart0_pins_default: main-uart0-default-pins { 145 pinctrl-single,pins = < 146 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 147 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 148 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 149 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 150 >; 151 }; 152 153 main_uart1_pins_default: main-uart1-default-pins { 154 pinctrl-single,pins = < 155 J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ 156 J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ 157 >; 158 }; 159 160 main_uart3_pins_default: main-uart3-default-pins { 161 pinctrl-single,pins = < 162 J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ 163 J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ 164 >; 165 }; 166 167 main_i2c1_pins_default: main-i2c1-default-pins { 168 pinctrl-single,pins = < 169 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 170 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 171 >; 172 }; 173 174 main_mmc1_pins_default: main-mmc1-default-pins { 175 pinctrl-single,pins = < 176 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 177 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 178 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 179 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 180 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 181 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 182 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 183 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 184 >; 185 }; 186 187 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 188 pinctrl-single,pins = < 189 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 190 >; 191 }; 192}; 193 194&main_pmx1 { 195 main_usbss0_pins_default: main-usbss0-default-pins { 196 pinctrl-single,pins = < 197 J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 198 >; 199 }; 200}; 201 202&wkup_uart0 { 203 /* Wakeup UART is used by System firmware */ 204 status = "reserved"; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&wkup_uart0_pins_default>; 207}; 208 209&mcu_uart0 { 210 status = "okay"; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&mcu_uart0_pins_default>; 213 clock-frequency = <96000000>; 214}; 215 216&main_uart0 { 217 status = "okay"; 218 /* Shared with ATF on this platform */ 219 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&main_uart0_pins_default>; 222}; 223 224&main_uart1 { 225 status = "okay"; 226 /* Default pinmux */ 227 pinctrl-names = "default"; 228 pinctrl-0 = <&main_uart1_pins_default>; 229}; 230 231&main_uart2 { 232 /* MAIN UART 2 is used by R5F firmware */ 233 status = "reserved"; 234}; 235 236&main_uart3 { 237 /* Shared with MCAN Interface */ 238 status = "okay"; 239 pinctrl-names = "default"; 240 pinctrl-0 = <&main_uart3_pins_default>; 241}; 242 243&main_gpio2 { 244 status = "disabled"; 245}; 246 247&main_gpio4 { 248 status = "disabled"; 249}; 250 251&main_gpio6 { 252 status = "disabled"; 253}; 254 255&wkup_gpio0 { 256 pinctrl-names = "default"; 257 pinctrl-0 = <&wkup_gpio_pins_default>; 258}; 259 260&wkup_gpio1 { 261 status = "disabled"; 262}; 263 264&mcu_cpsw { 265 pinctrl-names = "default"; 266 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 267}; 268 269&davinci_mdio { 270 phy0: ethernet-phy@0 { 271 reg = <0>; 272 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 273 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 274 }; 275}; 276 277&cpsw_port1 { 278 phy-mode = "rgmii-rxid"; 279 phy-handle = <&phy0>; 280}; 281 282&main_i2c0 { 283 status = "okay"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&main_i2c0_pins_default>; 286 clock-frequency = <400000>; 287 288 exp1: gpio@20 { 289 compatible = "ti,tca6416"; 290 reg = <0x20>; 291 gpio-controller; 292 #gpio-cells = <2>; 293 }; 294 295 exp2: gpio@22 { 296 compatible = "ti,tca6424"; 297 reg = <0x22>; 298 gpio-controller; 299 #gpio-cells = <2>; 300 }; 301}; 302 303/* 304 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 305 * swapped on the CPB. 306 * 307 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 308 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 309 */ 310&main_i2c1 { 311 status = "okay"; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&main_i2c1_pins_default>; 314 clock-frequency = <400000>; 315 316 exp3: gpio@20 { 317 compatible = "ti,tca6408"; 318 reg = <0x20>; 319 gpio-controller; 320 #gpio-cells = <2>; 321 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 322 "UB926_LOCK", "UB926_PWR_SW_CNTRL", 323 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 324 }; 325}; 326 327&main_sdhci0 { 328 /* eMMC */ 329 status = "okay"; 330 non-removable; 331 ti,driver-strength-ohm = <50>; 332 disable-wp; 333}; 334 335&main_sdhci1 { 336 /* SD card */ 337 status = "okay"; 338 pinctrl-0 = <&main_mmc1_pins_default>; 339 pinctrl-names = "default"; 340 vmmc-supply = <&vdd_mmc1>; 341 vqmmc-supply = <&vdd_sd_dv>; 342 ti,driver-strength-ohm = <50>; 343 disable-wp; 344}; 345 346&serdes_ln_ctrl { 347 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 348 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 349}; 350 351&usb_serdes_mux { 352 idle-states = <1>; /* USB0 to SERDES lane 3 */ 353}; 354 355&usbss0 { 356 pinctrl-names = "default"; 357 pinctrl-0 = <&main_usbss0_pins_default>; 358 ti,vbus-divider; 359 ti,usb2-only; 360}; 361 362&usb0 { 363 dr_mode = "otg"; 364 maximum-speed = "high-speed"; 365}; 366 367&tscadc0 { 368 adc { 369 ti,adc-channels = <0 1 2 3 4 5 6 7>; 370 }; 371}; 372 373&serdes_refclk { 374 clock-frequency = <100000000>; 375}; 376 377&serdes0 { 378 serdes0_pcie_link: phy@0 { 379 reg = <0>; 380 cdns,num-lanes = <2>; 381 #phy-cells = <0>; 382 cdns,phy-type = <PHY_TYPE_PCIE>; 383 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 384 }; 385 386 serdes0_qsgmii_link: phy@1 { 387 reg = <2>; 388 cdns,num-lanes = <1>; 389 #phy-cells = <0>; 390 cdns,phy-type = <PHY_TYPE_QSGMII>; 391 resets = <&serdes_wiz0 3>; 392 }; 393}; 394 395&pcie1_rc { 396 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 397 phys = <&serdes0_pcie_link>; 398 phy-names = "pcie-phy"; 399 num-lanes = <2>; 400}; 401 402&pcie1_ep { 403 phys = <&serdes0_pcie_link>; 404 phy-names = "pcie-phy"; 405 num-lanes = <2>; 406 status = "disabled"; 407}; 408