126bd3f31SLokesh Vutla// SPDX-License-Identifier: GPL-2.0
226bd3f31SLokesh Vutla/*
326bd3f31SLokesh Vutla * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
426bd3f31SLokesh Vutla */
526bd3f31SLokesh Vutla
626bd3f31SLokesh Vutla/dts-v1/;
726bd3f31SLokesh Vutla
826bd3f31SLokesh Vutla#include "k3-j7200-som-p0.dtsi"
93a6319dfSKishon Vijay Abraham I#include <dt-bindings/gpio/gpio.h>
10fc3b1550SGrygorii Strashko#include <dt-bindings/net/ti-dp83867.h>
11e38a45b0SKishon Vijay Abraham I#include <dt-bindings/mux/ti-serdes.h>
12429c0259SKishon Vijay Abraham I#include <dt-bindings/phy/phy.h>
1326bd3f31SLokesh Vutla
1426bd3f31SLokesh Vutla/ {
152cf3213dSNishanth Menon	compatible = "ti,j7200-evm", "ti,j7200";
162cf3213dSNishanth Menon	model = "Texas Instruments J7200 EVM";
172cf3213dSNishanth Menon
1826bd3f31SLokesh Vutla	chosen {
1926bd3f31SLokesh Vutla		stdout-path = "serial2:115200n8";
2026bd3f31SLokesh Vutla	};
2194374990SAswath Govindraju
2294374990SAswath Govindraju	evm_12v0: fixedregulator-evm12v0 {
2394374990SAswath Govindraju		/* main supply */
2494374990SAswath Govindraju		compatible = "regulator-fixed";
2594374990SAswath Govindraju		regulator-name = "evm_12v0";
2694374990SAswath Govindraju		regulator-min-microvolt = <12000000>;
2794374990SAswath Govindraju		regulator-max-microvolt = <12000000>;
2894374990SAswath Govindraju		regulator-always-on;
2994374990SAswath Govindraju		regulator-boot-on;
3094374990SAswath Govindraju	};
3194374990SAswath Govindraju
3294374990SAswath Govindraju	vsys_3v3: fixedregulator-vsys3v3 {
3394374990SAswath Govindraju		/* Output of LM5140 */
3494374990SAswath Govindraju		compatible = "regulator-fixed";
3594374990SAswath Govindraju		regulator-name = "vsys_3v3";
3694374990SAswath Govindraju		regulator-min-microvolt = <3300000>;
3794374990SAswath Govindraju		regulator-max-microvolt = <3300000>;
3894374990SAswath Govindraju		vin-supply = <&evm_12v0>;
3994374990SAswath Govindraju		regulator-always-on;
4094374990SAswath Govindraju		regulator-boot-on;
4194374990SAswath Govindraju	};
4294374990SAswath Govindraju
4394374990SAswath Govindraju	vsys_5v0: fixedregulator-vsys5v0 {
4494374990SAswath Govindraju		/* Output of LM5140 */
4594374990SAswath Govindraju		compatible = "regulator-fixed";
4694374990SAswath Govindraju		regulator-name = "vsys_5v0";
4794374990SAswath Govindraju		regulator-min-microvolt = <5000000>;
4894374990SAswath Govindraju		regulator-max-microvolt = <5000000>;
4994374990SAswath Govindraju		vin-supply = <&evm_12v0>;
5094374990SAswath Govindraju		regulator-always-on;
5194374990SAswath Govindraju		regulator-boot-on;
5294374990SAswath Govindraju	};
5394374990SAswath Govindraju
5494374990SAswath Govindraju	vdd_mmc1: fixedregulator-sd {
5594374990SAswath Govindraju		/* Output of TPS22918 */
5694374990SAswath Govindraju		compatible = "regulator-fixed";
5794374990SAswath Govindraju		regulator-name = "vdd_mmc1";
5894374990SAswath Govindraju		regulator-min-microvolt = <3300000>;
5994374990SAswath Govindraju		regulator-max-microvolt = <3300000>;
6094374990SAswath Govindraju		regulator-boot-on;
6194374990SAswath Govindraju		enable-active-high;
6294374990SAswath Govindraju		vin-supply = <&vsys_3v3>;
6394374990SAswath Govindraju		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
6494374990SAswath Govindraju	};
6594374990SAswath Govindraju
6694374990SAswath Govindraju	vdd_sd_dv: gpio-regulator-TLV71033 {
6794374990SAswath Govindraju		/* Output of TLV71033 */
6894374990SAswath Govindraju		compatible = "regulator-gpio";
6994374990SAswath Govindraju		regulator-name = "tlv71033";
7094374990SAswath Govindraju		pinctrl-names = "default";
7194374990SAswath Govindraju		pinctrl-0 = <&vdd_sd_dv_pins_default>;
7294374990SAswath Govindraju		regulator-min-microvolt = <1800000>;
7394374990SAswath Govindraju		regulator-max-microvolt = <3300000>;
7494374990SAswath Govindraju		regulator-boot-on;
7594374990SAswath Govindraju		vin-supply = <&vsys_5v0>;
7694374990SAswath Govindraju		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
7794374990SAswath Govindraju		states = <1800000 0x0>,
7894374990SAswath Govindraju			 <3300000 0x1>;
7994374990SAswath Govindraju	};
8026bd3f31SLokesh Vutla};
8126bd3f31SLokesh Vutla
829ae21ac4SVaishnav Achath&wkup_pmx2 {
83fc3b1550SGrygorii Strashko	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
84fc3b1550SGrygorii Strashko		pinctrl-single,pins = <
85*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
86*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
87*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
88*3d011933SKeerthy			J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
89*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
90*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
91*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
92*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
93*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
94*3d011933SKeerthy			J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
95*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
96*3d011933SKeerthy			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
97fc3b1550SGrygorii Strashko		>;
98fc3b1550SGrygorii Strashko	};
99fc3b1550SGrygorii Strashko
100fc3b1550SGrygorii Strashko	mcu_mdio_pins_default: mcu-mdio1-pins-default {
101fc3b1550SGrygorii Strashko		pinctrl-single,pins = <
102*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
103*3d011933SKeerthy			J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
104fc3b1550SGrygorii Strashko		>;
105fc3b1550SGrygorii Strashko	};
106fc3b1550SGrygorii Strashko};
107fc3b1550SGrygorii Strashko
108e25889f8SVignesh Raghavendra&main_pmx0 {
10994374990SAswath Govindraju	main_i2c0_pins_default: main-i2c0-pins-default {
11094374990SAswath Govindraju		pinctrl-single,pins = <
11194374990SAswath Govindraju			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
11294374990SAswath Govindraju			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
11394374990SAswath Govindraju		>;
11494374990SAswath Govindraju	};
11594374990SAswath Govindraju
116e25889f8SVignesh Raghavendra	main_i2c1_pins_default: main-i2c1-pins-default {
117e25889f8SVignesh Raghavendra		pinctrl-single,pins = <
118e25889f8SVignesh Raghavendra			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
119e25889f8SVignesh Raghavendra			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
120e25889f8SVignesh Raghavendra		>;
121e25889f8SVignesh Raghavendra	};
122a2178b83SFaiz Abbas
123a2178b83SFaiz Abbas	main_mmc1_pins_default: main-mmc1-pins-default {
124a2178b83SFaiz Abbas		pinctrl-single,pins = <
125a2178b83SFaiz Abbas			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
126a2178b83SFaiz Abbas			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
127a2178b83SFaiz Abbas			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
128a2178b83SFaiz Abbas			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
129a2178b83SFaiz Abbas			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
130a2178b83SFaiz Abbas			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
131a2178b83SFaiz Abbas			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
132a2178b83SFaiz Abbas			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
133a2178b83SFaiz Abbas		>;
134a2178b83SFaiz Abbas	};
135bbcb0522SRoger Quadros
13694374990SAswath Govindraju	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
13794374990SAswath Govindraju		pinctrl-single,pins = <
13894374990SAswath Govindraju			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
13994374990SAswath Govindraju		>;
14094374990SAswath Govindraju	};
141e25889f8SVignesh Raghavendra};
142e25889f8SVignesh Raghavendra
1430d0a0b44SMatt Ranostay&main_pmx1 {
1440d0a0b44SMatt Ranostay	main_usbss0_pins_default: main-usbss0-pins-default {
1450d0a0b44SMatt Ranostay		pinctrl-single,pins = <
1460d0a0b44SMatt Ranostay			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
1470d0a0b44SMatt Ranostay		>;
1480d0a0b44SMatt Ranostay	};
1490d0a0b44SMatt Ranostay};
1500d0a0b44SMatt Ranostay
15126bd3f31SLokesh Vutla&wkup_uart0 {
15226bd3f31SLokesh Vutla	/* Wakeup UART is used by System firmware */
1534cc34aa8SNishanth Menon	status = "reserved";
15426bd3f31SLokesh Vutla};
15526bd3f31SLokesh Vutla
156dae322f8SAndrew Davis&mcu_uart0 {
157dae322f8SAndrew Davis	status = "okay";
158dae322f8SAndrew Davis	/* Default pinmux */
159dae322f8SAndrew Davis};
160dae322f8SAndrew Davis
16126bd3f31SLokesh Vutla&main_uart0 {
162dae322f8SAndrew Davis	status = "okay";
16326bd3f31SLokesh Vutla	/* Shared with ATF on this platform */
16426bd3f31SLokesh Vutla	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
16526bd3f31SLokesh Vutla};
16626bd3f31SLokesh Vutla
167dae322f8SAndrew Davis&main_uart1 {
168dae322f8SAndrew Davis	status = "okay";
169dae322f8SAndrew Davis	/* Default pinmux */
170dae322f8SAndrew Davis};
171dae322f8SAndrew Davis
17226bd3f31SLokesh Vutla&main_uart2 {
17326bd3f31SLokesh Vutla	/* MAIN UART 2 is used by R5F firmware */
1744cc34aa8SNishanth Menon	status = "reserved";
17526bd3f31SLokesh Vutla};
17626bd3f31SLokesh Vutla
177f4cc7dafSFaiz Abbas&main_gpio2 {
178f4cc7dafSFaiz Abbas	status = "disabled";
179f4cc7dafSFaiz Abbas};
180f4cc7dafSFaiz Abbas
181f4cc7dafSFaiz Abbas&main_gpio4 {
182f4cc7dafSFaiz Abbas	status = "disabled";
183f4cc7dafSFaiz Abbas};
184f4cc7dafSFaiz Abbas
185f4cc7dafSFaiz Abbas&main_gpio6 {
186f4cc7dafSFaiz Abbas	status = "disabled";
187f4cc7dafSFaiz Abbas};
188f4cc7dafSFaiz Abbas
189f4cc7dafSFaiz Abbas&wkup_gpio1 {
190f4cc7dafSFaiz Abbas	status = "disabled";
191f4cc7dafSFaiz Abbas};
192f4cc7dafSFaiz Abbas
193fc3b1550SGrygorii Strashko&mcu_cpsw {
194fc3b1550SGrygorii Strashko	pinctrl-names = "default";
195fc3b1550SGrygorii Strashko	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
196fc3b1550SGrygorii Strashko};
197fc3b1550SGrygorii Strashko
198fc3b1550SGrygorii Strashko&davinci_mdio {
199fc3b1550SGrygorii Strashko	phy0: ethernet-phy@0 {
200fc3b1550SGrygorii Strashko		reg = <0>;
201fc3b1550SGrygorii Strashko		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
202fc3b1550SGrygorii Strashko		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
203fc3b1550SGrygorii Strashko	};
204fc3b1550SGrygorii Strashko};
205fc3b1550SGrygorii Strashko
206fc3b1550SGrygorii Strashko&cpsw_port1 {
207fc3b1550SGrygorii Strashko	phy-mode = "rgmii-rxid";
208fc3b1550SGrygorii Strashko	phy-handle = <&phy0>;
209fc3b1550SGrygorii Strashko};
210e25889f8SVignesh Raghavendra
211e25889f8SVignesh Raghavendra&main_i2c0 {
212a9ed915cSAndrew Davis	status = "okay";
21394374990SAswath Govindraju	pinctrl-names = "default";
21494374990SAswath Govindraju	pinctrl-0 = <&main_i2c0_pins_default>;
21594374990SAswath Govindraju	clock-frequency = <400000>;
21694374990SAswath Govindraju
217e25889f8SVignesh Raghavendra	exp1: gpio@20 {
218e25889f8SVignesh Raghavendra		compatible = "ti,tca6416";
219e25889f8SVignesh Raghavendra		reg = <0x20>;
220e25889f8SVignesh Raghavendra		gpio-controller;
221e25889f8SVignesh Raghavendra		#gpio-cells = <2>;
222e25889f8SVignesh Raghavendra	};
223e25889f8SVignesh Raghavendra
224e25889f8SVignesh Raghavendra	exp2: gpio@22 {
225e25889f8SVignesh Raghavendra		compatible = "ti,tca6424";
226e25889f8SVignesh Raghavendra		reg = <0x22>;
227e25889f8SVignesh Raghavendra		gpio-controller;
228e25889f8SVignesh Raghavendra		#gpio-cells = <2>;
229e25889f8SVignesh Raghavendra	};
230e25889f8SVignesh Raghavendra};
231e25889f8SVignesh Raghavendra
2322eefbf5fSPeter Ujfalusi/*
2332eefbf5fSPeter Ujfalusi * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
2342eefbf5fSPeter Ujfalusi * swapped on the CPB.
2352eefbf5fSPeter Ujfalusi *
2362eefbf5fSPeter Ujfalusi * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
2372eefbf5fSPeter Ujfalusi * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
2382eefbf5fSPeter Ujfalusi */
239e25889f8SVignesh Raghavendra&main_i2c1 {
240a9ed915cSAndrew Davis	status = "okay";
241e25889f8SVignesh Raghavendra	pinctrl-names = "default";
242e25889f8SVignesh Raghavendra	pinctrl-0 = <&main_i2c1_pins_default>;
243e25889f8SVignesh Raghavendra	clock-frequency = <400000>;
244e25889f8SVignesh Raghavendra
2452eefbf5fSPeter Ujfalusi	exp3: gpio@20 {
246e25889f8SVignesh Raghavendra		compatible = "ti,tca6408";
247e25889f8SVignesh Raghavendra		reg = <0x20>;
248e25889f8SVignesh Raghavendra		gpio-controller;
249e25889f8SVignesh Raghavendra		#gpio-cells = <2>;
2502eefbf5fSPeter Ujfalusi		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
2512eefbf5fSPeter Ujfalusi				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
2522eefbf5fSPeter Ujfalusi				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
253e25889f8SVignesh Raghavendra	};
254e25889f8SVignesh Raghavendra};
255a2178b83SFaiz Abbas
256a2178b83SFaiz Abbas&main_sdhci0 {
257a2178b83SFaiz Abbas	/* eMMC */
258a2178b83SFaiz Abbas	non-removable;
259a2178b83SFaiz Abbas	ti,driver-strength-ohm = <50>;
260a2178b83SFaiz Abbas	disable-wp;
261a2178b83SFaiz Abbas};
262a2178b83SFaiz Abbas
263a2178b83SFaiz Abbas&main_sdhci1 {
264a2178b83SFaiz Abbas	/* SD card */
265a2178b83SFaiz Abbas	pinctrl-0 = <&main_mmc1_pins_default>;
266a2178b83SFaiz Abbas	pinctrl-names = "default";
26794374990SAswath Govindraju	vmmc-supply = <&vdd_mmc1>;
26894374990SAswath Govindraju	vqmmc-supply = <&vdd_sd_dv>;
269a2178b83SFaiz Abbas	ti,driver-strength-ohm = <50>;
270a2178b83SFaiz Abbas	disable-wp;
271a2178b83SFaiz Abbas};
272e38a45b0SKishon Vijay Abraham I
273e38a45b0SKishon Vijay Abraham I&serdes_ln_ctrl {
274e38a45b0SKishon Vijay Abraham I	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
275e38a45b0SKishon Vijay Abraham I		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
276e38a45b0SKishon Vijay Abraham I};
277bbcb0522SRoger Quadros
278bbcb0522SRoger Quadros&usb_serdes_mux {
279bbcb0522SRoger Quadros	idle-states = <1>; /* USB0 to SERDES lane 3 */
280bbcb0522SRoger Quadros};
281bbcb0522SRoger Quadros
282bbcb0522SRoger Quadros&usbss0 {
283bbcb0522SRoger Quadros	pinctrl-names = "default";
284bbcb0522SRoger Quadros	pinctrl-0 = <&main_usbss0_pins_default>;
285bbcb0522SRoger Quadros	ti,vbus-divider;
286bbcb0522SRoger Quadros	ti,usb2-only;
287bbcb0522SRoger Quadros};
288bbcb0522SRoger Quadros
289bbcb0522SRoger Quadros&usb0 {
290bbcb0522SRoger Quadros	dr_mode = "otg";
291bbcb0522SRoger Quadros	maximum-speed = "high-speed";
292bbcb0522SRoger Quadros};
293e6b45168SVignesh Raghavendra
294e6b45168SVignesh Raghavendra&tscadc0 {
295e6b45168SVignesh Raghavendra	adc {
296e6b45168SVignesh Raghavendra		ti,adc-channels = <0 1 2 3 4 5 6 7>;
297e6b45168SVignesh Raghavendra	};
298e6b45168SVignesh Raghavendra};
299429c0259SKishon Vijay Abraham I
300429c0259SKishon Vijay Abraham I&serdes_refclk {
301429c0259SKishon Vijay Abraham I	clock-frequency = <100000000>;
302429c0259SKishon Vijay Abraham I};
303429c0259SKishon Vijay Abraham I
304429c0259SKishon Vijay Abraham I&serdes0 {
305429c0259SKishon Vijay Abraham I	serdes0_pcie_link: phy@0 {
306429c0259SKishon Vijay Abraham I		reg = <0>;
307429c0259SKishon Vijay Abraham I		cdns,num-lanes = <2>;
308429c0259SKishon Vijay Abraham I		#phy-cells = <0>;
309429c0259SKishon Vijay Abraham I		cdns,phy-type = <PHY_TYPE_PCIE>;
310429c0259SKishon Vijay Abraham I		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
311429c0259SKishon Vijay Abraham I	};
312429c0259SKishon Vijay Abraham I
313429c0259SKishon Vijay Abraham I	serdes0_qsgmii_link: phy@1 {
314429c0259SKishon Vijay Abraham I		reg = <2>;
315429c0259SKishon Vijay Abraham I		cdns,num-lanes = <1>;
316429c0259SKishon Vijay Abraham I		#phy-cells = <0>;
317429c0259SKishon Vijay Abraham I		cdns,phy-type = <PHY_TYPE_QSGMII>;
318429c0259SKishon Vijay Abraham I		resets = <&serdes_wiz0 3>;
319429c0259SKishon Vijay Abraham I	};
320429c0259SKishon Vijay Abraham I};
3213a6319dfSKishon Vijay Abraham I
3223a6319dfSKishon Vijay Abraham I&pcie1_rc {
3233a6319dfSKishon Vijay Abraham I	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
3243a6319dfSKishon Vijay Abraham I	phys = <&serdes0_pcie_link>;
3253a6319dfSKishon Vijay Abraham I	phy-names = "pcie-phy";
3263a6319dfSKishon Vijay Abraham I	num-lanes = <2>;
3273a6319dfSKishon Vijay Abraham I};
3283a6319dfSKishon Vijay Abraham I
3293a6319dfSKishon Vijay Abraham I&pcie1_ep {
3303a6319dfSKishon Vijay Abraham I	phys = <&serdes0_pcie_link>;
3313a6319dfSKishon Vijay Abraham I	phy-names = "pcie-phy";
3323a6319dfSKishon Vijay Abraham I	num-lanes = <2>;
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3343a6319dfSKishon Vijay Abraham I};
335