126bd3f31SLokesh Vutla// SPDX-License-Identifier: GPL-2.0 226bd3f31SLokesh Vutla/* 326bd3f31SLokesh Vutla * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 426bd3f31SLokesh Vutla */ 526bd3f31SLokesh Vutla 626bd3f31SLokesh Vutla/dts-v1/; 726bd3f31SLokesh Vutla 826bd3f31SLokesh Vutla#include "k3-j7200-som-p0.dtsi" 93a6319dfSKishon Vijay Abraham I#include <dt-bindings/gpio/gpio.h> 10fc3b1550SGrygorii Strashko#include <dt-bindings/net/ti-dp83867.h> 11e38a45b0SKishon Vijay Abraham I#include <dt-bindings/mux/ti-serdes.h> 12429c0259SKishon Vijay Abraham I#include <dt-bindings/phy/phy.h> 1326bd3f31SLokesh Vutla 1426bd3f31SLokesh Vutla/ { 152cf3213dSNishanth Menon compatible = "ti,j7200-evm", "ti,j7200"; 162cf3213dSNishanth Menon model = "Texas Instruments J7200 EVM"; 172cf3213dSNishanth Menon 1826bd3f31SLokesh Vutla chosen { 1926bd3f31SLokesh Vutla stdout-path = "serial2:115200n8"; 2026bd3f31SLokesh Vutla }; 2194374990SAswath Govindraju 2294374990SAswath Govindraju evm_12v0: fixedregulator-evm12v0 { 2394374990SAswath Govindraju /* main supply */ 2494374990SAswath Govindraju compatible = "regulator-fixed"; 2594374990SAswath Govindraju regulator-name = "evm_12v0"; 2694374990SAswath Govindraju regulator-min-microvolt = <12000000>; 2794374990SAswath Govindraju regulator-max-microvolt = <12000000>; 2894374990SAswath Govindraju regulator-always-on; 2994374990SAswath Govindraju regulator-boot-on; 3094374990SAswath Govindraju }; 3194374990SAswath Govindraju 3294374990SAswath Govindraju vsys_3v3: fixedregulator-vsys3v3 { 3394374990SAswath Govindraju /* Output of LM5140 */ 3494374990SAswath Govindraju compatible = "regulator-fixed"; 3594374990SAswath Govindraju regulator-name = "vsys_3v3"; 3694374990SAswath Govindraju regulator-min-microvolt = <3300000>; 3794374990SAswath Govindraju regulator-max-microvolt = <3300000>; 3894374990SAswath Govindraju vin-supply = <&evm_12v0>; 3994374990SAswath Govindraju regulator-always-on; 4094374990SAswath Govindraju regulator-boot-on; 4194374990SAswath Govindraju }; 4294374990SAswath Govindraju 4394374990SAswath Govindraju vsys_5v0: fixedregulator-vsys5v0 { 4494374990SAswath Govindraju /* Output of LM5140 */ 4594374990SAswath Govindraju compatible = "regulator-fixed"; 4694374990SAswath Govindraju regulator-name = "vsys_5v0"; 4794374990SAswath Govindraju regulator-min-microvolt = <5000000>; 4894374990SAswath Govindraju regulator-max-microvolt = <5000000>; 4994374990SAswath Govindraju vin-supply = <&evm_12v0>; 5094374990SAswath Govindraju regulator-always-on; 5194374990SAswath Govindraju regulator-boot-on; 5294374990SAswath Govindraju }; 5394374990SAswath Govindraju 5494374990SAswath Govindraju vdd_mmc1: fixedregulator-sd { 5594374990SAswath Govindraju /* Output of TPS22918 */ 5694374990SAswath Govindraju compatible = "regulator-fixed"; 5794374990SAswath Govindraju regulator-name = "vdd_mmc1"; 5894374990SAswath Govindraju regulator-min-microvolt = <3300000>; 5994374990SAswath Govindraju regulator-max-microvolt = <3300000>; 6094374990SAswath Govindraju regulator-boot-on; 6194374990SAswath Govindraju enable-active-high; 6294374990SAswath Govindraju vin-supply = <&vsys_3v3>; 6394374990SAswath Govindraju gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 6494374990SAswath Govindraju }; 6594374990SAswath Govindraju 6694374990SAswath Govindraju vdd_sd_dv: gpio-regulator-TLV71033 { 6794374990SAswath Govindraju /* Output of TLV71033 */ 6894374990SAswath Govindraju compatible = "regulator-gpio"; 6994374990SAswath Govindraju regulator-name = "tlv71033"; 7094374990SAswath Govindraju pinctrl-names = "default"; 7194374990SAswath Govindraju pinctrl-0 = <&vdd_sd_dv_pins_default>; 7294374990SAswath Govindraju regulator-min-microvolt = <1800000>; 7394374990SAswath Govindraju regulator-max-microvolt = <3300000>; 7494374990SAswath Govindraju regulator-boot-on; 7594374990SAswath Govindraju vin-supply = <&vsys_5v0>; 7694374990SAswath Govindraju gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 7794374990SAswath Govindraju states = <1800000 0x0>, 7894374990SAswath Govindraju <3300000 0x1>; 7994374990SAswath Govindraju }; 8026bd3f31SLokesh Vutla}; 8126bd3f31SLokesh Vutla 82*3709ea7fSUdit Kumar&wkup_pmx0 { 83*3709ea7fSUdit Kumar mcu_uart0_pins_default: mcu-uart0-pins-default { 84*3709ea7fSUdit Kumar pinctrl-single,pins = < 85*3709ea7fSUdit Kumar J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ 86*3709ea7fSUdit Kumar J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ 87*3709ea7fSUdit Kumar J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ 88*3709ea7fSUdit Kumar J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ 89*3709ea7fSUdit Kumar >; 90*3709ea7fSUdit Kumar }; 91*3709ea7fSUdit Kumar 92*3709ea7fSUdit Kumar wkup_uart0_pins_default: wkup-uart0-pins-default { 93*3709ea7fSUdit Kumar pinctrl-single,pins = < 94*3709ea7fSUdit Kumar J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 95*3709ea7fSUdit Kumar J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 96*3709ea7fSUdit Kumar >; 97*3709ea7fSUdit Kumar }; 98*3709ea7fSUdit Kumar}; 99*3709ea7fSUdit Kumar 1009ae21ac4SVaishnav Achath&wkup_pmx2 { 101fc3b1550SGrygorii Strashko mcu_cpsw_pins_default: mcu-cpsw-pins-default { 102fc3b1550SGrygorii Strashko pinctrl-single,pins = < 1033d011933SKeerthy J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 1043d011933SKeerthy J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 1053d011933SKeerthy J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 1063d011933SKeerthy J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 1073d011933SKeerthy J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 1083d011933SKeerthy J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 1093d011933SKeerthy J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 1103d011933SKeerthy J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 1113d011933SKeerthy J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 1123d011933SKeerthy J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 1133d011933SKeerthy J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 1143d011933SKeerthy J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 115fc3b1550SGrygorii Strashko >; 116fc3b1550SGrygorii Strashko }; 117fc3b1550SGrygorii Strashko 118be8be0d0SVaishnav Achath wkup_gpio_pins_default: wkup-gpio-pins-default { 119be8be0d0SVaishnav Achath pinctrl-single,pins = < 120be8be0d0SVaishnav Achath J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 121be8be0d0SVaishnav Achath >; 122be8be0d0SVaishnav Achath }; 123be8be0d0SVaishnav Achath 124fc3b1550SGrygorii Strashko mcu_mdio_pins_default: mcu-mdio1-pins-default { 125fc3b1550SGrygorii Strashko pinctrl-single,pins = < 1263d011933SKeerthy J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 1273d011933SKeerthy J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 128fc3b1550SGrygorii Strashko >; 129fc3b1550SGrygorii Strashko }; 130fc3b1550SGrygorii Strashko}; 131fc3b1550SGrygorii Strashko 132e25889f8SVignesh Raghavendra&main_pmx0 { 133*3709ea7fSUdit Kumar main_uart0_pins_default: main-uart0-pins-default { 134*3709ea7fSUdit Kumar pinctrl-single,pins = < 135*3709ea7fSUdit Kumar J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 136*3709ea7fSUdit Kumar J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 137*3709ea7fSUdit Kumar J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 138*3709ea7fSUdit Kumar J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 139*3709ea7fSUdit Kumar >; 140*3709ea7fSUdit Kumar }; 141*3709ea7fSUdit Kumar 142*3709ea7fSUdit Kumar main_uart1_pins_default: main-uart1-pins-default { 143*3709ea7fSUdit Kumar pinctrl-single,pins = < 144*3709ea7fSUdit Kumar J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ 145*3709ea7fSUdit Kumar J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ 146*3709ea7fSUdit Kumar >; 147*3709ea7fSUdit Kumar }; 148*3709ea7fSUdit Kumar 149*3709ea7fSUdit Kumar main_uart3_pins_default: main-uart3-pins-default { 150*3709ea7fSUdit Kumar pinctrl-single,pins = < 151*3709ea7fSUdit Kumar J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ 152*3709ea7fSUdit Kumar J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ 153*3709ea7fSUdit Kumar >; 154*3709ea7fSUdit Kumar }; 155*3709ea7fSUdit Kumar 156e25889f8SVignesh Raghavendra main_i2c1_pins_default: main-i2c1-pins-default { 157e25889f8SVignesh Raghavendra pinctrl-single,pins = < 158e25889f8SVignesh Raghavendra J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 159e25889f8SVignesh Raghavendra J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 160e25889f8SVignesh Raghavendra >; 161e25889f8SVignesh Raghavendra }; 162a2178b83SFaiz Abbas 163a2178b83SFaiz Abbas main_mmc1_pins_default: main-mmc1-pins-default { 164a2178b83SFaiz Abbas pinctrl-single,pins = < 165a2178b83SFaiz Abbas J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 166a2178b83SFaiz Abbas J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 167a2178b83SFaiz Abbas J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 168a2178b83SFaiz Abbas J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 169a2178b83SFaiz Abbas J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 170a2178b83SFaiz Abbas J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 171a2178b83SFaiz Abbas J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 172a2178b83SFaiz Abbas J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 173a2178b83SFaiz Abbas >; 174a2178b83SFaiz Abbas }; 175bbcb0522SRoger Quadros 17694374990SAswath Govindraju vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 17794374990SAswath Govindraju pinctrl-single,pins = < 17894374990SAswath Govindraju J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 17994374990SAswath Govindraju >; 18094374990SAswath Govindraju }; 181e25889f8SVignesh Raghavendra}; 182e25889f8SVignesh Raghavendra 1830d0a0b44SMatt Ranostay&main_pmx1 { 1840d0a0b44SMatt Ranostay main_usbss0_pins_default: main-usbss0-pins-default { 1850d0a0b44SMatt Ranostay pinctrl-single,pins = < 1860d0a0b44SMatt Ranostay J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 1870d0a0b44SMatt Ranostay >; 1880d0a0b44SMatt Ranostay }; 1890d0a0b44SMatt Ranostay}; 1900d0a0b44SMatt Ranostay 19126bd3f31SLokesh Vutla&wkup_uart0 { 19226bd3f31SLokesh Vutla /* Wakeup UART is used by System firmware */ 1934cc34aa8SNishanth Menon status = "reserved"; 194*3709ea7fSUdit Kumar pinctrl-names = "default"; 195*3709ea7fSUdit Kumar pinctrl-0 = <&wkup_uart0_pins_default>; 19626bd3f31SLokesh Vutla}; 19726bd3f31SLokesh Vutla 198dae322f8SAndrew Davis&mcu_uart0 { 199dae322f8SAndrew Davis status = "okay"; 200*3709ea7fSUdit Kumar pinctrl-names = "default"; 201*3709ea7fSUdit Kumar pinctrl-0 = <&mcu_uart0_pins_default>; 202*3709ea7fSUdit Kumar clock-frequency = <96000000>; 203dae322f8SAndrew Davis}; 204dae322f8SAndrew Davis 20526bd3f31SLokesh Vutla&main_uart0 { 206dae322f8SAndrew Davis status = "okay"; 20726bd3f31SLokesh Vutla /* Shared with ATF on this platform */ 20826bd3f31SLokesh Vutla power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 209*3709ea7fSUdit Kumar pinctrl-names = "default"; 210*3709ea7fSUdit Kumar pinctrl-0 = <&main_uart0_pins_default>; 21126bd3f31SLokesh Vutla}; 21226bd3f31SLokesh Vutla 213dae322f8SAndrew Davis&main_uart1 { 214dae322f8SAndrew Davis status = "okay"; 215dae322f8SAndrew Davis /* Default pinmux */ 216*3709ea7fSUdit Kumar pinctrl-names = "default"; 217*3709ea7fSUdit Kumar pinctrl-0 = <&main_uart1_pins_default>; 218dae322f8SAndrew Davis}; 219dae322f8SAndrew Davis 22026bd3f31SLokesh Vutla&main_uart2 { 22126bd3f31SLokesh Vutla /* MAIN UART 2 is used by R5F firmware */ 2224cc34aa8SNishanth Menon status = "reserved"; 22326bd3f31SLokesh Vutla}; 22426bd3f31SLokesh Vutla 225*3709ea7fSUdit Kumar&main_uart3 { 226*3709ea7fSUdit Kumar /* Shared with MCAN Interface */ 227*3709ea7fSUdit Kumar status = "okay"; 228*3709ea7fSUdit Kumar pinctrl-names = "default"; 229*3709ea7fSUdit Kumar pinctrl-0 = <&main_uart3_pins_default>; 230*3709ea7fSUdit Kumar}; 231*3709ea7fSUdit Kumar 232f4cc7dafSFaiz Abbas&main_gpio2 { 233f4cc7dafSFaiz Abbas status = "disabled"; 234f4cc7dafSFaiz Abbas}; 235f4cc7dafSFaiz Abbas 236f4cc7dafSFaiz Abbas&main_gpio4 { 237f4cc7dafSFaiz Abbas status = "disabled"; 238f4cc7dafSFaiz Abbas}; 239f4cc7dafSFaiz Abbas 240f4cc7dafSFaiz Abbas&main_gpio6 { 241f4cc7dafSFaiz Abbas status = "disabled"; 242f4cc7dafSFaiz Abbas}; 243f4cc7dafSFaiz Abbas 244be8be0d0SVaishnav Achath&wkup_gpio0 { 245be8be0d0SVaishnav Achath pinctrl-names = "default"; 246be8be0d0SVaishnav Achath pinctrl-0 = <&wkup_gpio_pins_default>; 247be8be0d0SVaishnav Achath}; 248be8be0d0SVaishnav Achath 249f4cc7dafSFaiz Abbas&wkup_gpio1 { 250f4cc7dafSFaiz Abbas status = "disabled"; 251f4cc7dafSFaiz Abbas}; 252f4cc7dafSFaiz Abbas 253fc3b1550SGrygorii Strashko&mcu_cpsw { 254fc3b1550SGrygorii Strashko pinctrl-names = "default"; 255a6550e25SNishanth Menon pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 256fc3b1550SGrygorii Strashko}; 257fc3b1550SGrygorii Strashko 258fc3b1550SGrygorii Strashko&davinci_mdio { 259fc3b1550SGrygorii Strashko phy0: ethernet-phy@0 { 260fc3b1550SGrygorii Strashko reg = <0>; 261fc3b1550SGrygorii Strashko ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 262fc3b1550SGrygorii Strashko ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 263fc3b1550SGrygorii Strashko }; 264fc3b1550SGrygorii Strashko}; 265fc3b1550SGrygorii Strashko 266fc3b1550SGrygorii Strashko&cpsw_port1 { 267fc3b1550SGrygorii Strashko phy-mode = "rgmii-rxid"; 268fc3b1550SGrygorii Strashko phy-handle = <&phy0>; 269fc3b1550SGrygorii Strashko}; 270e25889f8SVignesh Raghavendra 271e25889f8SVignesh Raghavendra&main_i2c0 { 272a9ed915cSAndrew Davis status = "okay"; 27394374990SAswath Govindraju pinctrl-names = "default"; 27494374990SAswath Govindraju pinctrl-0 = <&main_i2c0_pins_default>; 27594374990SAswath Govindraju clock-frequency = <400000>; 27694374990SAswath Govindraju 277e25889f8SVignesh Raghavendra exp1: gpio@20 { 278e25889f8SVignesh Raghavendra compatible = "ti,tca6416"; 279e25889f8SVignesh Raghavendra reg = <0x20>; 280e25889f8SVignesh Raghavendra gpio-controller; 281e25889f8SVignesh Raghavendra #gpio-cells = <2>; 282e25889f8SVignesh Raghavendra }; 283e25889f8SVignesh Raghavendra 284e25889f8SVignesh Raghavendra exp2: gpio@22 { 285e25889f8SVignesh Raghavendra compatible = "ti,tca6424"; 286e25889f8SVignesh Raghavendra reg = <0x22>; 287e25889f8SVignesh Raghavendra gpio-controller; 288e25889f8SVignesh Raghavendra #gpio-cells = <2>; 289e25889f8SVignesh Raghavendra }; 290e25889f8SVignesh Raghavendra}; 291e25889f8SVignesh Raghavendra 2922eefbf5fSPeter Ujfalusi/* 2932eefbf5fSPeter Ujfalusi * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 2942eefbf5fSPeter Ujfalusi * swapped on the CPB. 2952eefbf5fSPeter Ujfalusi * 2962eefbf5fSPeter Ujfalusi * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 2972eefbf5fSPeter Ujfalusi * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 2982eefbf5fSPeter Ujfalusi */ 299e25889f8SVignesh Raghavendra&main_i2c1 { 300a9ed915cSAndrew Davis status = "okay"; 301e25889f8SVignesh Raghavendra pinctrl-names = "default"; 302e25889f8SVignesh Raghavendra pinctrl-0 = <&main_i2c1_pins_default>; 303e25889f8SVignesh Raghavendra clock-frequency = <400000>; 304e25889f8SVignesh Raghavendra 3052eefbf5fSPeter Ujfalusi exp3: gpio@20 { 306e25889f8SVignesh Raghavendra compatible = "ti,tca6408"; 307e25889f8SVignesh Raghavendra reg = <0x20>; 308e25889f8SVignesh Raghavendra gpio-controller; 309e25889f8SVignesh Raghavendra #gpio-cells = <2>; 3102eefbf5fSPeter Ujfalusi gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 3112eefbf5fSPeter Ujfalusi "UB926_LOCK", "UB926_PWR_SW_CNTRL", 3122eefbf5fSPeter Ujfalusi "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 313e25889f8SVignesh Raghavendra }; 314e25889f8SVignesh Raghavendra}; 315a2178b83SFaiz Abbas 316a2178b83SFaiz Abbas&main_sdhci0 { 317a2178b83SFaiz Abbas /* eMMC */ 318a2178b83SFaiz Abbas non-removable; 319a2178b83SFaiz Abbas ti,driver-strength-ohm = <50>; 320a2178b83SFaiz Abbas disable-wp; 321a2178b83SFaiz Abbas}; 322a2178b83SFaiz Abbas 323a2178b83SFaiz Abbas&main_sdhci1 { 324a2178b83SFaiz Abbas /* SD card */ 325a2178b83SFaiz Abbas pinctrl-0 = <&main_mmc1_pins_default>; 326a2178b83SFaiz Abbas pinctrl-names = "default"; 32794374990SAswath Govindraju vmmc-supply = <&vdd_mmc1>; 32894374990SAswath Govindraju vqmmc-supply = <&vdd_sd_dv>; 329a2178b83SFaiz Abbas ti,driver-strength-ohm = <50>; 330a2178b83SFaiz Abbas disable-wp; 331a2178b83SFaiz Abbas}; 332e38a45b0SKishon Vijay Abraham I 333e38a45b0SKishon Vijay Abraham I&serdes_ln_ctrl { 334e38a45b0SKishon Vijay Abraham I idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 335e38a45b0SKishon Vijay Abraham I <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 336e38a45b0SKishon Vijay Abraham I}; 337bbcb0522SRoger Quadros 338bbcb0522SRoger Quadros&usb_serdes_mux { 339bbcb0522SRoger Quadros idle-states = <1>; /* USB0 to SERDES lane 3 */ 340bbcb0522SRoger Quadros}; 341bbcb0522SRoger Quadros 342bbcb0522SRoger Quadros&usbss0 { 343bbcb0522SRoger Quadros pinctrl-names = "default"; 344bbcb0522SRoger Quadros pinctrl-0 = <&main_usbss0_pins_default>; 345bbcb0522SRoger Quadros ti,vbus-divider; 346bbcb0522SRoger Quadros ti,usb2-only; 347bbcb0522SRoger Quadros}; 348bbcb0522SRoger Quadros 349bbcb0522SRoger Quadros&usb0 { 350bbcb0522SRoger Quadros dr_mode = "otg"; 351bbcb0522SRoger Quadros maximum-speed = "high-speed"; 352bbcb0522SRoger Quadros}; 353e6b45168SVignesh Raghavendra 354e6b45168SVignesh Raghavendra&tscadc0 { 355e6b45168SVignesh Raghavendra adc { 356e6b45168SVignesh Raghavendra ti,adc-channels = <0 1 2 3 4 5 6 7>; 357e6b45168SVignesh Raghavendra }; 358e6b45168SVignesh Raghavendra}; 359429c0259SKishon Vijay Abraham I 360429c0259SKishon Vijay Abraham I&serdes_refclk { 361429c0259SKishon Vijay Abraham I clock-frequency = <100000000>; 362429c0259SKishon Vijay Abraham I}; 363429c0259SKishon Vijay Abraham I 364429c0259SKishon Vijay Abraham I&serdes0 { 365429c0259SKishon Vijay Abraham I serdes0_pcie_link: phy@0 { 366429c0259SKishon Vijay Abraham I reg = <0>; 367429c0259SKishon Vijay Abraham I cdns,num-lanes = <2>; 368429c0259SKishon Vijay Abraham I #phy-cells = <0>; 369429c0259SKishon Vijay Abraham I cdns,phy-type = <PHY_TYPE_PCIE>; 370429c0259SKishon Vijay Abraham I resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 371429c0259SKishon Vijay Abraham I }; 372429c0259SKishon Vijay Abraham I 373429c0259SKishon Vijay Abraham I serdes0_qsgmii_link: phy@1 { 374429c0259SKishon Vijay Abraham I reg = <2>; 375429c0259SKishon Vijay Abraham I cdns,num-lanes = <1>; 376429c0259SKishon Vijay Abraham I #phy-cells = <0>; 377429c0259SKishon Vijay Abraham I cdns,phy-type = <PHY_TYPE_QSGMII>; 378429c0259SKishon Vijay Abraham I resets = <&serdes_wiz0 3>; 379429c0259SKishon Vijay Abraham I }; 380429c0259SKishon Vijay Abraham I}; 3813a6319dfSKishon Vijay Abraham I 3823a6319dfSKishon Vijay Abraham I&pcie1_rc { 3833a6319dfSKishon Vijay Abraham I reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 3843a6319dfSKishon Vijay Abraham I phys = <&serdes0_pcie_link>; 3853a6319dfSKishon Vijay Abraham I phy-names = "pcie-phy"; 3863a6319dfSKishon Vijay Abraham I num-lanes = <2>; 3873a6319dfSKishon Vijay Abraham I}; 3883a6319dfSKishon Vijay Abraham I 3893a6319dfSKishon Vijay Abraham I&pcie1_ep { 3903a6319dfSKishon Vijay Abraham I phys = <&serdes0_pcie_link>; 3913a6319dfSKishon Vijay Abraham I phy-names = "pcie-phy"; 3923a6319dfSKishon Vijay Abraham I num-lanes = <2>; 3933a6319dfSKishon Vijay Abraham I status = "disabled"; 3943a6319dfSKishon Vijay Abraham I}; 395