1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_conf: scm-conf@40f00000 { 10 compatible = "syscon", "simple-mfd"; 11 reg = <0x0 0x40f00000 0x0 0x20000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x40f00000 0x20000>; 15 16 phy_gmii_sel: phy@4040 { 17 compatible = "ti,am654-phy-gmii-sel"; 18 reg = <0x4040 0x4>; 19 #phy-cells = <1>; 20 }; 21 }; 22 23 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 24 mcu_timerio_input: pinctrl@40f04200 { 25 compatible = "pinctrl-single"; 26 reg = <0x0 0x40f04200 0x0 0x10>; 27 #pinctrl-cells = <1>; 28 pinctrl-single,register-width = <32>; 29 pinctrl-single,function-mask = <0x00000101>; 30 }; 31 32 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 33 mcu_timerio_output: pinctrl@40f04280 { 34 compatible = "pinctrl-single"; 35 reg = <0x0 0x40f04280 0x0 0x8>; 36 #pinctrl-cells = <1>; 37 pinctrl-single,register-width = <32>; 38 pinctrl-single,function-mask = <0x00000003>; 39 }; 40 41 mcu_uart0: serial@40a00000 { 42 compatible = "ti,am654-uart"; 43 reg = <0x00 0x40a00000 0x00 0x100>; 44 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 45 clock-frequency = <96000000>; 46 current-speed = <115200>; 47 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 48 status = "disabled"; 49 }; 50 51 mcu_ram: sram@41c00000 { 52 compatible = "mmio-sram"; 53 reg = <0x00 0x41c00000 0x00 0x80000>; 54 ranges = <0x0 0x00 0x41c00000 0x80000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 }; 58 59 mcu_i2c0: i2c@40b00000 { 60 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 61 reg = <0x0 0x40b00000 0x0 0x100>; 62 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 clock-names = "fck"; 66 clocks = <&k3_clks 114 1>; 67 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 68 status = "disabled"; 69 }; 70 71 mcu_spi0: spi@40300000 { 72 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 73 reg = <0x0 0x40300000 0x0 0x400>; 74 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 75 clocks = <&k3_clks 142 1>; 76 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 status = "disabled"; 80 }; 81 82 mcu_spi1: spi@40310000 { 83 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 84 reg = <0x0 0x40310000 0x0 0x400>; 85 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 86 clocks = <&k3_clks 143 1>; 87 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 status = "disabled"; 91 }; 92 93 mcu_spi2: spi@40320000 { 94 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 95 reg = <0x0 0x40320000 0x0 0x400>; 96 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&k3_clks 144 1>; 98 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 status = "disabled"; 102 }; 103 104 tscadc0: tscadc@40200000 { 105 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 106 reg = <0x0 0x40200000 0x0 0x1000>; 107 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&k3_clks 0 2>; 109 assigned-clocks = <&k3_clks 0 2>; 110 assigned-clock-rates = <60000000>; 111 clock-names = "fck"; 112 dmas = <&mcu_udmap 0x7100>, 113 <&mcu_udmap 0x7101 >; 114 dma-names = "fifo0", "fifo1"; 115 116 adc { 117 #io-channel-cells = <1>; 118 compatible = "ti,am654-adc", "ti,am3359-adc"; 119 }; 120 }; 121 122 tscadc1: tscadc@40210000 { 123 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 124 reg = <0x0 0x40210000 0x0 0x1000>; 125 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&k3_clks 1 2>; 127 assigned-clocks = <&k3_clks 1 2>; 128 assigned-clock-rates = <60000000>; 129 clock-names = "fck"; 130 dmas = <&mcu_udmap 0x7102>, 131 <&mcu_udmap 0x7103>; 132 dma-names = "fifo0", "fifo1"; 133 134 adc { 135 #io-channel-cells = <1>; 136 compatible = "ti,am654-adc", "ti,am3359-adc"; 137 }; 138 }; 139 140 /* 141 * The MCU domain timer interrupts are routed only to the ESM module, 142 * and not currently available for Linux. The MCU domain timers are 143 * of limited use without interrupts, and likely reserved by the ESM. 144 */ 145 mcu_timer0: timer@40400000 { 146 compatible = "ti,am654-timer"; 147 reg = <0x00 0x40400000 0x00 0x400>; 148 clocks = <&k3_clks 35 0>; 149 clock-names = "fck"; 150 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 151 ti,timer-pwm; 152 status = "reserved"; 153 }; 154 155 mcu_timer1: timer@40410000 { 156 compatible = "ti,am654-timer"; 157 reg = <0x00 0x40410000 0x00 0x400>; 158 clocks = <&k3_clks 36 0>; 159 clock-names = "fck"; 160 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 161 ti,timer-pwm; 162 status = "reserved"; 163 }; 164 165 mcu_timer2: timer@40420000 { 166 compatible = "ti,am654-timer"; 167 reg = <0x00 0x40420000 0x00 0x400>; 168 clocks = <&k3_clks 37 0>; 169 clock-names = "fck"; 170 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 171 ti,timer-pwm; 172 status = "reserved"; 173 }; 174 175 mcu_timer3: timer@40430000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x40430000 0x00 0x400>; 178 clocks = <&k3_clks 38 0>; 179 clock-names = "fck"; 180 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 181 ti,timer-pwm; 182 status = "reserved"; 183 }; 184 185 mcu_navss: bus@28380000 { 186 compatible = "simple-mfd"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 190 dma-coherent; 191 dma-ranges; 192 193 ti,sci-dev-id = <119>; 194 195 mcu_ringacc: ringacc@2b800000 { 196 compatible = "ti,am654-navss-ringacc"; 197 reg = <0x0 0x2b800000 0x0 0x400000>, 198 <0x0 0x2b000000 0x0 0x400000>, 199 <0x0 0x28590000 0x0 0x100>, 200 <0x0 0x2a500000 0x0 0x40000>; 201 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 202 ti,num-rings = <286>; 203 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 204 ti,sci = <&dmsc>; 205 ti,sci-dev-id = <195>; 206 msi-parent = <&inta_main_udmass>; 207 }; 208 209 mcu_udmap: dma-controller@285c0000 { 210 compatible = "ti,am654-navss-mcu-udmap"; 211 reg = <0x0 0x285c0000 0x0 0x100>, 212 <0x0 0x2a800000 0x0 0x40000>, 213 <0x0 0x2aa00000 0x0 0x40000>; 214 reg-names = "gcfg", "rchanrt", "tchanrt"; 215 msi-parent = <&inta_main_udmass>; 216 #dma-cells = <1>; 217 218 ti,sci = <&dmsc>; 219 ti,sci-dev-id = <194>; 220 ti,ringacc = <&mcu_ringacc>; 221 222 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 223 <0xd>; /* TX_CHAN */ 224 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 225 <0xa>; /* RX_CHAN */ 226 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 227 }; 228 }; 229 230 m_can0: mcan@40528000 { 231 compatible = "bosch,m_can"; 232 reg = <0x0 0x40528000 0x0 0x400>, 233 <0x0 0x40500000 0x0 0x4400>; 234 reg-names = "m_can", "message_ram"; 235 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 236 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; 237 clock-names = "hclk", "cclk"; 238 interrupt-parent = <&gic500>; 239 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 241 interrupt-names = "int0", "int1"; 242 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 243 status = "disabled"; 244 }; 245 246 m_can1: mcan@40568000 { 247 compatible = "bosch,m_can"; 248 reg = <0x0 0x40568000 0x0 0x400>, 249 <0x0 0x40540000 0x0 0x4400>; 250 reg-names = "m_can", "message_ram"; 251 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 252 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; 253 clock-names = "hclk", "cclk"; 254 interrupt-parent = <&gic500>; 255 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 257 interrupt-names = "int0", "int1"; 258 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 259 status = "disabled"; 260 }; 261 262 fss: fss@47000000 { 263 compatible = "simple-bus"; 264 #address-cells = <2>; 265 #size-cells = <2>; 266 ranges; 267 268 ospi0: spi@47040000 { 269 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 270 reg = <0x0 0x47040000 0x0 0x100>, 271 <0x5 0x00000000 0x1 0x0000000>; 272 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 273 cdns,fifo-depth = <256>; 274 cdns,fifo-width = <4>; 275 cdns,trigger-address = <0x0>; 276 clocks = <&k3_clks 248 0>; 277 assigned-clocks = <&k3_clks 248 0>; 278 assigned-clock-parents = <&k3_clks 248 2>; 279 assigned-clock-rates = <166666666>; 280 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 }; 284 285 ospi1: spi@47050000 { 286 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 287 reg = <0x0 0x47050000 0x0 0x100>, 288 <0x7 0x00000000 0x1 0x00000000>; 289 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 290 cdns,fifo-depth = <256>; 291 cdns,fifo-width = <4>; 292 cdns,trigger-address = <0x0>; 293 clocks = <&k3_clks 249 6>; 294 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 }; 298 }; 299 300 mcu_cpsw: ethernet@46000000 { 301 compatible = "ti,am654-cpsw-nuss"; 302 #address-cells = <2>; 303 #size-cells = <2>; 304 reg = <0x0 0x46000000 0x0 0x200000>; 305 reg-names = "cpsw_nuss"; 306 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 307 dma-coherent; 308 clocks = <&k3_clks 5 10>; 309 clock-names = "fck"; 310 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 311 312 dmas = <&mcu_udmap 0xf000>, 313 <&mcu_udmap 0xf001>, 314 <&mcu_udmap 0xf002>, 315 <&mcu_udmap 0xf003>, 316 <&mcu_udmap 0xf004>, 317 <&mcu_udmap 0xf005>, 318 <&mcu_udmap 0xf006>, 319 <&mcu_udmap 0xf007>, 320 <&mcu_udmap 0x7000>; 321 dma-names = "tx0", "tx1", "tx2", "tx3", 322 "tx4", "tx5", "tx6", "tx7", 323 "rx"; 324 325 ethernet-ports { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 cpsw_port1: port@1 { 330 reg = <1>; 331 ti,mac-only; 332 label = "port1"; 333 ti,syscon-efuse = <&mcu_conf 0x200>; 334 phys = <&phy_gmii_sel 1>; 335 }; 336 }; 337 338 davinci_mdio: mdio@f00 { 339 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 340 reg = <0x0 0xf00 0x0 0x100>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 clocks = <&k3_clks 5 10>; 344 clock-names = "fck"; 345 bus_freq = <1000000>; 346 status = "disabled"; 347 }; 348 349 cpts@3d000 { 350 compatible = "ti,am65-cpts"; 351 reg = <0x0 0x3d000 0x0 0x400>; 352 clocks = <&mcu_cpsw_cpts_mux>; 353 clock-names = "cpts"; 354 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "cpts"; 356 ti,cpts-ext-ts-inputs = <4>; 357 ti,cpts-periodic-outputs = <2>; 358 359 mcu_cpsw_cpts_mux: refclk-mux { 360 #clock-cells = <0>; 361 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 362 <&k3_clks 118 6>, <&k3_clks 118 3>, 363 <&k3_clks 118 8>, <&k3_clks 118 14>, 364 <&k3_clks 120 3>, <&k3_clks 121 3>; 365 assigned-clocks = <&mcu_cpsw_cpts_mux>; 366 assigned-clock-parents = <&k3_clks 118 5>; 367 }; 368 }; 369 }; 370 371 mcu_r5fss0: r5fss@41000000 { 372 compatible = "ti,am654-r5fss"; 373 ti,cluster-mode = <1>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0x41000000 0x00 0x41000000 0x20000>, 377 <0x41400000 0x00 0x41400000 0x20000>; 378 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; 379 380 mcu_r5fss0_core0: r5f@41000000 { 381 compatible = "ti,am654-r5f"; 382 reg = <0x41000000 0x00008000>, 383 <0x41010000 0x00008000>; 384 reg-names = "atcm", "btcm"; 385 ti,sci = <&dmsc>; 386 ti,sci-dev-id = <159>; 387 ti,sci-proc-ids = <0x01 0xff>; 388 resets = <&k3_reset 159 1>; 389 firmware-name = "am65x-mcu-r5f0_0-fw"; 390 ti,atcm-enable = <1>; 391 ti,btcm-enable = <1>; 392 ti,loczrama = <1>; 393 }; 394 395 mcu_r5fss0_core1: r5f@41400000 { 396 compatible = "ti,am654-r5f"; 397 reg = <0x41400000 0x00008000>, 398 <0x41410000 0x00008000>; 399 reg-names = "atcm", "btcm"; 400 ti,sci = <&dmsc>; 401 ti,sci-dev-id = <245>; 402 ti,sci-proc-ids = <0x02 0xff>; 403 resets = <&k3_reset 245 1>; 404 firmware-name = "am65x-mcu-r5f0_1-fw"; 405 ti,atcm-enable = <1>; 406 ti,btcm-enable = <1>; 407 ti,loczrama = <1>; 408 }; 409 }; 410 411 mcu_rti1: watchdog@40610000 { 412 compatible = "ti,j7-rti-wdt"; 413 reg = <0x0 0x40610000 0x0 0x100>; 414 clocks = <&k3_clks 135 0>; 415 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; 416 assigned-clocks = <&k3_clks 135 0>; 417 assigned-clock-parents = <&k3_clks 135 4>; 418 }; 419}; 420