1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_conf: scm-conf@40f00000 { 10 compatible = "syscon", "simple-mfd"; 11 reg = <0x0 0x40f00000 0x0 0x20000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x40f00000 0x20000>; 15 16 phy_gmii_sel: phy@4040 { 17 compatible = "ti,am654-phy-gmii-sel"; 18 reg = <0x4040 0x4>; 19 #phy-cells = <1>; 20 }; 21 }; 22 23 mcu_uart0: serial@40a00000 { 24 compatible = "ti,am654-uart"; 25 reg = <0x00 0x40a00000 0x00 0x100>; 26 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 27 clock-frequency = <96000000>; 28 current-speed = <115200>; 29 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 30 status = "disabled"; 31 }; 32 33 mcu_ram: sram@41c00000 { 34 compatible = "mmio-sram"; 35 reg = <0x00 0x41c00000 0x00 0x80000>; 36 ranges = <0x0 0x00 0x41c00000 0x80000>; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 }; 40 41 mcu_i2c0: i2c@40b00000 { 42 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 43 reg = <0x0 0x40b00000 0x0 0x100>; 44 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 clock-names = "fck"; 48 clocks = <&k3_clks 114 1>; 49 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 50 status = "disabled"; 51 }; 52 53 mcu_spi0: spi@40300000 { 54 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 55 reg = <0x0 0x40300000 0x0 0x400>; 56 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 57 clocks = <&k3_clks 142 1>; 58 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 status = "disabled"; 62 }; 63 64 mcu_spi1: spi@40310000 { 65 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 66 reg = <0x0 0x40310000 0x0 0x400>; 67 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&k3_clks 143 1>; 69 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 status = "disabled"; 73 }; 74 75 mcu_spi2: spi@40320000 { 76 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 77 reg = <0x0 0x40320000 0x0 0x400>; 78 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 79 clocks = <&k3_clks 144 1>; 80 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 81 #address-cells = <1>; 82 #size-cells = <0>; 83 status = "disabled"; 84 }; 85 86 tscadc0: tscadc@40200000 { 87 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 88 reg = <0x0 0x40200000 0x0 0x1000>; 89 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&k3_clks 0 2>; 91 assigned-clocks = <&k3_clks 0 2>; 92 assigned-clock-rates = <60000000>; 93 clock-names = "fck"; 94 dmas = <&mcu_udmap 0x7100>, 95 <&mcu_udmap 0x7101 >; 96 dma-names = "fifo0", "fifo1"; 97 98 adc { 99 #io-channel-cells = <1>; 100 compatible = "ti,am654-adc", "ti,am3359-adc"; 101 }; 102 }; 103 104 tscadc1: tscadc@40210000 { 105 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 106 reg = <0x0 0x40210000 0x0 0x1000>; 107 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&k3_clks 1 2>; 109 assigned-clocks = <&k3_clks 1 2>; 110 assigned-clock-rates = <60000000>; 111 clock-names = "fck"; 112 dmas = <&mcu_udmap 0x7102>, 113 <&mcu_udmap 0x7103>; 114 dma-names = "fifo0", "fifo1"; 115 116 adc { 117 #io-channel-cells = <1>; 118 compatible = "ti,am654-adc", "ti,am3359-adc"; 119 }; 120 }; 121 122 mcu_navss: bus@28380000 { 123 compatible = "simple-mfd"; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 127 dma-coherent; 128 dma-ranges; 129 130 ti,sci-dev-id = <119>; 131 132 mcu_ringacc: ringacc@2b800000 { 133 compatible = "ti,am654-navss-ringacc"; 134 reg = <0x0 0x2b800000 0x0 0x400000>, 135 <0x0 0x2b000000 0x0 0x400000>, 136 <0x0 0x28590000 0x0 0x100>, 137 <0x0 0x2a500000 0x0 0x40000>; 138 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 139 ti,num-rings = <286>; 140 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 141 ti,sci = <&dmsc>; 142 ti,sci-dev-id = <195>; 143 msi-parent = <&inta_main_udmass>; 144 }; 145 146 mcu_udmap: dma-controller@285c0000 { 147 compatible = "ti,am654-navss-mcu-udmap"; 148 reg = <0x0 0x285c0000 0x0 0x100>, 149 <0x0 0x2a800000 0x0 0x40000>, 150 <0x0 0x2aa00000 0x0 0x40000>; 151 reg-names = "gcfg", "rchanrt", "tchanrt"; 152 msi-parent = <&inta_main_udmass>; 153 #dma-cells = <1>; 154 155 ti,sci = <&dmsc>; 156 ti,sci-dev-id = <194>; 157 ti,ringacc = <&mcu_ringacc>; 158 159 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 160 <0xd>; /* TX_CHAN */ 161 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 162 <0xa>; /* RX_CHAN */ 163 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 164 }; 165 }; 166 167 m_can0: mcan@40528000 { 168 compatible = "bosch,m_can"; 169 reg = <0x0 0x40528000 0x0 0x400>, 170 <0x0 0x40500000 0x0 0x4400>; 171 reg-names = "m_can", "message_ram"; 172 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 173 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; 174 clock-names = "hclk", "cclk"; 175 interrupt-parent = <&gic500>; 176 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = "int0", "int1"; 179 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 180 status = "disabled"; 181 }; 182 183 m_can1: mcan@40568000 { 184 compatible = "bosch,m_can"; 185 reg = <0x0 0x40568000 0x0 0x400>, 186 <0x0 0x40540000 0x0 0x4400>; 187 reg-names = "m_can", "message_ram"; 188 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 189 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; 190 clock-names = "hclk", "cclk"; 191 interrupt-parent = <&gic500>; 192 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "int0", "int1"; 195 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 196 status = "disabled"; 197 }; 198 199 fss: fss@47000000 { 200 compatible = "simple-bus"; 201 #address-cells = <2>; 202 #size-cells = <2>; 203 ranges; 204 205 ospi0: spi@47040000 { 206 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 207 reg = <0x0 0x47040000 0x0 0x100>, 208 <0x5 0x00000000 0x1 0x0000000>; 209 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 210 cdns,fifo-depth = <256>; 211 cdns,fifo-width = <4>; 212 cdns,trigger-address = <0x0>; 213 clocks = <&k3_clks 248 0>; 214 assigned-clocks = <&k3_clks 248 0>; 215 assigned-clock-parents = <&k3_clks 248 2>; 216 assigned-clock-rates = <166666666>; 217 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 }; 221 222 ospi1: spi@47050000 { 223 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 224 reg = <0x0 0x47050000 0x0 0x100>, 225 <0x7 0x00000000 0x1 0x00000000>; 226 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 227 cdns,fifo-depth = <256>; 228 cdns,fifo-width = <4>; 229 cdns,trigger-address = <0x0>; 230 clocks = <&k3_clks 249 6>; 231 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 }; 235 }; 236 237 mcu_cpsw: ethernet@46000000 { 238 compatible = "ti,am654-cpsw-nuss"; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 reg = <0x0 0x46000000 0x0 0x200000>; 242 reg-names = "cpsw_nuss"; 243 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 244 dma-coherent; 245 clocks = <&k3_clks 5 10>; 246 clock-names = "fck"; 247 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 248 249 dmas = <&mcu_udmap 0xf000>, 250 <&mcu_udmap 0xf001>, 251 <&mcu_udmap 0xf002>, 252 <&mcu_udmap 0xf003>, 253 <&mcu_udmap 0xf004>, 254 <&mcu_udmap 0xf005>, 255 <&mcu_udmap 0xf006>, 256 <&mcu_udmap 0xf007>, 257 <&mcu_udmap 0x7000>; 258 dma-names = "tx0", "tx1", "tx2", "tx3", 259 "tx4", "tx5", "tx6", "tx7", 260 "rx"; 261 262 ethernet-ports { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 266 cpsw_port1: port@1 { 267 reg = <1>; 268 ti,mac-only; 269 label = "port1"; 270 ti,syscon-efuse = <&mcu_conf 0x200>; 271 phys = <&phy_gmii_sel 1>; 272 }; 273 }; 274 275 davinci_mdio: mdio@f00 { 276 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 277 reg = <0x0 0xf00 0x0 0x100>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 clocks = <&k3_clks 5 10>; 281 clock-names = "fck"; 282 bus_freq = <1000000>; 283 status = "disabled"; 284 }; 285 286 cpts@3d000 { 287 compatible = "ti,am65-cpts"; 288 reg = <0x0 0x3d000 0x0 0x400>; 289 clocks = <&mcu_cpsw_cpts_mux>; 290 clock-names = "cpts"; 291 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-names = "cpts"; 293 ti,cpts-ext-ts-inputs = <4>; 294 ti,cpts-periodic-outputs = <2>; 295 296 mcu_cpsw_cpts_mux: refclk-mux { 297 #clock-cells = <0>; 298 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 299 <&k3_clks 118 6>, <&k3_clks 118 3>, 300 <&k3_clks 118 8>, <&k3_clks 118 14>, 301 <&k3_clks 120 3>, <&k3_clks 121 3>; 302 assigned-clocks = <&mcu_cpsw_cpts_mux>; 303 assigned-clock-parents = <&k3_clks 118 5>; 304 }; 305 }; 306 }; 307 308 mcu_r5fss0: r5fss@41000000 { 309 compatible = "ti,am654-r5fss"; 310 ti,cluster-mode = <1>; 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges = <0x41000000 0x00 0x41000000 0x20000>, 314 <0x41400000 0x00 0x41400000 0x20000>; 315 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; 316 317 mcu_r5fss0_core0: r5f@41000000 { 318 compatible = "ti,am654-r5f"; 319 reg = <0x41000000 0x00008000>, 320 <0x41010000 0x00008000>; 321 reg-names = "atcm", "btcm"; 322 ti,sci = <&dmsc>; 323 ti,sci-dev-id = <159>; 324 ti,sci-proc-ids = <0x01 0xff>; 325 resets = <&k3_reset 159 1>; 326 firmware-name = "am65x-mcu-r5f0_0-fw"; 327 ti,atcm-enable = <1>; 328 ti,btcm-enable = <1>; 329 ti,loczrama = <1>; 330 }; 331 332 mcu_r5fss0_core1: r5f@41400000 { 333 compatible = "ti,am654-r5f"; 334 reg = <0x41400000 0x00008000>, 335 <0x41410000 0x00008000>; 336 reg-names = "atcm", "btcm"; 337 ti,sci = <&dmsc>; 338 ti,sci-dev-id = <245>; 339 ti,sci-proc-ids = <0x02 0xff>; 340 resets = <&k3_reset 245 1>; 341 firmware-name = "am65x-mcu-r5f0_1-fw"; 342 ti,atcm-enable = <1>; 343 ti,btcm-enable = <1>; 344 ti,loczrama = <1>; 345 }; 346 }; 347 348 mcu_rti1: watchdog@40610000 { 349 compatible = "ti,j7-rti-wdt"; 350 reg = <0x0 0x40610000 0x0 0x100>; 351 clocks = <&k3_clks 135 0>; 352 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; 353 assigned-clocks = <&k3_clks 135 0>; 354 assigned-clock-parents = <&k3_clks 135 4>; 355 }; 356}; 357