1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals
4 *
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8&cbass_mcu {
9	mcu_conf: scm-conf@40f00000 {
10		compatible = "syscon", "simple-mfd";
11		reg = <0x0 0x40f00000 0x0 0x20000>;
12		#address-cells = <1>;
13		#size-cells = <1>;
14		ranges = <0x0 0x0 0x40f00000 0x20000>;
15
16		phy_gmii_sel: phy@4040 {
17			compatible = "ti,am654-phy-gmii-sel";
18			reg = <0x4040 0x4>;
19			#phy-cells = <1>;
20		};
21	};
22
23	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
24	mcu_timerio_input: pinctrl@40f04200 {
25		compatible = "pinctrl-single";
26		reg = <0x0 0x40f04200 0x0 0x10>;
27		#pinctrl-cells = <1>;
28		pinctrl-single,register-width = <32>;
29		pinctrl-single,function-mask = <0x00000101>;
30	};
31
32	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
33	mcu_timerio_output: pinctrl@40f04280 {
34		compatible = "pinctrl-single";
35		reg = <0x0 0x40f04280 0x0 0x8>;
36		#pinctrl-cells = <1>;
37		pinctrl-single,register-width = <32>;
38		pinctrl-single,function-mask = <0x00000003>;
39	};
40
41	mcu_uart0: serial@40a00000 {
42		compatible = "ti,am654-uart";
43		reg = <0x00 0x40a00000 0x00 0x100>;
44		interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
45		clock-frequency = <96000000>;
46		current-speed = <115200>;
47		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
48		status = "disabled";
49	};
50
51	mcu_ram: sram@41c00000 {
52		compatible = "mmio-sram";
53		reg = <0x00 0x41c00000 0x00 0x80000>;
54		ranges = <0x0 0x00 0x41c00000 0x80000>;
55		#address-cells = <1>;
56		#size-cells = <1>;
57	};
58
59	mcu_i2c0: i2c@40b00000 {
60		compatible = "ti,am654-i2c", "ti,omap4-i2c";
61		reg = <0x0 0x40b00000 0x0 0x100>;
62		interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
63		#address-cells = <1>;
64		#size-cells = <0>;
65		clock-names = "fck";
66		clocks = <&k3_clks 114 1>;
67		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
68		status = "disabled";
69	};
70
71	mcu_spi0: spi@40300000 {
72		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
73		reg = <0x0 0x40300000 0x0 0x400>;
74		interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
75		clocks = <&k3_clks 142 1>;
76		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
77		#address-cells = <1>;
78		#size-cells = <0>;
79		status = "disabled";
80	};
81
82	mcu_spi1: spi@40310000 {
83		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
84		reg = <0x0 0x40310000 0x0 0x400>;
85		interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
86		clocks = <&k3_clks 143 1>;
87		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
88		#address-cells = <1>;
89		#size-cells = <0>;
90		status = "disabled";
91	};
92
93	mcu_spi2: spi@40320000 {
94		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
95		reg = <0x0 0x40320000 0x0 0x400>;
96		interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
97		clocks = <&k3_clks 144 1>;
98		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
99		#address-cells = <1>;
100		#size-cells = <0>;
101		status = "disabled";
102	};
103
104	tscadc0: tscadc@40200000 {
105		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
106		reg = <0x0 0x40200000 0x0 0x1000>;
107		interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
108		clocks = <&k3_clks 0 2>;
109		assigned-clocks = <&k3_clks 0 2>;
110		assigned-clock-rates = <60000000>;
111		clock-names = "fck";
112		dmas = <&mcu_udmap 0x7100>,
113			<&mcu_udmap 0x7101 >;
114		dma-names = "fifo0", "fifo1";
115
116		adc {
117			#io-channel-cells = <1>;
118			compatible = "ti,am654-adc", "ti,am3359-adc";
119		};
120	};
121
122	tscadc1: tscadc@40210000 {
123		compatible = "ti,am654-tscadc", "ti,am3359-tscadc";
124		reg = <0x0 0x40210000 0x0 0x1000>;
125		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
126		clocks = <&k3_clks 1 2>;
127		assigned-clocks = <&k3_clks 1 2>;
128		assigned-clock-rates = <60000000>;
129		clock-names = "fck";
130		dmas = <&mcu_udmap 0x7102>,
131			<&mcu_udmap 0x7103>;
132		dma-names = "fifo0", "fifo1";
133
134		adc {
135			#io-channel-cells = <1>;
136			compatible = "ti,am654-adc", "ti,am3359-adc";
137		};
138	};
139
140	/*
141	 * The MCU domain timer interrupts are routed only to the ESM module,
142	 * and not currently available for Linux. The MCU domain timers are
143	 * of limited use without interrupts, and likely reserved by the ESM.
144	 */
145	mcu_timer0: timer@40400000 {
146		compatible = "ti,am654-timer";
147		reg = <0x00 0x40400000 0x00 0x400>;
148		clocks = <&k3_clks 35 0>;
149		clock-names = "fck";
150		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
151		ti,timer-pwm;
152		status = "reserved";
153	};
154
155	mcu_timer1: timer@40410000 {
156		compatible = "ti,am654-timer";
157		reg = <0x00 0x40410000 0x00 0x400>;
158		clocks = <&k3_clks 36 0>;
159		clock-names = "fck";
160		power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
161		ti,timer-pwm;
162		status = "reserved";
163	};
164
165	mcu_timer2: timer@40420000 {
166		compatible = "ti,am654-timer";
167		reg = <0x00 0x40420000 0x00 0x400>;
168		clocks = <&k3_clks 37 0>;
169		clock-names = "fck";
170		power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
171		ti,timer-pwm;
172		status = "reserved";
173	};
174
175	mcu_timer3: timer@40430000 {
176		compatible = "ti,am654-timer";
177		reg = <0x00 0x40430000 0x00 0x400>;
178		clocks = <&k3_clks 38 0>;
179		clock-names = "fck";
180		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
181		ti,timer-pwm;
182		status = "reserved";
183	};
184
185	mcu_navss: bus@28380000 {
186		compatible = "simple-mfd";
187		#address-cells = <2>;
188		#size-cells = <2>;
189		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
190		dma-coherent;
191		dma-ranges;
192
193		ti,sci-dev-id = <119>;
194
195		mcu_ringacc: ringacc@2b800000 {
196			compatible = "ti,am654-navss-ringacc";
197			reg = <0x0 0x2b800000 0x0 0x400000>,
198			      <0x0 0x2b000000 0x0 0x400000>,
199			      <0x0 0x28590000 0x0 0x100>,
200			      <0x0 0x2a500000 0x0 0x40000>,
201			      <0x0 0x28440000 0x0 0x40000>;
202			reg-names = "rt", "fifos", "proxy_gcfg",
203				    "proxy_target", "cfg";
204			ti,num-rings = <286>;
205			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
206			ti,sci = <&dmsc>;
207			ti,sci-dev-id = <195>;
208			msi-parent = <&inta_main_udmass>;
209		};
210
211		mcu_udmap: dma-controller@285c0000 {
212			compatible = "ti,am654-navss-mcu-udmap";
213			reg = <0x0 0x285c0000 0x0 0x100>,
214			      <0x0 0x2a800000 0x0 0x40000>,
215			      <0x0 0x2aa00000 0x0 0x40000>;
216			reg-names = "gcfg", "rchanrt", "tchanrt";
217			msi-parent = <&inta_main_udmass>;
218			#dma-cells = <1>;
219
220			ti,sci = <&dmsc>;
221			ti,sci-dev-id = <194>;
222			ti,ringacc = <&mcu_ringacc>;
223
224			ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
225						<0xd>; /* TX_CHAN */
226			ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
227						<0xa>; /* RX_CHAN */
228			ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
229		};
230	};
231
232	secure_proxy_mcu: mailbox@2a480000 {
233		compatible = "ti,am654-secure-proxy";
234		#mbox-cells = <1>;
235		reg-names = "target_data", "rt", "scfg";
236		reg = <0x0 0x2a480000 0x0 0x80000>,
237		      <0x0 0x2a380000 0x0 0x80000>,
238		      <0x0 0x2a400000 0x0 0x80000>;
239		/*
240		 * Marked Disabled:
241		 * Node is incomplete as it is meant for bootloaders and
242		 * firmware on non-MPU processors
243		 */
244		status = "disabled";
245	};
246
247	m_can0: can@40528000 {
248		compatible = "bosch,m_can";
249		reg = <0x0 0x40528000 0x0 0x400>,
250		      <0x0 0x40500000 0x0 0x4400>;
251		reg-names = "m_can", "message_ram";
252		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
253		clocks = <&k3_clks 102 5>, <&k3_clks 102 0>;
254		clock-names = "hclk", "cclk";
255		interrupt-parent = <&gic500>;
256		interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
257			     <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
258		interrupt-names = "int0", "int1";
259		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
260		status = "disabled";
261	};
262
263	m_can1: can@40568000 {
264		compatible = "bosch,m_can";
265		reg = <0x0 0x40568000 0x0 0x400>,
266		      <0x0 0x40540000 0x0 0x4400>;
267		reg-names = "m_can", "message_ram";
268		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
269		clocks = <&k3_clks 103 5>, <&k3_clks 103 0>;
270		clock-names = "hclk", "cclk";
271		interrupt-parent = <&gic500>;
272		interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
273			     <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
274		interrupt-names = "int0", "int1";
275		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
276		status = "disabled";
277	};
278
279	fss: fss@47000000 {
280		compatible = "simple-bus";
281		#address-cells = <2>;
282		#size-cells = <2>;
283		ranges;
284
285		ospi0: spi@47040000 {
286			compatible = "ti,am654-ospi", "cdns,qspi-nor";
287			reg = <0x0 0x47040000 0x0 0x100>,
288				<0x5 0x00000000 0x1 0x0000000>;
289			interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
290			cdns,fifo-depth = <256>;
291			cdns,fifo-width = <4>;
292			cdns,trigger-address = <0x0>;
293			clocks = <&k3_clks 248 0>;
294			assigned-clocks = <&k3_clks 248 0>;
295			assigned-clock-parents = <&k3_clks 248 2>;
296			assigned-clock-rates = <166666666>;
297			power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
298			#address-cells = <1>;
299			#size-cells = <0>;
300		};
301
302		ospi1: spi@47050000 {
303			compatible = "ti,am654-ospi", "cdns,qspi-nor";
304			reg = <0x0 0x47050000 0x0 0x100>,
305				<0x7 0x00000000 0x1 0x00000000>;
306			interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
307			cdns,fifo-depth = <256>;
308			cdns,fifo-width = <4>;
309			cdns,trigger-address = <0x0>;
310			clocks = <&k3_clks 249 6>;
311			power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
312			#address-cells = <1>;
313			#size-cells = <0>;
314		};
315	};
316
317	mcu_cpsw: ethernet@46000000 {
318		compatible = "ti,am654-cpsw-nuss";
319		#address-cells = <2>;
320		#size-cells = <2>;
321		reg = <0x0 0x46000000 0x0 0x200000>;
322		reg-names = "cpsw_nuss";
323		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
324		dma-coherent;
325		clocks = <&k3_clks 5 10>;
326		clock-names = "fck";
327		power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
328
329		dmas = <&mcu_udmap 0xf000>,
330		       <&mcu_udmap 0xf001>,
331		       <&mcu_udmap 0xf002>,
332		       <&mcu_udmap 0xf003>,
333		       <&mcu_udmap 0xf004>,
334		       <&mcu_udmap 0xf005>,
335		       <&mcu_udmap 0xf006>,
336		       <&mcu_udmap 0xf007>,
337		       <&mcu_udmap 0x7000>;
338		dma-names = "tx0", "tx1", "tx2", "tx3",
339			    "tx4", "tx5", "tx6", "tx7",
340			    "rx";
341
342		ethernet-ports {
343			#address-cells = <1>;
344			#size-cells = <0>;
345
346			cpsw_port1: port@1 {
347				reg = <1>;
348				ti,mac-only;
349				label = "port1";
350				ti,syscon-efuse = <&mcu_conf 0x200>;
351				phys = <&phy_gmii_sel 1>;
352			};
353		};
354
355		davinci_mdio: mdio@f00 {
356			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
357			reg = <0x0 0xf00 0x0 0x100>;
358			#address-cells = <1>;
359			#size-cells = <0>;
360			clocks = <&k3_clks 5 10>;
361			clock-names = "fck";
362			bus_freq = <1000000>;
363			status = "disabled";
364		};
365
366		cpts@3d000 {
367			compatible = "ti,am65-cpts";
368			reg = <0x0 0x3d000 0x0 0x400>;
369			clocks = <&mcu_cpsw_cpts_mux>;
370			clock-names = "cpts";
371			interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
372			interrupt-names = "cpts";
373			ti,cpts-ext-ts-inputs = <4>;
374			ti,cpts-periodic-outputs = <2>;
375
376			mcu_cpsw_cpts_mux: refclk-mux {
377				#clock-cells = <0>;
378				clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
379					<&k3_clks 118 6>, <&k3_clks 118 3>,
380					<&k3_clks 118 8>, <&k3_clks 118 14>,
381					<&k3_clks 120 3>, <&k3_clks 121 3>;
382				assigned-clocks = <&mcu_cpsw_cpts_mux>;
383				assigned-clock-parents = <&k3_clks 118 5>;
384			};
385		};
386	};
387
388	mcu_r5fss0: r5fss@41000000 {
389		compatible = "ti,am654-r5fss";
390		ti,cluster-mode = <1>;
391		#address-cells = <1>;
392		#size-cells = <1>;
393		ranges = <0x41000000 0x00 0x41000000 0x20000>,
394			 <0x41400000 0x00 0x41400000 0x20000>;
395		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
396
397		mcu_r5fss0_core0: r5f@41000000 {
398			compatible = "ti,am654-r5f";
399			reg = <0x41000000 0x00008000>,
400			      <0x41010000 0x00008000>;
401			reg-names = "atcm", "btcm";
402			ti,sci = <&dmsc>;
403			ti,sci-dev-id = <159>;
404			ti,sci-proc-ids = <0x01 0xff>;
405			resets = <&k3_reset 159 1>;
406			firmware-name = "am65x-mcu-r5f0_0-fw";
407			ti,atcm-enable = <1>;
408			ti,btcm-enable = <1>;
409			ti,loczrama = <1>;
410		};
411
412		mcu_r5fss0_core1: r5f@41400000 {
413			compatible = "ti,am654-r5f";
414			reg = <0x41400000 0x00008000>,
415			      <0x41410000 0x00008000>;
416			reg-names = "atcm", "btcm";
417			ti,sci = <&dmsc>;
418			ti,sci-dev-id = <245>;
419			ti,sci-proc-ids = <0x02 0xff>;
420			resets = <&k3_reset 245 1>;
421			firmware-name = "am65x-mcu-r5f0_1-fw";
422			ti,atcm-enable = <1>;
423			ti,btcm-enable = <1>;
424			ti,loczrama = <1>;
425		};
426	};
427
428	mcu_rti1: watchdog@40610000 {
429		compatible = "ti,j7-rti-wdt";
430		reg = <0x0 0x40610000 0x0 0x100>;
431		clocks = <&k3_clks 135 0>;
432		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
433		assigned-clocks = <&k3_clks 135 0>;
434		assigned-clock-parents = <&k3_clks 135 4>;
435	};
436};
437