14201af25SNishanth Menon// SPDX-License-Identifier: GPL-2.0 24201af25SNishanth Menon/* 34201af25SNishanth Menon * Device Tree Source for AM6 SoC Family MCU Domain peripherals 44201af25SNishanth Menon * 54201af25SNishanth Menon * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 64201af25SNishanth Menon */ 74201af25SNishanth Menon 84201af25SNishanth Menon&cbass_mcu { 94201af25SNishanth Menon mcu_uart0: serial@40a00000 { 104201af25SNishanth Menon compatible = "ti,am654-uart"; 114201af25SNishanth Menon reg = <0x00 0x40a00000 0x00 0x100>; 124201af25SNishanth Menon reg-shift = <2>; 134201af25SNishanth Menon reg-io-width = <4>; 144201af25SNishanth Menon interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 154201af25SNishanth Menon clock-frequency = <96000000>; 164201af25SNishanth Menon current-speed = <115200>; 17c68272cbSLokesh Vutla power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 184201af25SNishanth Menon }; 1919a1768fSVignesh R 20f853f005SSuman Anna mcu_ram: sram@41c00000 { 21f853f005SSuman Anna compatible = "mmio-sram"; 22f853f005SSuman Anna reg = <0x00 0x41c00000 0x00 0x80000>; 23f853f005SSuman Anna ranges = <0x0 0x00 0x41c00000 0x80000>; 24f853f005SSuman Anna #address-cells = <1>; 25f853f005SSuman Anna #size-cells = <1>; 26f853f005SSuman Anna }; 27f853f005SSuman Anna 2819a1768fSVignesh R mcu_i2c0: i2c@40b00000 { 2919a1768fSVignesh R compatible = "ti,am654-i2c", "ti,omap4-i2c"; 3019a1768fSVignesh R reg = <0x0 0x40b00000 0x0 0x100>; 3119a1768fSVignesh R interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 3219a1768fSVignesh R #address-cells = <1>; 3319a1768fSVignesh R #size-cells = <0>; 3419a1768fSVignesh R clock-names = "fck"; 3519a1768fSVignesh R clocks = <&k3_clks 114 1>; 36c68272cbSLokesh Vutla power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 3719a1768fSVignesh R }; 382cd7d393SVignesh R 392cd7d393SVignesh R mcu_spi0: spi@40300000 { 402cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 412cd7d393SVignesh R reg = <0x0 0x40300000 0x0 0x400>; 422cd7d393SVignesh R interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 432cd7d393SVignesh R clocks = <&k3_clks 142 1>; 44c68272cbSLokesh Vutla power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 452cd7d393SVignesh R #address-cells = <1>; 462cd7d393SVignesh R #size-cells = <0>; 472cd7d393SVignesh R }; 482cd7d393SVignesh R 492cd7d393SVignesh R mcu_spi1: spi@40310000 { 502cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 512cd7d393SVignesh R reg = <0x0 0x40310000 0x0 0x400>; 522cd7d393SVignesh R interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 532cd7d393SVignesh R clocks = <&k3_clks 143 1>; 54c68272cbSLokesh Vutla power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 552cd7d393SVignesh R #address-cells = <1>; 562cd7d393SVignesh R #size-cells = <0>; 572cd7d393SVignesh R }; 582cd7d393SVignesh R 592cd7d393SVignesh R mcu_spi2: spi@40320000 { 602cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 612cd7d393SVignesh R reg = <0x0 0x40320000 0x0 0x400>; 622cd7d393SVignesh R interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 632cd7d393SVignesh R clocks = <&k3_clks 144 1>; 64c68272cbSLokesh Vutla power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 652cd7d393SVignesh R #address-cells = <1>; 662cd7d393SVignesh R #size-cells = <0>; 672cd7d393SVignesh R }; 68aa6eaaa2SVignesh R 69aa6eaaa2SVignesh R tscadc0: tscadc@40200000 { 70aa6eaaa2SVignesh R compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 71aa6eaaa2SVignesh R reg = <0x0 0x40200000 0x0 0x1000>; 72aa6eaaa2SVignesh R interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 73aa6eaaa2SVignesh R clocks = <&k3_clks 0 2>; 74aa6eaaa2SVignesh R assigned-clocks = <&k3_clks 0 2>; 75aa6eaaa2SVignesh R assigned-clock-rates = <60000000>; 76aa6eaaa2SVignesh R clock-names = "adc_tsc_fck"; 77aa6eaaa2SVignesh R 78aa6eaaa2SVignesh R adc { 79aa6eaaa2SVignesh R #io-channel-cells = <1>; 80aa6eaaa2SVignesh R compatible = "ti,am654-adc", "ti,am3359-adc"; 81aa6eaaa2SVignesh R }; 82aa6eaaa2SVignesh R }; 83aa6eaaa2SVignesh R 84aa6eaaa2SVignesh R tscadc1: tscadc@40210000 { 85aa6eaaa2SVignesh R compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 86aa6eaaa2SVignesh R reg = <0x0 0x40210000 0x0 0x1000>; 87aa6eaaa2SVignesh R interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 88aa6eaaa2SVignesh R clocks = <&k3_clks 1 2>; 89aa6eaaa2SVignesh R assigned-clocks = <&k3_clks 1 2>; 90aa6eaaa2SVignesh R assigned-clock-rates = <60000000>; 91aa6eaaa2SVignesh R clock-names = "adc_tsc_fck"; 92aa6eaaa2SVignesh R 93aa6eaaa2SVignesh R adc { 94aa6eaaa2SVignesh R #io-channel-cells = <1>; 95aa6eaaa2SVignesh R compatible = "ti,am654-adc", "ti,am3359-adc"; 96aa6eaaa2SVignesh R }; 97aa6eaaa2SVignesh R }; 984201af25SNishanth Menon}; 99