14201af25SNishanth Menon// SPDX-License-Identifier: GPL-2.0 24201af25SNishanth Menon/* 34201af25SNishanth Menon * Device Tree Source for AM6 SoC Family MCU Domain peripherals 44201af25SNishanth Menon * 55bb9e0f6SSuman Anna * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 64201af25SNishanth Menon */ 74201af25SNishanth Menon 84201af25SNishanth Menon&cbass_mcu { 9e5c956c4SNishanth Menon mcu_conf: scm-conf@40f00000 { 10f2965b99SGrygorii Strashko compatible = "syscon", "simple-mfd"; 11f2965b99SGrygorii Strashko reg = <0x0 0x40f00000 0x0 0x20000>; 12f2965b99SGrygorii Strashko #address-cells = <1>; 13f2965b99SGrygorii Strashko #size-cells = <1>; 14f2965b99SGrygorii Strashko ranges = <0x0 0x0 0x40f00000 0x20000>; 15243246b5SGrygorii Strashko 16243246b5SGrygorii Strashko phy_gmii_sel: phy@4040 { 17243246b5SGrygorii Strashko compatible = "ti,am654-phy-gmii-sel"; 18243246b5SGrygorii Strashko reg = <0x4040 0x4>; 19243246b5SGrygorii Strashko #phy-cells = <1>; 20243246b5SGrygorii Strashko }; 21f2965b99SGrygorii Strashko }; 22f2965b99SGrygorii Strashko 234201af25SNishanth Menon mcu_uart0: serial@40a00000 { 244201af25SNishanth Menon compatible = "ti,am654-uart"; 254201af25SNishanth Menon reg = <0x00 0x40a00000 0x00 0x100>; 264201af25SNishanth Menon interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 274201af25SNishanth Menon clock-frequency = <96000000>; 284201af25SNishanth Menon current-speed = <115200>; 29c68272cbSLokesh Vutla power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 3065e8781aSAndrew Davis status = "disabled"; 314201af25SNishanth Menon }; 3219a1768fSVignesh R 33f853f005SSuman Anna mcu_ram: sram@41c00000 { 34f853f005SSuman Anna compatible = "mmio-sram"; 35f853f005SSuman Anna reg = <0x00 0x41c00000 0x00 0x80000>; 36f853f005SSuman Anna ranges = <0x0 0x00 0x41c00000 0x80000>; 37f853f005SSuman Anna #address-cells = <1>; 38f853f005SSuman Anna #size-cells = <1>; 39f853f005SSuman Anna }; 40f853f005SSuman Anna 4119a1768fSVignesh R mcu_i2c0: i2c@40b00000 { 4219a1768fSVignesh R compatible = "ti,am654-i2c", "ti,omap4-i2c"; 4319a1768fSVignesh R reg = <0x0 0x40b00000 0x0 0x100>; 4419a1768fSVignesh R interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 4519a1768fSVignesh R #address-cells = <1>; 4619a1768fSVignesh R #size-cells = <0>; 4719a1768fSVignesh R clock-names = "fck"; 4819a1768fSVignesh R clocks = <&k3_clks 114 1>; 49c68272cbSLokesh Vutla power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 50c0a5ba87SAndrew Davis status = "disabled"; 5119a1768fSVignesh R }; 522cd7d393SVignesh R 532cd7d393SVignesh R mcu_spi0: spi@40300000 { 542cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 552cd7d393SVignesh R reg = <0x0 0x40300000 0x0 0x400>; 562cd7d393SVignesh R interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 572cd7d393SVignesh R clocks = <&k3_clks 142 1>; 58c68272cbSLokesh Vutla power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 592cd7d393SVignesh R #address-cells = <1>; 602cd7d393SVignesh R #size-cells = <0>; 611c49cbb1SAndrew Davis status = "disabled"; 622cd7d393SVignesh R }; 632cd7d393SVignesh R 642cd7d393SVignesh R mcu_spi1: spi@40310000 { 652cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 662cd7d393SVignesh R reg = <0x0 0x40310000 0x0 0x400>; 672cd7d393SVignesh R interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 682cd7d393SVignesh R clocks = <&k3_clks 143 1>; 69c68272cbSLokesh Vutla power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 702cd7d393SVignesh R #address-cells = <1>; 712cd7d393SVignesh R #size-cells = <0>; 721c49cbb1SAndrew Davis status = "disabled"; 732cd7d393SVignesh R }; 742cd7d393SVignesh R 752cd7d393SVignesh R mcu_spi2: spi@40320000 { 762cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 772cd7d393SVignesh R reg = <0x0 0x40320000 0x0 0x400>; 782cd7d393SVignesh R interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 792cd7d393SVignesh R clocks = <&k3_clks 144 1>; 80c68272cbSLokesh Vutla power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 812cd7d393SVignesh R #address-cells = <1>; 822cd7d393SVignesh R #size-cells = <0>; 831c49cbb1SAndrew Davis status = "disabled"; 842cd7d393SVignesh R }; 85aa6eaaa2SVignesh R 86aa6eaaa2SVignesh R tscadc0: tscadc@40200000 { 87aa6eaaa2SVignesh R compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 88aa6eaaa2SVignesh R reg = <0x0 0x40200000 0x0 0x1000>; 89aa6eaaa2SVignesh R interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 90aa6eaaa2SVignesh R clocks = <&k3_clks 0 2>; 91aa6eaaa2SVignesh R assigned-clocks = <&k3_clks 0 2>; 92aa6eaaa2SVignesh R assigned-clock-rates = <60000000>; 93e5bad300SMatt Ranostay clock-names = "fck"; 9485800da0SVignesh Raghavendra dmas = <&mcu_udmap 0x7100>, 9585800da0SVignesh Raghavendra <&mcu_udmap 0x7101 >; 9685800da0SVignesh Raghavendra dma-names = "fifo0", "fifo1"; 97aa6eaaa2SVignesh R 98aa6eaaa2SVignesh R adc { 99aa6eaaa2SVignesh R #io-channel-cells = <1>; 100aa6eaaa2SVignesh R compatible = "ti,am654-adc", "ti,am3359-adc"; 101aa6eaaa2SVignesh R }; 102aa6eaaa2SVignesh R }; 103aa6eaaa2SVignesh R 104aa6eaaa2SVignesh R tscadc1: tscadc@40210000 { 105aa6eaaa2SVignesh R compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 106aa6eaaa2SVignesh R reg = <0x0 0x40210000 0x0 0x1000>; 107aa6eaaa2SVignesh R interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 108aa6eaaa2SVignesh R clocks = <&k3_clks 1 2>; 109aa6eaaa2SVignesh R assigned-clocks = <&k3_clks 1 2>; 110aa6eaaa2SVignesh R assigned-clock-rates = <60000000>; 111e5bad300SMatt Ranostay clock-names = "fck"; 11285800da0SVignesh Raghavendra dmas = <&mcu_udmap 0x7102>, 11385800da0SVignesh Raghavendra <&mcu_udmap 0x7103>; 11485800da0SVignesh Raghavendra dma-names = "fifo0", "fifo1"; 115aa6eaaa2SVignesh R 116aa6eaaa2SVignesh R adc { 117aa6eaaa2SVignesh R #io-channel-cells = <1>; 118aa6eaaa2SVignesh R compatible = "ti,am654-adc", "ti,am3359-adc"; 119aa6eaaa2SVignesh R }; 120aa6eaaa2SVignesh R }; 12107481770SVignesh Raghavendra 1229ecdb6d6SNishanth Menon mcu_navss: bus@28380000 { 1233d623054SPeter Ujfalusi compatible = "simple-mfd"; 1243d623054SPeter Ujfalusi #address-cells = <2>; 1253d623054SPeter Ujfalusi #size-cells = <2>; 1269ecdb6d6SNishanth Menon ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 1273d623054SPeter Ujfalusi dma-coherent; 1283d623054SPeter Ujfalusi dma-ranges; 1293d623054SPeter Ujfalusi 1303d623054SPeter Ujfalusi ti,sci-dev-id = <119>; 1313d623054SPeter Ujfalusi 1323d623054SPeter Ujfalusi mcu_ringacc: ringacc@2b800000 { 1333d623054SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 1343d623054SPeter Ujfalusi reg = <0x0 0x2b800000 0x0 0x400000>, 1353d623054SPeter Ujfalusi <0x0 0x2b000000 0x0 0x400000>, 1363d623054SPeter Ujfalusi <0x0 0x28590000 0x0 0x100>, 1373d623054SPeter Ujfalusi <0x0 0x2a500000 0x0 0x40000>; 1383d623054SPeter Ujfalusi reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 1393d623054SPeter Ujfalusi ti,num-rings = <286>; 1406da45875SLokesh Vutla ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 1413d623054SPeter Ujfalusi ti,sci = <&dmsc>; 1423d623054SPeter Ujfalusi ti,sci-dev-id = <195>; 1433d623054SPeter Ujfalusi msi-parent = <&inta_main_udmass>; 1443d623054SPeter Ujfalusi }; 1453d623054SPeter Ujfalusi 1463d623054SPeter Ujfalusi mcu_udmap: dma-controller@285c0000 { 1473d623054SPeter Ujfalusi compatible = "ti,am654-navss-mcu-udmap"; 1483d623054SPeter Ujfalusi reg = <0x0 0x285c0000 0x0 0x100>, 1493d623054SPeter Ujfalusi <0x0 0x2a800000 0x0 0x40000>, 1503d623054SPeter Ujfalusi <0x0 0x2aa00000 0x0 0x40000>; 1513d623054SPeter Ujfalusi reg-names = "gcfg", "rchanrt", "tchanrt"; 1523d623054SPeter Ujfalusi msi-parent = <&inta_main_udmass>; 1533d623054SPeter Ujfalusi #dma-cells = <1>; 1543d623054SPeter Ujfalusi 1553d623054SPeter Ujfalusi ti,sci = <&dmsc>; 1563d623054SPeter Ujfalusi ti,sci-dev-id = <194>; 1573d623054SPeter Ujfalusi ti,ringacc = <&mcu_ringacc>; 1583d623054SPeter Ujfalusi 1596da45875SLokesh Vutla ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 1606da45875SLokesh Vutla <0xd>; /* TX_CHAN */ 1616da45875SLokesh Vutla ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 1626da45875SLokesh Vutla <0xa>; /* RX_CHAN */ 1636da45875SLokesh Vutla ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 1643d623054SPeter Ujfalusi }; 1653d623054SPeter Ujfalusi }; 1663d623054SPeter Ujfalusi 167c3e4ea55SFaiz Abbas m_can0: mcan@40528000 { 168c3e4ea55SFaiz Abbas compatible = "bosch,m_can"; 169c3e4ea55SFaiz Abbas reg = <0x0 0x40528000 0x0 0x400>, 170c3e4ea55SFaiz Abbas <0x0 0x40500000 0x0 0x4400>; 171c3e4ea55SFaiz Abbas reg-names = "m_can", "message_ram"; 172c3e4ea55SFaiz Abbas power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 173c3e4ea55SFaiz Abbas clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; 174c3e4ea55SFaiz Abbas clock-names = "hclk", "cclk"; 175c3e4ea55SFaiz Abbas interrupt-parent = <&gic500>; 176c3e4ea55SFaiz Abbas interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 177c3e4ea55SFaiz Abbas <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 178c3e4ea55SFaiz Abbas interrupt-names = "int0", "int1"; 179c3e4ea55SFaiz Abbas bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 180*b08bf4a5SAndrew Davis status = "disabled"; 181c3e4ea55SFaiz Abbas }; 182c3e4ea55SFaiz Abbas 183c3e4ea55SFaiz Abbas m_can1: mcan@40568000 { 184c3e4ea55SFaiz Abbas compatible = "bosch,m_can"; 185c3e4ea55SFaiz Abbas reg = <0x0 0x40568000 0x0 0x400>, 186c3e4ea55SFaiz Abbas <0x0 0x40540000 0x0 0x4400>; 187c3e4ea55SFaiz Abbas reg-names = "m_can", "message_ram"; 188c3e4ea55SFaiz Abbas power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 189c3e4ea55SFaiz Abbas clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; 190c3e4ea55SFaiz Abbas clock-names = "hclk", "cclk"; 191c3e4ea55SFaiz Abbas interrupt-parent = <&gic500>; 192c3e4ea55SFaiz Abbas interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 193c3e4ea55SFaiz Abbas <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 194c3e4ea55SFaiz Abbas interrupt-names = "int0", "int1"; 195c3e4ea55SFaiz Abbas bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 196*b08bf4a5SAndrew Davis status = "disabled"; 197c3e4ea55SFaiz Abbas }; 198c3e4ea55SFaiz Abbas 19907481770SVignesh Raghavendra fss: fss@47000000 { 20007481770SVignesh Raghavendra compatible = "simple-bus"; 20107481770SVignesh Raghavendra #address-cells = <2>; 20207481770SVignesh Raghavendra #size-cells = <2>; 20307481770SVignesh Raghavendra ranges; 20407481770SVignesh Raghavendra 20507481770SVignesh Raghavendra ospi0: spi@47040000 { 20607481770SVignesh Raghavendra compatible = "ti,am654-ospi", "cdns,qspi-nor"; 20707481770SVignesh Raghavendra reg = <0x0 0x47040000 0x0 0x100>, 20807481770SVignesh Raghavendra <0x5 0x00000000 0x1 0x0000000>; 20907481770SVignesh Raghavendra interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 21007481770SVignesh Raghavendra cdns,fifo-depth = <256>; 21107481770SVignesh Raghavendra cdns,fifo-width = <4>; 21207481770SVignesh Raghavendra cdns,trigger-address = <0x0>; 21307481770SVignesh Raghavendra clocks = <&k3_clks 248 0>; 21407481770SVignesh Raghavendra assigned-clocks = <&k3_clks 248 0>; 21507481770SVignesh Raghavendra assigned-clock-parents = <&k3_clks 248 2>; 21607481770SVignesh Raghavendra assigned-clock-rates = <166666666>; 21707481770SVignesh Raghavendra power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 21807481770SVignesh Raghavendra #address-cells = <1>; 21907481770SVignesh Raghavendra #size-cells = <0>; 22007481770SVignesh Raghavendra }; 22107481770SVignesh Raghavendra 22207481770SVignesh Raghavendra ospi1: spi@47050000 { 22307481770SVignesh Raghavendra compatible = "ti,am654-ospi", "cdns,qspi-nor"; 22407481770SVignesh Raghavendra reg = <0x0 0x47050000 0x0 0x100>, 22507481770SVignesh Raghavendra <0x7 0x00000000 0x1 0x00000000>; 22607481770SVignesh Raghavendra interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 22707481770SVignesh Raghavendra cdns,fifo-depth = <256>; 22807481770SVignesh Raghavendra cdns,fifo-width = <4>; 22907481770SVignesh Raghavendra cdns,trigger-address = <0x0>; 23007481770SVignesh Raghavendra clocks = <&k3_clks 249 6>; 23107481770SVignesh Raghavendra power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 23207481770SVignesh Raghavendra #address-cells = <1>; 23307481770SVignesh Raghavendra #size-cells = <0>; 23407481770SVignesh Raghavendra }; 23507481770SVignesh Raghavendra }; 236ba86a6e9SGrygorii Strashko 237ba86a6e9SGrygorii Strashko mcu_cpsw: ethernet@46000000 { 238ba86a6e9SGrygorii Strashko compatible = "ti,am654-cpsw-nuss"; 239ba86a6e9SGrygorii Strashko #address-cells = <2>; 240ba86a6e9SGrygorii Strashko #size-cells = <2>; 241ba86a6e9SGrygorii Strashko reg = <0x0 0x46000000 0x0 0x200000>; 242ba86a6e9SGrygorii Strashko reg-names = "cpsw_nuss"; 243ba86a6e9SGrygorii Strashko ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 244ba86a6e9SGrygorii Strashko dma-coherent; 245ba86a6e9SGrygorii Strashko clocks = <&k3_clks 5 10>; 246ba86a6e9SGrygorii Strashko clock-names = "fck"; 247ba86a6e9SGrygorii Strashko power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 248ba86a6e9SGrygorii Strashko 249ba86a6e9SGrygorii Strashko dmas = <&mcu_udmap 0xf000>, 250ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf001>, 251ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf002>, 252ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf003>, 253ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf004>, 254ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf005>, 255ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf006>, 256ba86a6e9SGrygorii Strashko <&mcu_udmap 0xf007>, 257ba86a6e9SGrygorii Strashko <&mcu_udmap 0x7000>; 258ba86a6e9SGrygorii Strashko dma-names = "tx0", "tx1", "tx2", "tx3", 259ba86a6e9SGrygorii Strashko "tx4", "tx5", "tx6", "tx7", 260ba86a6e9SGrygorii Strashko "rx"; 261ba86a6e9SGrygorii Strashko 262ba86a6e9SGrygorii Strashko ethernet-ports { 263ba86a6e9SGrygorii Strashko #address-cells = <1>; 264ba86a6e9SGrygorii Strashko #size-cells = <0>; 265ba86a6e9SGrygorii Strashko 266ba86a6e9SGrygorii Strashko cpsw_port1: port@1 { 267ba86a6e9SGrygorii Strashko reg = <1>; 268ba86a6e9SGrygorii Strashko ti,mac-only; 269ba86a6e9SGrygorii Strashko label = "port1"; 270ba86a6e9SGrygorii Strashko ti,syscon-efuse = <&mcu_conf 0x200>; 271ba86a6e9SGrygorii Strashko phys = <&phy_gmii_sel 1>; 272ba86a6e9SGrygorii Strashko }; 273ba86a6e9SGrygorii Strashko }; 274ba86a6e9SGrygorii Strashko 275ba86a6e9SGrygorii Strashko davinci_mdio: mdio@f00 { 276ba86a6e9SGrygorii Strashko compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 277ba86a6e9SGrygorii Strashko reg = <0x0 0xf00 0x0 0x100>; 278ba86a6e9SGrygorii Strashko #address-cells = <1>; 279ba86a6e9SGrygorii Strashko #size-cells = <0>; 280ba86a6e9SGrygorii Strashko clocks = <&k3_clks 5 10>; 281ba86a6e9SGrygorii Strashko clock-names = "fck"; 282ba86a6e9SGrygorii Strashko bus_freq = <1000000>; 283c75c5c0bSAndrew Davis status = "disabled"; 284ba86a6e9SGrygorii Strashko }; 285885a26baSGrygorii Strashko 286ef2d1363SGrygorii Strashko cpts@3d000 { 287ef2d1363SGrygorii Strashko compatible = "ti,am65-cpts"; 288ef2d1363SGrygorii Strashko reg = <0x0 0x3d000 0x0 0x400>; 289885a26baSGrygorii Strashko clocks = <&mcu_cpsw_cpts_mux>; 290885a26baSGrygorii Strashko clock-names = "cpts"; 291885a26baSGrygorii Strashko interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; 292885a26baSGrygorii Strashko interrupt-names = "cpts"; 293885a26baSGrygorii Strashko ti,cpts-ext-ts-inputs = <4>; 294885a26baSGrygorii Strashko ti,cpts-periodic-outputs = <2>; 295885a26baSGrygorii Strashko 296885a26baSGrygorii Strashko mcu_cpsw_cpts_mux: refclk-mux { 297885a26baSGrygorii Strashko #clock-cells = <0>; 298885a26baSGrygorii Strashko clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 299885a26baSGrygorii Strashko <&k3_clks 118 6>, <&k3_clks 118 3>, 300885a26baSGrygorii Strashko <&k3_clks 118 8>, <&k3_clks 118 14>, 301885a26baSGrygorii Strashko <&k3_clks 120 3>, <&k3_clks 121 3>; 302885a26baSGrygorii Strashko assigned-clocks = <&mcu_cpsw_cpts_mux>; 303885a26baSGrygorii Strashko assigned-clock-parents = <&k3_clks 118 5>; 304885a26baSGrygorii Strashko }; 305885a26baSGrygorii Strashko }; 306ba86a6e9SGrygorii Strashko }; 3075bb9e0f6SSuman Anna 3085bb9e0f6SSuman Anna mcu_r5fss0: r5fss@41000000 { 3095bb9e0f6SSuman Anna compatible = "ti,am654-r5fss"; 3105bb9e0f6SSuman Anna ti,cluster-mode = <1>; 3115bb9e0f6SSuman Anna #address-cells = <1>; 3125bb9e0f6SSuman Anna #size-cells = <1>; 3135bb9e0f6SSuman Anna ranges = <0x41000000 0x00 0x41000000 0x20000>, 3145bb9e0f6SSuman Anna <0x41400000 0x00 0x41400000 0x20000>; 3155bb9e0f6SSuman Anna power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; 3165bb9e0f6SSuman Anna 3175bb9e0f6SSuman Anna mcu_r5fss0_core0: r5f@41000000 { 3185bb9e0f6SSuman Anna compatible = "ti,am654-r5f"; 3195bb9e0f6SSuman Anna reg = <0x41000000 0x00008000>, 3205bb9e0f6SSuman Anna <0x41010000 0x00008000>; 3215bb9e0f6SSuman Anna reg-names = "atcm", "btcm"; 3225bb9e0f6SSuman Anna ti,sci = <&dmsc>; 3235bb9e0f6SSuman Anna ti,sci-dev-id = <159>; 3245bb9e0f6SSuman Anna ti,sci-proc-ids = <0x01 0xff>; 3255bb9e0f6SSuman Anna resets = <&k3_reset 159 1>; 3265bb9e0f6SSuman Anna firmware-name = "am65x-mcu-r5f0_0-fw"; 3275bb9e0f6SSuman Anna ti,atcm-enable = <1>; 3285bb9e0f6SSuman Anna ti,btcm-enable = <1>; 3295bb9e0f6SSuman Anna ti,loczrama = <1>; 3305bb9e0f6SSuman Anna }; 3315bb9e0f6SSuman Anna 3325bb9e0f6SSuman Anna mcu_r5fss0_core1: r5f@41400000 { 3335bb9e0f6SSuman Anna compatible = "ti,am654-r5f"; 3345bb9e0f6SSuman Anna reg = <0x41400000 0x00008000>, 3355bb9e0f6SSuman Anna <0x41410000 0x00008000>; 3365bb9e0f6SSuman Anna reg-names = "atcm", "btcm"; 3375bb9e0f6SSuman Anna ti,sci = <&dmsc>; 3385bb9e0f6SSuman Anna ti,sci-dev-id = <245>; 3395bb9e0f6SSuman Anna ti,sci-proc-ids = <0x02 0xff>; 3405bb9e0f6SSuman Anna resets = <&k3_reset 245 1>; 3415bb9e0f6SSuman Anna firmware-name = "am65x-mcu-r5f0_1-fw"; 3425bb9e0f6SSuman Anna ti,atcm-enable = <1>; 3435bb9e0f6SSuman Anna ti,btcm-enable = <1>; 3445bb9e0f6SSuman Anna ti,loczrama = <1>; 3455bb9e0f6SSuman Anna }; 3465bb9e0f6SSuman Anna }; 3476674a90bSJan Kiszka 3486674a90bSJan Kiszka mcu_rti1: watchdog@40610000 { 3496674a90bSJan Kiszka compatible = "ti,j7-rti-wdt"; 3506674a90bSJan Kiszka reg = <0x0 0x40610000 0x0 0x100>; 3516674a90bSJan Kiszka clocks = <&k3_clks 135 0>; 3526674a90bSJan Kiszka power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; 3536674a90bSJan Kiszka assigned-clocks = <&k3_clks 135 0>; 3546674a90bSJan Kiszka assigned-clock-parents = <&k3_clks 135 4>; 3556674a90bSJan Kiszka }; 3564201af25SNishanth Menon}; 357