14201af25SNishanth Menon// SPDX-License-Identifier: GPL-2.0 24201af25SNishanth Menon/* 34201af25SNishanth Menon * Device Tree Source for AM6 SoC Family MCU Domain peripherals 44201af25SNishanth Menon * 54201af25SNishanth Menon * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 64201af25SNishanth Menon */ 74201af25SNishanth Menon 84201af25SNishanth Menon&cbass_mcu { 9f2965b99SGrygorii Strashko mcu_conf: scm_conf@40f00000 { 10f2965b99SGrygorii Strashko compatible = "syscon", "simple-mfd"; 11f2965b99SGrygorii Strashko reg = <0x0 0x40f00000 0x0 0x20000>; 12f2965b99SGrygorii Strashko #address-cells = <1>; 13f2965b99SGrygorii Strashko #size-cells = <1>; 14f2965b99SGrygorii Strashko ranges = <0x0 0x0 0x40f00000 0x20000>; 15243246b5SGrygorii Strashko 16243246b5SGrygorii Strashko phy_gmii_sel: phy@4040 { 17243246b5SGrygorii Strashko compatible = "ti,am654-phy-gmii-sel"; 18243246b5SGrygorii Strashko reg = <0x4040 0x4>; 19243246b5SGrygorii Strashko #phy-cells = <1>; 20243246b5SGrygorii Strashko }; 21f2965b99SGrygorii Strashko }; 22f2965b99SGrygorii Strashko 234201af25SNishanth Menon mcu_uart0: serial@40a00000 { 244201af25SNishanth Menon compatible = "ti,am654-uart"; 254201af25SNishanth Menon reg = <0x00 0x40a00000 0x00 0x100>; 264201af25SNishanth Menon reg-shift = <2>; 274201af25SNishanth Menon reg-io-width = <4>; 284201af25SNishanth Menon interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 294201af25SNishanth Menon clock-frequency = <96000000>; 304201af25SNishanth Menon current-speed = <115200>; 31c68272cbSLokesh Vutla power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 324201af25SNishanth Menon }; 3319a1768fSVignesh R 34f853f005SSuman Anna mcu_ram: sram@41c00000 { 35f853f005SSuman Anna compatible = "mmio-sram"; 36f853f005SSuman Anna reg = <0x00 0x41c00000 0x00 0x80000>; 37f853f005SSuman Anna ranges = <0x0 0x00 0x41c00000 0x80000>; 38f853f005SSuman Anna #address-cells = <1>; 39f853f005SSuman Anna #size-cells = <1>; 40f853f005SSuman Anna }; 41f853f005SSuman Anna 4219a1768fSVignesh R mcu_i2c0: i2c@40b00000 { 4319a1768fSVignesh R compatible = "ti,am654-i2c", "ti,omap4-i2c"; 4419a1768fSVignesh R reg = <0x0 0x40b00000 0x0 0x100>; 4519a1768fSVignesh R interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 4619a1768fSVignesh R #address-cells = <1>; 4719a1768fSVignesh R #size-cells = <0>; 4819a1768fSVignesh R clock-names = "fck"; 4919a1768fSVignesh R clocks = <&k3_clks 114 1>; 50c68272cbSLokesh Vutla power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 5119a1768fSVignesh R }; 522cd7d393SVignesh R 532cd7d393SVignesh R mcu_spi0: spi@40300000 { 542cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 552cd7d393SVignesh R reg = <0x0 0x40300000 0x0 0x400>; 562cd7d393SVignesh R interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 572cd7d393SVignesh R clocks = <&k3_clks 142 1>; 58c68272cbSLokesh Vutla power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 592cd7d393SVignesh R #address-cells = <1>; 602cd7d393SVignesh R #size-cells = <0>; 612cd7d393SVignesh R }; 622cd7d393SVignesh R 632cd7d393SVignesh R mcu_spi1: spi@40310000 { 642cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 652cd7d393SVignesh R reg = <0x0 0x40310000 0x0 0x400>; 662cd7d393SVignesh R interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 672cd7d393SVignesh R clocks = <&k3_clks 143 1>; 68c68272cbSLokesh Vutla power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 692cd7d393SVignesh R #address-cells = <1>; 702cd7d393SVignesh R #size-cells = <0>; 712cd7d393SVignesh R }; 722cd7d393SVignesh R 732cd7d393SVignesh R mcu_spi2: spi@40320000 { 742cd7d393SVignesh R compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 752cd7d393SVignesh R reg = <0x0 0x40320000 0x0 0x400>; 762cd7d393SVignesh R interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 772cd7d393SVignesh R clocks = <&k3_clks 144 1>; 78c68272cbSLokesh Vutla power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 792cd7d393SVignesh R #address-cells = <1>; 802cd7d393SVignesh R #size-cells = <0>; 812cd7d393SVignesh R }; 82aa6eaaa2SVignesh R 83aa6eaaa2SVignesh R tscadc0: tscadc@40200000 { 84aa6eaaa2SVignesh R compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 85aa6eaaa2SVignesh R reg = <0x0 0x40200000 0x0 0x1000>; 86aa6eaaa2SVignesh R interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 87aa6eaaa2SVignesh R clocks = <&k3_clks 0 2>; 88aa6eaaa2SVignesh R assigned-clocks = <&k3_clks 0 2>; 89aa6eaaa2SVignesh R assigned-clock-rates = <60000000>; 90aa6eaaa2SVignesh R clock-names = "adc_tsc_fck"; 9185800da0SVignesh Raghavendra dmas = <&mcu_udmap 0x7100>, 9285800da0SVignesh Raghavendra <&mcu_udmap 0x7101 >; 9385800da0SVignesh Raghavendra dma-names = "fifo0", "fifo1"; 94aa6eaaa2SVignesh R 95aa6eaaa2SVignesh R adc { 96aa6eaaa2SVignesh R #io-channel-cells = <1>; 97aa6eaaa2SVignesh R compatible = "ti,am654-adc", "ti,am3359-adc"; 98aa6eaaa2SVignesh R }; 99aa6eaaa2SVignesh R }; 100aa6eaaa2SVignesh R 101aa6eaaa2SVignesh R tscadc1: tscadc@40210000 { 102aa6eaaa2SVignesh R compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 103aa6eaaa2SVignesh R reg = <0x0 0x40210000 0x0 0x1000>; 104aa6eaaa2SVignesh R interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 105aa6eaaa2SVignesh R clocks = <&k3_clks 1 2>; 106aa6eaaa2SVignesh R assigned-clocks = <&k3_clks 1 2>; 107aa6eaaa2SVignesh R assigned-clock-rates = <60000000>; 108aa6eaaa2SVignesh R clock-names = "adc_tsc_fck"; 10985800da0SVignesh Raghavendra dmas = <&mcu_udmap 0x7102>, 11085800da0SVignesh Raghavendra <&mcu_udmap 0x7103>; 11185800da0SVignesh Raghavendra dma-names = "fifo0", "fifo1"; 112aa6eaaa2SVignesh R 113aa6eaaa2SVignesh R adc { 114aa6eaaa2SVignesh R #io-channel-cells = <1>; 115aa6eaaa2SVignesh R compatible = "ti,am654-adc", "ti,am3359-adc"; 116aa6eaaa2SVignesh R }; 117aa6eaaa2SVignesh R }; 11807481770SVignesh Raghavendra 1193d623054SPeter Ujfalusi mcu_navss { 1203d623054SPeter Ujfalusi compatible = "simple-mfd"; 1213d623054SPeter Ujfalusi #address-cells = <2>; 1223d623054SPeter Ujfalusi #size-cells = <2>; 1233d623054SPeter Ujfalusi ranges; 1243d623054SPeter Ujfalusi dma-coherent; 1253d623054SPeter Ujfalusi dma-ranges; 1263d623054SPeter Ujfalusi 1273d623054SPeter Ujfalusi ti,sci-dev-id = <119>; 1283d623054SPeter Ujfalusi 1293d623054SPeter Ujfalusi mcu_ringacc: ringacc@2b800000 { 1303d623054SPeter Ujfalusi compatible = "ti,am654-navss-ringacc"; 1313d623054SPeter Ujfalusi reg = <0x0 0x2b800000 0x0 0x400000>, 1323d623054SPeter Ujfalusi <0x0 0x2b000000 0x0 0x400000>, 1333d623054SPeter Ujfalusi <0x0 0x28590000 0x0 0x100>, 1343d623054SPeter Ujfalusi <0x0 0x2a500000 0x0 0x40000>; 1353d623054SPeter Ujfalusi reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 1363d623054SPeter Ujfalusi ti,num-rings = <286>; 1373d623054SPeter Ujfalusi ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ 1383d623054SPeter Ujfalusi ti,dma-ring-reset-quirk; 1393d623054SPeter Ujfalusi ti,sci = <&dmsc>; 1403d623054SPeter Ujfalusi ti,sci-dev-id = <195>; 1413d623054SPeter Ujfalusi msi-parent = <&inta_main_udmass>; 1423d623054SPeter Ujfalusi }; 1433d623054SPeter Ujfalusi 1443d623054SPeter Ujfalusi mcu_udmap: dma-controller@285c0000 { 1453d623054SPeter Ujfalusi compatible = "ti,am654-navss-mcu-udmap"; 1463d623054SPeter Ujfalusi reg = <0x0 0x285c0000 0x0 0x100>, 1473d623054SPeter Ujfalusi <0x0 0x2a800000 0x0 0x40000>, 1483d623054SPeter Ujfalusi <0x0 0x2aa00000 0x0 0x40000>; 1493d623054SPeter Ujfalusi reg-names = "gcfg", "rchanrt", "tchanrt"; 1503d623054SPeter Ujfalusi msi-parent = <&inta_main_udmass>; 1513d623054SPeter Ujfalusi #dma-cells = <1>; 1523d623054SPeter Ujfalusi 1533d623054SPeter Ujfalusi ti,sci = <&dmsc>; 1543d623054SPeter Ujfalusi ti,sci-dev-id = <194>; 1553d623054SPeter Ujfalusi ti,ringacc = <&mcu_ringacc>; 1563d623054SPeter Ujfalusi 1573d623054SPeter Ujfalusi ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ 1583d623054SPeter Ujfalusi <0x2>; /* TX_CHAN */ 1593d623054SPeter Ujfalusi ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ 1603d623054SPeter Ujfalusi <0x4>; /* RX_CHAN */ 1613d623054SPeter Ujfalusi ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ 1623d623054SPeter Ujfalusi }; 1633d623054SPeter Ujfalusi }; 1643d623054SPeter Ujfalusi 16507481770SVignesh Raghavendra fss: fss@47000000 { 16607481770SVignesh Raghavendra compatible = "simple-bus"; 16707481770SVignesh Raghavendra #address-cells = <2>; 16807481770SVignesh Raghavendra #size-cells = <2>; 16907481770SVignesh Raghavendra ranges; 17007481770SVignesh Raghavendra 17107481770SVignesh Raghavendra ospi0: spi@47040000 { 17207481770SVignesh Raghavendra compatible = "ti,am654-ospi", "cdns,qspi-nor"; 17307481770SVignesh Raghavendra reg = <0x0 0x47040000 0x0 0x100>, 17407481770SVignesh Raghavendra <0x5 0x00000000 0x1 0x0000000>; 17507481770SVignesh Raghavendra interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 17607481770SVignesh Raghavendra cdns,fifo-depth = <256>; 17707481770SVignesh Raghavendra cdns,fifo-width = <4>; 17807481770SVignesh Raghavendra cdns,trigger-address = <0x0>; 17907481770SVignesh Raghavendra clocks = <&k3_clks 248 0>; 18007481770SVignesh Raghavendra assigned-clocks = <&k3_clks 248 0>; 18107481770SVignesh Raghavendra assigned-clock-parents = <&k3_clks 248 2>; 18207481770SVignesh Raghavendra assigned-clock-rates = <166666666>; 18307481770SVignesh Raghavendra power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 18407481770SVignesh Raghavendra #address-cells = <1>; 18507481770SVignesh Raghavendra #size-cells = <0>; 18607481770SVignesh Raghavendra }; 18707481770SVignesh Raghavendra 18807481770SVignesh Raghavendra ospi1: spi@47050000 { 18907481770SVignesh Raghavendra compatible = "ti,am654-ospi", "cdns,qspi-nor"; 19007481770SVignesh Raghavendra reg = <0x0 0x47050000 0x0 0x100>, 19107481770SVignesh Raghavendra <0x7 0x00000000 0x1 0x00000000>; 19207481770SVignesh Raghavendra interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 19307481770SVignesh Raghavendra cdns,fifo-depth = <256>; 19407481770SVignesh Raghavendra cdns,fifo-width = <4>; 19507481770SVignesh Raghavendra cdns,trigger-address = <0x0>; 19607481770SVignesh Raghavendra clocks = <&k3_clks 249 6>; 19707481770SVignesh Raghavendra power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 19807481770SVignesh Raghavendra #address-cells = <1>; 19907481770SVignesh Raghavendra #size-cells = <0>; 20007481770SVignesh Raghavendra }; 20107481770SVignesh Raghavendra }; 2024201af25SNishanth Menon}; 203