1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/mux/ti-serdes.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include "k3-am642.dtsi"
13
14/ {
15	compatible =  "ti,am642-sk", "ti,am642";
16	model = "Texas Instruments AM642 SK";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
21	};
22
23	memory@80000000 {
24		device_type = "memory";
25		/* 2G RAM */
26		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
27
28	};
29
30	reserved-memory {
31		#address-cells = <2>;
32		#size-cells = <2>;
33		ranges;
34
35		secure_ddr: optee@9e800000 {
36			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
37			alignment = <0x1000>;
38			no-map;
39		};
40	};
41
42	vusb_main: fixed-regulator-vusb-main5v0 {
43		/* USB MAIN INPUT 5V DC */
44		compatible = "regulator-fixed";
45		regulator-name = "vusb_main5v0";
46		regulator-min-microvolt = <5000000>;
47		regulator-max-microvolt = <5000000>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51
52	vcc_3v3_sys: fixedregulator-vcc-3v3-sys {
53		/* output of LP8733xx */
54		compatible = "regulator-fixed";
55		regulator-name = "vcc_3v3_sys";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		vin-supply = <&vusb_main>;
59		regulator-always-on;
60		regulator-boot-on;
61	};
62
63	vdd_mmc1: fixed-regulator-sd {
64		/* TPS2051BD */
65		compatible = "regulator-fixed";
66		regulator-name = "vdd_mmc1";
67		regulator-min-microvolt = <3300000>;
68		regulator-max-microvolt = <3300000>;
69		regulator-boot-on;
70		enable-active-high;
71		vin-supply = <&vcc_3v3_sys>;
72		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
73	};
74};
75
76&main_pmx0 {
77	main_mmc1_pins_default: main-mmc1-pins-default {
78		pinctrl-single,pins = <
79			AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
80			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
81			AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
82			AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
83			AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
84			AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
85			AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
86			AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
87		>;
88	};
89
90	main_usb0_pins_default: main-usb0-pins-default {
91		pinctrl-single,pins = <
92			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
93		>;
94	};
95
96	main_i2c1_pins_default: main-i2c1-pins-default {
97		pinctrl-single,pins = <
98			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
99			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
100		>;
101	};
102
103	mdio1_pins_default: mdio1-pins-default {
104		pinctrl-single,pins = <
105			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
106			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
107		>;
108	};
109
110	rgmii1_pins_default: rgmii1-pins-default {
111		pinctrl-single,pins = <
112			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
113			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
114			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
115			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
116			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
117			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
118			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
119			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
120			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
121			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
122			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
123			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
124		>;
125	};
126
127       rgmii2_pins_default: rgmii2-pins-default {
128		pinctrl-single,pins = <
129			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
130			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
131			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
132			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
133			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
134			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
135			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
136			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
137			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
138			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
139			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
140			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
141		>;
142	};
143
144	ospi0_pins_default: ospi0-pins-default {
145		pinctrl-single,pins = <
146			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
147			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
148			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
149			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
150			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
151			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
152			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
153			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
154			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
155			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
156			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
157		>;
158	};
159};
160
161&mcu_uart0 {
162	status = "disabled";
163};
164
165&mcu_uart1 {
166	status = "disabled";
167};
168
169&main_uart1 {
170	/* main_uart1 is reserved for firmware usage */
171	status = "reserved";
172};
173
174&main_uart2 {
175	status = "disabled";
176};
177
178&main_uart3 {
179	status = "disabled";
180};
181
182&main_uart4 {
183	status = "disabled";
184};
185
186&main_uart5 {
187	status = "disabled";
188};
189
190&main_uart6 {
191	status = "disabled";
192};
193
194&mcu_i2c0 {
195	status = "disabled";
196};
197
198&mcu_i2c1 {
199	status = "disabled";
200};
201
202&main_i2c1 {
203	pinctrl-names = "default";
204	pinctrl-0 = <&main_i2c1_pins_default>;
205	clock-frequency = <400000>;
206
207	exp1: gpio@70 {
208		compatible = "nxp,pca9538";
209		reg = <0x70>;
210		gpio-controller;
211		#gpio-cells = <2>;
212		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
213				  "PRU_DETECT", "MMC1_SD_EN",
214				  "VPP_LDO_EN", "RPI_PS_3V3_En",
215				  "RPI_PS_5V0_En", "RPI_HAT_DETECT";
216	};
217};
218
219&main_i2c3 {
220	status = "disabled";
221};
222
223&mcu_spi0 {
224	status = "disabled";
225};
226
227&mcu_spi1 {
228	status = "disabled";
229};
230
231/* mcu_gpio0 is reserved for mcu firmware usage */
232&mcu_gpio0 {
233	status = "reserved";
234};
235
236&sdhci1 {
237	/* SD/MMC */
238	vmmc-supply = <&vdd_mmc1>;
239	pinctrl-names = "default";
240	bus-width = <4>;
241	pinctrl-0 = <&main_mmc1_pins_default>;
242	ti,driver-strength-ohm = <50>;
243	disable-wp;
244};
245
246&serdes_ln_ctrl {
247	idle-states = <AM64_SERDES0_LANE0_USB>;
248};
249
250&serdes0 {
251	serdes0_usb_link: phy@0 {
252		reg = <0>;
253		cdns,num-lanes = <1>;
254		#phy-cells = <0>;
255		cdns,phy-type = <PHY_TYPE_USB3>;
256		resets = <&serdes_wiz0 1>;
257	};
258};
259
260&usbss0 {
261	ti,vbus-divider;
262};
263
264&usb0 {
265	dr_mode = "host";
266	maximum-speed = "super-speed";
267	pinctrl-names = "default";
268	pinctrl-0 = <&main_usb0_pins_default>;
269	phys = <&serdes0_usb_link>;
270	phy-names = "cdns3,usb3-phy";
271};
272
273&cpsw3g {
274	pinctrl-names = "default";
275	pinctrl-0 = <&mdio1_pins_default
276		     &rgmii1_pins_default
277		     &rgmii2_pins_default>;
278};
279
280&cpsw_port1 {
281	phy-mode = "rgmii-rxid";
282	phy-handle = <&cpsw3g_phy0>;
283};
284
285&cpsw_port2 {
286	phy-mode = "rgmii-rxid";
287	phy-handle = <&cpsw3g_phy1>;
288};
289
290&cpsw3g_mdio {
291	cpsw3g_phy0: ethernet-phy@0 {
292		reg = <0>;
293		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
294		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
295	};
296
297	cpsw3g_phy1: ethernet-phy@1 {
298		reg = <1>;
299		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
300		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
301	};
302};
303
304&tscadc0 {
305	status = "disabled";
306};
307
308&ospi0 {
309	pinctrl-names = "default";
310	pinctrl-0 = <&ospi0_pins_default>;
311
312	flash@0{
313		compatible = "jedec,spi-nor";
314		reg = <0x0>;
315		spi-tx-bus-width = <8>;
316		spi-rx-bus-width = <8>;
317		spi-max-frequency = <25000000>;
318		cdns,tshsl-ns = <60>;
319		cdns,tsd2d-ns = <60>;
320		cdns,tchsh-ns = <60>;
321		cdns,tslch-ns = <60>;
322		cdns,read-delay = <4>;
323		#address-cells = <1>;
324		#size-cells = <1>;
325	};
326};
327
328&mailbox0_cluster2 {
329	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
330		ti,mbox-rx = <0 0 2>;
331		ti,mbox-tx = <1 0 2>;
332	};
333
334	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
335		ti,mbox-rx = <2 0 2>;
336		ti,mbox-tx = <3 0 2>;
337	};
338};
339
340&mailbox0_cluster3 {
341	status = "disabled";
342};
343
344&mailbox0_cluster4 {
345	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
346		ti,mbox-rx = <0 0 2>;
347		ti,mbox-tx = <1 0 2>;
348	};
349
350	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
351		ti,mbox-rx = <2 0 2>;
352		ti,mbox-tx = <3 0 2>;
353	};
354};
355
356&mailbox0_cluster5 {
357	status = "disabled";
358};
359
360&mailbox0_cluster6 {
361	mbox_m4_0: mbox-m4-0 {
362		ti,mbox-rx = <0 0 2>;
363		ti,mbox-tx = <1 0 2>;
364	};
365};
366
367&mailbox0_cluster7 {
368	status = "disabled";
369};
370
371&pcie0_rc {
372	status = "disabled";
373};
374
375&pcie0_ep {
376	status = "disabled";
377};
378