1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/mux/ti-serdes.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/leds/common.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-sk", "ti,am642"; 17 model = "Texas Instruments AM642 SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 2G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 28 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 rtos_ipc_memory_region: ipc-memories@a5000000 { 91 reg = <0x00 0xa5000000 0x00 0x00800000>; 92 alignment = <0x1000>; 93 no-map; 94 }; 95 }; 96 97 vusb_main: fixed-regulator-vusb-main5v0 { 98 /* USB MAIN INPUT 5V DC */ 99 compatible = "regulator-fixed"; 100 regulator-name = "vusb_main5v0"; 101 regulator-min-microvolt = <5000000>; 102 regulator-max-microvolt = <5000000>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 vcc_3v3_sys: fixedregulator-vcc-3v3-sys { 108 /* output of LP8733xx */ 109 compatible = "regulator-fixed"; 110 regulator-name = "vcc_3v3_sys"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 vin-supply = <&vusb_main>; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vdd_mmc1: fixed-regulator-sd { 119 /* TPS2051BD */ 120 compatible = "regulator-fixed"; 121 regulator-name = "vdd_mmc1"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 regulator-boot-on; 125 enable-active-high; 126 vin-supply = <&vcc_3v3_sys>; 127 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 128 }; 129 130 com8_ls_en: regulator-1 { 131 compatible = "regulator-fixed"; 132 regulator-name = "com8_ls_en"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 regulator-always-on; 136 regulator-boot-on; 137 pinctrl-0 = <&main_com8_ls_en_pins_default>; 138 pinctrl-names = "default"; 139 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; 140 }; 141 142 wlan_en: regulator-2 { 143 /* output of SN74AVC4T245RSVR */ 144 compatible = "regulator-fixed"; 145 regulator-name = "wlan_en"; 146 regulator-min-microvolt = <1800000>; 147 regulator-max-microvolt = <1800000>; 148 enable-active-high; 149 pinctrl-0 = <&main_wlan_en_pins_default>; 150 pinctrl-names = "default"; 151 vin-supply = <&com8_ls_en>; 152 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; 153 }; 154 155 led-controller { 156 compatible = "gpio-leds"; 157 158 led-0 { 159 color = <LED_COLOR_ID_GREEN>; 160 function = LED_FUNCTION_INDICATOR; 161 function-enumerator = <1>; 162 gpios = <&exp2 0 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 166 led-1 { 167 color = <LED_COLOR_ID_RED>; 168 function = LED_FUNCTION_INDICATOR; 169 function-enumerator = <2>; 170 gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 171 default-state = "off"; 172 }; 173 174 led-2 { 175 color = <LED_COLOR_ID_GREEN>; 176 function = LED_FUNCTION_INDICATOR; 177 function-enumerator = <3>; 178 gpios = <&exp2 2 GPIO_ACTIVE_HIGH>; 179 default-state = "off"; 180 }; 181 182 led-3 { 183 color = <LED_COLOR_ID_AMBER>; 184 function = LED_FUNCTION_INDICATOR; 185 function-enumerator = <4>; 186 gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; 187 default-state = "off"; 188 }; 189 190 led-4 { 191 color = <LED_COLOR_ID_GREEN>; 192 function = LED_FUNCTION_INDICATOR; 193 function-enumerator = <5>; 194 gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; 195 default-state = "off"; 196 }; 197 198 led-5 { 199 color = <LED_COLOR_ID_RED>; 200 function = LED_FUNCTION_INDICATOR; 201 function-enumerator = <6>; 202 gpios = <&exp2 5 GPIO_ACTIVE_HIGH>; 203 default-state = "off"; 204 }; 205 206 led-6 { 207 color = <LED_COLOR_ID_GREEN>; 208 function = LED_FUNCTION_INDICATOR; 209 function-enumerator = <7>; 210 gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 211 default-state = "off"; 212 }; 213 214 led-7 { 215 color = <LED_COLOR_ID_AMBER>; 216 function = LED_FUNCTION_HEARTBEAT; 217 function-enumerator = <8>; 218 linux,default-trigger = "heartbeat"; 219 gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 220 }; 221 }; 222}; 223 224&main_pmx0 { 225 main_mmc1_pins_default: main-mmc1-pins-default { 226 pinctrl-single,pins = < 227 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ 228 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 229 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 230 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ 231 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 232 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 233 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 234 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 235 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 236 >; 237 }; 238 239 main_uart0_pins_default: main-uart0-pins-default { 240 pinctrl-single,pins = < 241 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 242 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 243 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 244 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 245 >; 246 }; 247 248 main_uart1_pins_default: main-uart1-pins-default { 249 pinctrl-single,pins = < 250 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 251 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 252 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 253 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 254 >; 255 }; 256 257 main_usb0_pins_default: main-usb0-pins-default { 258 pinctrl-single,pins = < 259 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 260 >; 261 }; 262 263 main_i2c0_pins_default: main-i2c0-pins-default { 264 pinctrl-single,pins = < 265 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 266 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 267 >; 268 }; 269 270 main_i2c1_pins_default: main-i2c1-pins-default { 271 pinctrl-single,pins = < 272 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 273 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 274 >; 275 }; 276 277 mdio1_pins_default: mdio1-pins-default { 278 pinctrl-single,pins = < 279 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 280 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 281 >; 282 }; 283 284 rgmii1_pins_default: rgmii1-pins-default { 285 pinctrl-single,pins = < 286 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ 287 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ 288 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ 289 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ 290 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ 291 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ 292 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 293 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 294 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 295 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 296 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 297 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 298 >; 299 }; 300 301 rgmii2_pins_default: rgmii2-pins-default { 302 pinctrl-single,pins = < 303 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 304 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 305 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 306 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 307 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 308 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 309 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 310 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 311 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 312 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 313 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 314 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 315 >; 316 }; 317 318 ospi0_pins_default: ospi0-pins-default { 319 pinctrl-single,pins = < 320 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 321 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 322 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 323 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 324 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 325 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 326 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 327 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 328 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 329 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 330 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 331 >; 332 }; 333 334 main_ecap0_pins_default: main-ecap0-pins-default { 335 pinctrl-single,pins = < 336 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 337 >; 338 }; 339 main_wlan_en_pins_default: main-wlan-en-pins-default { 340 pinctrl-single,pins = < 341 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ 342 >; 343 }; 344 345 main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { 346 pinctrl-single,pins = < 347 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ 348 >; 349 }; 350 351 main_wlan_pins_default: main-wlan-pins-default { 352 pinctrl-single,pins = < 353 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ 354 >; 355 }; 356}; 357 358&main_uart0 { 359 status = "okay"; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&main_uart0_pins_default>; 362}; 363 364&main_uart1 { 365 /* main_uart1 is reserved for firmware usage */ 366 status = "reserved"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&main_uart1_pins_default>; 369}; 370 371&main_i2c0 { 372 status = "okay"; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&main_i2c0_pins_default>; 375 clock-frequency = <400000>; 376 377 eeprom@51 { 378 compatible = "atmel,24c512"; 379 reg = <0x51>; 380 }; 381}; 382 383&main_i2c1 { 384 status = "okay"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&main_i2c1_pins_default>; 387 clock-frequency = <400000>; 388 389 exp1: gpio@70 { 390 compatible = "nxp,pca9538"; 391 reg = <0x70>; 392 gpio-controller; 393 #gpio-cells = <2>; 394 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 395 "PRU_DETECT", "MMC1_SD_EN", 396 "VPP_LDO_EN", "RPI_PS_3V3_En", 397 "RPI_PS_5V0_En", "RPI_HAT_DETECT"; 398 }; 399 400 exp2: gpio@60 { 401 compatible = "ti,tpic2810"; 402 reg = <0x60>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; 406 }; 407}; 408 409/* mcu_gpio0 is reserved for mcu firmware usage */ 410&mcu_gpio0 { 411 status = "reserved"; 412}; 413 414&sdhci0 { 415 vmmc-supply = <&wlan_en>; 416 bus-width = <4>; 417 non-removable; 418 cap-power-off-card; 419 keep-power-in-suspend; 420 ti,driver-strength-ohm = <50>; 421 422 #address-cells = <1>; 423 #size-cells = <0>; 424 wlcore: wlcore@2 { 425 compatible = "ti,wl1837"; 426 reg = <2>; 427 pinctrl-0 = <&main_wlan_pins_default>; 428 pinctrl-names = "default"; 429 interrupt-parent = <&main_gpio0>; 430 interrupts = <46 IRQ_TYPE_EDGE_FALLING>; 431 }; 432}; 433 434&sdhci1 { 435 /* SD/MMC */ 436 vmmc-supply = <&vdd_mmc1>; 437 pinctrl-names = "default"; 438 bus-width = <4>; 439 pinctrl-0 = <&main_mmc1_pins_default>; 440 ti,driver-strength-ohm = <50>; 441 disable-wp; 442}; 443 444&serdes_ln_ctrl { 445 idle-states = <AM64_SERDES0_LANE0_USB>; 446}; 447 448&serdes0 { 449 serdes0_usb_link: phy@0 { 450 reg = <0>; 451 cdns,num-lanes = <1>; 452 #phy-cells = <0>; 453 cdns,phy-type = <PHY_TYPE_USB3>; 454 resets = <&serdes_wiz0 1>; 455 }; 456}; 457 458&usbss0 { 459 ti,vbus-divider; 460}; 461 462&usb0 { 463 dr_mode = "host"; 464 maximum-speed = "super-speed"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&main_usb0_pins_default>; 467 phys = <&serdes0_usb_link>; 468 phy-names = "cdns3,usb3-phy"; 469}; 470 471&cpsw3g { 472 pinctrl-names = "default"; 473 pinctrl-0 = <&rgmii1_pins_default 474 &rgmii2_pins_default>; 475}; 476 477&cpsw_port1 { 478 phy-mode = "rgmii-rxid"; 479 phy-handle = <&cpsw3g_phy0>; 480}; 481 482&cpsw_port2 { 483 phy-mode = "rgmii-rxid"; 484 phy-handle = <&cpsw3g_phy1>; 485}; 486 487&cpsw3g_mdio { 488 status = "okay"; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&mdio1_pins_default>; 491 492 cpsw3g_phy0: ethernet-phy@0 { 493 reg = <0>; 494 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 495 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 496 }; 497 498 cpsw3g_phy1: ethernet-phy@1 { 499 reg = <1>; 500 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 501 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 502 }; 503}; 504 505&tscadc0 { 506 status = "disabled"; 507}; 508 509&ospi0 { 510 pinctrl-names = "default"; 511 pinctrl-0 = <&ospi0_pins_default>; 512 513 flash@0 { 514 compatible = "jedec,spi-nor"; 515 reg = <0x0>; 516 spi-tx-bus-width = <8>; 517 spi-rx-bus-width = <8>; 518 spi-max-frequency = <25000000>; 519 cdns,tshsl-ns = <60>; 520 cdns,tsd2d-ns = <60>; 521 cdns,tchsh-ns = <60>; 522 cdns,tslch-ns = <60>; 523 cdns,read-delay = <4>; 524 }; 525}; 526 527&mailbox0_cluster2 { 528 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 529 ti,mbox-rx = <0 0 2>; 530 ti,mbox-tx = <1 0 2>; 531 }; 532 533 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 534 ti,mbox-rx = <2 0 2>; 535 ti,mbox-tx = <3 0 2>; 536 }; 537}; 538 539&mailbox0_cluster3 { 540 status = "disabled"; 541}; 542 543&mailbox0_cluster4 { 544 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 545 ti,mbox-rx = <0 0 2>; 546 ti,mbox-tx = <1 0 2>; 547 }; 548 549 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 550 ti,mbox-rx = <2 0 2>; 551 ti,mbox-tx = <3 0 2>; 552 }; 553}; 554 555&mailbox0_cluster5 { 556 status = "disabled"; 557}; 558 559&mailbox0_cluster6 { 560 mbox_m4_0: mbox-m4-0 { 561 ti,mbox-rx = <0 0 2>; 562 ti,mbox-tx = <1 0 2>; 563 }; 564}; 565 566&mailbox0_cluster7 { 567 status = "disabled"; 568}; 569 570&main_r5fss0_core0 { 571 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 572 memory-region = <&main_r5fss0_core0_dma_memory_region>, 573 <&main_r5fss0_core0_memory_region>; 574}; 575 576&main_r5fss0_core1 { 577 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 578 memory-region = <&main_r5fss0_core1_dma_memory_region>, 579 <&main_r5fss0_core1_memory_region>; 580}; 581 582&main_r5fss1_core0 { 583 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 584 memory-region = <&main_r5fss1_core0_dma_memory_region>, 585 <&main_r5fss1_core0_memory_region>; 586}; 587 588&main_r5fss1_core1 { 589 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 590 memory-region = <&main_r5fss1_core1_dma_memory_region>, 591 <&main_r5fss1_core1_memory_region>; 592}; 593 594&ecap0 { 595 status = "okay"; 596 /* PWM is available on Pin 1 of header J3 */ 597 pinctrl-names = "default"; 598 pinctrl-0 = <&main_ecap0_pins_default>; 599}; 600