1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/mux/ti-serdes.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/leds/common.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-sk", "ti,am642"; 17 model = "Texas Instruments AM642 SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 }; 22 23 aliases { 24 serial0 = &mcu_uart0; 25 serial1 = &main_uart1; 26 serial2 = &main_uart0; 27 i2c0 = &main_i2c0; 28 i2c1 = &main_i2c1; 29 mmc0 = &sdhci0; 30 mmc1 = &sdhci1; 31 ethernet0 = &cpsw_port1; 32 ethernet1 = &cpsw_port2; 33 }; 34 35 memory@80000000 { 36 device_type = "memory"; 37 /* 2G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 39 }; 40 41 reserved-memory { 42 #address-cells = <2>; 43 #size-cells = <2>; 44 ranges; 45 46 secure_ddr: optee@9e800000 { 47 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 48 alignment = <0x1000>; 49 no-map; 50 }; 51 52 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 64 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1000000 0x00 0x100000>; 67 no-map; 68 }; 69 70 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa1100000 0x00 0xf00000>; 73 no-map; 74 }; 75 76 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2000000 0x00 0x100000>; 79 no-map; 80 }; 81 82 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa2100000 0x00 0xf00000>; 85 no-map; 86 }; 87 88 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3000000 0x00 0x100000>; 91 no-map; 92 }; 93 94 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa3100000 0x00 0xf00000>; 97 no-map; 98 }; 99 100 rtos_ipc_memory_region: ipc-memories@a5000000 { 101 reg = <0x00 0xa5000000 0x00 0x00800000>; 102 alignment = <0x1000>; 103 no-map; 104 }; 105 }; 106 107 vusb_main: regulator-0 { 108 /* USB MAIN INPUT 5V DC */ 109 compatible = "regulator-fixed"; 110 regulator-name = "vusb_main5v0"; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 regulator-always-on; 114 regulator-boot-on; 115 }; 116 117 vcc_3v3_sys: regulator-1 { 118 /* output of LP8733xx */ 119 compatible = "regulator-fixed"; 120 regulator-name = "vcc_3v3_sys"; 121 regulator-min-microvolt = <3300000>; 122 regulator-max-microvolt = <3300000>; 123 vin-supply = <&vusb_main>; 124 regulator-always-on; 125 regulator-boot-on; 126 }; 127 128 vdd_mmc1: regulator-2 { 129 /* TPS2051BD */ 130 compatible = "regulator-fixed"; 131 regulator-name = "vdd_mmc1"; 132 regulator-min-microvolt = <3300000>; 133 regulator-max-microvolt = <3300000>; 134 regulator-boot-on; 135 enable-active-high; 136 vin-supply = <&vcc_3v3_sys>; 137 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 138 }; 139 140 com8_ls_en: regulator-3 { 141 compatible = "regulator-fixed"; 142 regulator-name = "com8_ls_en"; 143 regulator-min-microvolt = <3300000>; 144 regulator-max-microvolt = <3300000>; 145 regulator-always-on; 146 regulator-boot-on; 147 pinctrl-0 = <&main_com8_ls_en_pins_default>; 148 pinctrl-names = "default"; 149 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; 150 }; 151 152 wlan_en: regulator-4 { 153 /* output of SN74AVC4T245RSVR */ 154 compatible = "regulator-fixed"; 155 regulator-name = "wlan_en"; 156 regulator-min-microvolt = <1800000>; 157 regulator-max-microvolt = <1800000>; 158 enable-active-high; 159 pinctrl-0 = <&main_wlan_en_pins_default>; 160 pinctrl-names = "default"; 161 vin-supply = <&com8_ls_en>; 162 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; 163 }; 164 165 led-controller { 166 compatible = "gpio-leds"; 167 168 led-0 { 169 color = <LED_COLOR_ID_GREEN>; 170 function = LED_FUNCTION_INDICATOR; 171 function-enumerator = <1>; 172 gpios = <&exp2 0 GPIO_ACTIVE_HIGH>; 173 default-state = "off"; 174 }; 175 176 led-1 { 177 color = <LED_COLOR_ID_RED>; 178 function = LED_FUNCTION_INDICATOR; 179 function-enumerator = <2>; 180 gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 181 default-state = "off"; 182 }; 183 184 led-2 { 185 color = <LED_COLOR_ID_GREEN>; 186 function = LED_FUNCTION_INDICATOR; 187 function-enumerator = <3>; 188 gpios = <&exp2 2 GPIO_ACTIVE_HIGH>; 189 default-state = "off"; 190 }; 191 192 led-3 { 193 color = <LED_COLOR_ID_AMBER>; 194 function = LED_FUNCTION_INDICATOR; 195 function-enumerator = <4>; 196 gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; 197 default-state = "off"; 198 }; 199 200 led-4 { 201 color = <LED_COLOR_ID_GREEN>; 202 function = LED_FUNCTION_INDICATOR; 203 function-enumerator = <5>; 204 gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; 205 default-state = "off"; 206 }; 207 208 led-5 { 209 color = <LED_COLOR_ID_RED>; 210 function = LED_FUNCTION_INDICATOR; 211 function-enumerator = <6>; 212 gpios = <&exp2 5 GPIO_ACTIVE_HIGH>; 213 default-state = "off"; 214 }; 215 216 led-6 { 217 color = <LED_COLOR_ID_GREEN>; 218 function = LED_FUNCTION_INDICATOR; 219 function-enumerator = <7>; 220 gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 221 default-state = "off"; 222 }; 223 224 led-7 { 225 color = <LED_COLOR_ID_AMBER>; 226 function = LED_FUNCTION_HEARTBEAT; 227 function-enumerator = <8>; 228 linux,default-trigger = "heartbeat"; 229 gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 230 }; 231 }; 232}; 233 234&main_pmx0 { 235 main_mmc1_pins_default: main-mmc1-pins-default { 236 pinctrl-single,pins = < 237 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ 238 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 239 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 240 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ 241 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 242 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 243 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 244 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 245 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 246 >; 247 }; 248 249 main_uart0_pins_default: main-uart0-pins-default { 250 pinctrl-single,pins = < 251 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 252 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 253 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 254 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 255 >; 256 }; 257 258 main_uart1_pins_default: main-uart1-pins-default { 259 pinctrl-single,pins = < 260 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 261 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 262 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 263 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 264 >; 265 }; 266 267 main_usb0_pins_default: main-usb0-pins-default { 268 pinctrl-single,pins = < 269 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 270 >; 271 }; 272 273 main_i2c0_pins_default: main-i2c0-pins-default { 274 pinctrl-single,pins = < 275 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 276 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 277 >; 278 }; 279 280 main_i2c1_pins_default: main-i2c1-pins-default { 281 pinctrl-single,pins = < 282 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 283 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 284 >; 285 }; 286 287 mdio1_pins_default: mdio1-pins-default { 288 pinctrl-single,pins = < 289 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 290 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 291 >; 292 }; 293 294 rgmii1_pins_default: rgmii1-pins-default { 295 pinctrl-single,pins = < 296 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ 297 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ 298 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ 299 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ 300 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ 301 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ 302 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 303 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 304 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 305 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 306 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 307 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 308 >; 309 }; 310 311 rgmii2_pins_default: rgmii2-pins-default { 312 pinctrl-single,pins = < 313 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 314 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 315 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 316 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 317 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 318 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 319 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 320 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 321 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 322 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 323 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 324 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 325 >; 326 }; 327 328 ospi0_pins_default: ospi0-pins-default { 329 pinctrl-single,pins = < 330 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 331 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 332 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 333 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 334 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 335 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 336 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 337 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 338 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 339 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 340 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 341 >; 342 }; 343 344 main_ecap0_pins_default: main-ecap0-pins-default { 345 pinctrl-single,pins = < 346 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 347 >; 348 }; 349 main_wlan_en_pins_default: main-wlan-en-pins-default { 350 pinctrl-single,pins = < 351 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ 352 >; 353 }; 354 355 main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { 356 pinctrl-single,pins = < 357 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ 358 >; 359 }; 360 361 main_wlan_pins_default: main-wlan-pins-default { 362 pinctrl-single,pins = < 363 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ 364 >; 365 }; 366}; 367 368&main_uart0 { 369 status = "okay"; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&main_uart0_pins_default>; 372}; 373 374&main_uart1 { 375 /* main_uart1 is reserved for firmware usage */ 376 status = "reserved"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&main_uart1_pins_default>; 379}; 380 381&main_i2c0 { 382 status = "okay"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&main_i2c0_pins_default>; 385 clock-frequency = <400000>; 386 387 eeprom@51 { 388 compatible = "atmel,24c512"; 389 reg = <0x51>; 390 }; 391}; 392 393&main_i2c1 { 394 status = "okay"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&main_i2c1_pins_default>; 397 clock-frequency = <400000>; 398 399 exp1: gpio@70 { 400 compatible = "nxp,pca9538"; 401 reg = <0x70>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 405 "PRU_DETECT", "MMC1_SD_EN", 406 "VPP_LDO_EN", "RPI_PS_3V3_En", 407 "RPI_PS_5V0_En", "RPI_HAT_DETECT"; 408 }; 409 410 exp2: gpio@60 { 411 compatible = "ti,tpic2810"; 412 reg = <0x60>; 413 gpio-controller; 414 #gpio-cells = <2>; 415 gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; 416 }; 417}; 418 419/* mcu_gpio0 is reserved for mcu firmware usage */ 420&mcu_gpio0 { 421 status = "reserved"; 422}; 423 424&sdhci0 { 425 vmmc-supply = <&wlan_en>; 426 bus-width = <4>; 427 non-removable; 428 cap-power-off-card; 429 keep-power-in-suspend; 430 ti,driver-strength-ohm = <50>; 431 432 #address-cells = <1>; 433 #size-cells = <0>; 434 wlcore: wlcore@2 { 435 compatible = "ti,wl1837"; 436 reg = <2>; 437 pinctrl-0 = <&main_wlan_pins_default>; 438 pinctrl-names = "default"; 439 interrupt-parent = <&main_gpio0>; 440 interrupts = <46 IRQ_TYPE_EDGE_FALLING>; 441 }; 442}; 443 444&sdhci1 { 445 /* SD/MMC */ 446 vmmc-supply = <&vdd_mmc1>; 447 pinctrl-names = "default"; 448 bus-width = <4>; 449 pinctrl-0 = <&main_mmc1_pins_default>; 450 ti,driver-strength-ohm = <50>; 451 disable-wp; 452}; 453 454&serdes_ln_ctrl { 455 idle-states = <AM64_SERDES0_LANE0_USB>; 456}; 457 458&serdes0 { 459 serdes0_usb_link: phy@0 { 460 reg = <0>; 461 cdns,num-lanes = <1>; 462 #phy-cells = <0>; 463 cdns,phy-type = <PHY_TYPE_USB3>; 464 resets = <&serdes_wiz0 1>; 465 }; 466}; 467 468&usbss0 { 469 ti,vbus-divider; 470}; 471 472&usb0 { 473 dr_mode = "host"; 474 maximum-speed = "super-speed"; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&main_usb0_pins_default>; 477 phys = <&serdes0_usb_link>; 478 phy-names = "cdns3,usb3-phy"; 479}; 480 481&cpsw3g { 482 pinctrl-names = "default"; 483 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; 484}; 485 486&cpsw_port1 { 487 phy-mode = "rgmii-rxid"; 488 phy-handle = <&cpsw3g_phy0>; 489}; 490 491&cpsw_port2 { 492 phy-mode = "rgmii-rxid"; 493 phy-handle = <&cpsw3g_phy1>; 494}; 495 496&cpsw3g_mdio { 497 status = "okay"; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&mdio1_pins_default>; 500 501 cpsw3g_phy0: ethernet-phy@0 { 502 reg = <0>; 503 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 504 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 505 }; 506 507 cpsw3g_phy1: ethernet-phy@1 { 508 reg = <1>; 509 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 510 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 511 }; 512}; 513 514&tscadc0 { 515 status = "disabled"; 516}; 517 518&ospi0 { 519 pinctrl-names = "default"; 520 pinctrl-0 = <&ospi0_pins_default>; 521 522 flash@0 { 523 compatible = "jedec,spi-nor"; 524 reg = <0x0>; 525 spi-tx-bus-width = <8>; 526 spi-rx-bus-width = <8>; 527 spi-max-frequency = <25000000>; 528 cdns,tshsl-ns = <60>; 529 cdns,tsd2d-ns = <60>; 530 cdns,tchsh-ns = <60>; 531 cdns,tslch-ns = <60>; 532 cdns,read-delay = <4>; 533 534 partitions { 535 compatible = "fixed-partitions"; 536 #address-cells = <1>; 537 #size-cells = <1>; 538 539 partition@0 { 540 label = "ospi.tiboot3"; 541 reg = <0x0 0x100000>; 542 }; 543 544 partition@100000 { 545 label = "ospi.tispl"; 546 reg = <0x100000 0x200000>; 547 }; 548 549 partition@300000 { 550 label = "ospi.u-boot"; 551 reg = <0x300000 0x400000>; 552 }; 553 554 partition@700000 { 555 label = "ospi.env"; 556 reg = <0x700000 0x40000>; 557 }; 558 559 partition@740000 { 560 label = "ospi.env.backup"; 561 reg = <0x740000 0x40000>; 562 }; 563 564 partition@800000 { 565 label = "ospi.rootfs"; 566 reg = <0x800000 0x37c0000>; 567 }; 568 569 partition@3fc0000 { 570 label = "ospi.phypattern"; 571 reg = <0x3fc0000 0x40000>; 572 }; 573 }; 574 }; 575}; 576 577&mailbox0_cluster2 { 578 status = "okay"; 579 580 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 581 ti,mbox-rx = <0 0 2>; 582 ti,mbox-tx = <1 0 2>; 583 }; 584 585 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 586 ti,mbox-rx = <2 0 2>; 587 ti,mbox-tx = <3 0 2>; 588 }; 589}; 590 591&mailbox0_cluster4 { 592 status = "okay"; 593 594 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 595 ti,mbox-rx = <0 0 2>; 596 ti,mbox-tx = <1 0 2>; 597 }; 598 599 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 600 ti,mbox-rx = <2 0 2>; 601 ti,mbox-tx = <3 0 2>; 602 }; 603}; 604 605&mailbox0_cluster6 { 606 status = "okay"; 607 608 mbox_m4_0: mbox-m4-0 { 609 ti,mbox-rx = <0 0 2>; 610 ti,mbox-tx = <1 0 2>; 611 }; 612}; 613 614&main_r5fss0_core0 { 615 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; 616 memory-region = <&main_r5fss0_core0_dma_memory_region>, 617 <&main_r5fss0_core0_memory_region>; 618}; 619 620&main_r5fss0_core1 { 621 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; 622 memory-region = <&main_r5fss0_core1_dma_memory_region>, 623 <&main_r5fss0_core1_memory_region>; 624}; 625 626&main_r5fss1_core0 { 627 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; 628 memory-region = <&main_r5fss1_core0_dma_memory_region>, 629 <&main_r5fss1_core0_memory_region>; 630}; 631 632&main_r5fss1_core1 { 633 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; 634 memory-region = <&main_r5fss1_core1_dma_memory_region>, 635 <&main_r5fss1_core1_memory_region>; 636}; 637 638&ecap0 { 639 status = "okay"; 640 /* PWM is available on Pin 1 of header J3 */ 641 pinctrl-names = "default"; 642 pinctrl-0 = <&main_ecap0_pins_default>; 643}; 644