1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/leds/common.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include "k3-am642.dtsi" 13 14#include "k3-serdes.h" 15 16/ { 17 compatible = "ti,am642-evm", "ti,am642"; 18 model = "Texas Instruments AM642 EVM"; 19 20 chosen { 21 stdout-path = &main_uart0; 22 }; 23 24 aliases { 25 serial0 = &mcu_uart0; 26 serial1 = &main_uart1; 27 serial2 = &main_uart0; 28 serial3 = &main_uart3; 29 i2c0 = &main_i2c0; 30 i2c1 = &main_i2c1; 31 mmc0 = &sdhci0; 32 mmc1 = &sdhci1; 33 ethernet0 = &cpsw_port1; 34 ethernet1 = &cpsw_port2; 35 }; 36 37 memory@80000000 { 38 device_type = "memory"; 39 /* 2G RAM */ 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 41 }; 42 43 reserved-memory { 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 48 secure_ddr: optee@9e800000 { 49 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 50 alignment = <0x1000>; 51 no-map; 52 }; 53 54 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa0000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa0100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa1000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa1100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa2000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa2100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 91 compatible = "shared-dma-pool"; 92 reg = <0x00 0xa3000000 0x00 0x100000>; 93 no-map; 94 }; 95 96 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 97 compatible = "shared-dma-pool"; 98 reg = <0x00 0xa3100000 0x00 0xf00000>; 99 no-map; 100 }; 101 102 rtos_ipc_memory_region: ipc-memories@a5000000 { 103 reg = <0x00 0xa5000000 0x00 0x00800000>; 104 alignment = <0x1000>; 105 no-map; 106 }; 107 }; 108 109 evm_12v0: regulator-0 { 110 /* main DC jack */ 111 compatible = "regulator-fixed"; 112 regulator-name = "evm_12v0"; 113 regulator-min-microvolt = <12000000>; 114 regulator-max-microvolt = <12000000>; 115 regulator-always-on; 116 regulator-boot-on; 117 }; 118 119 vsys_5v0: regulator-1 { 120 /* output of LM5140 */ 121 compatible = "regulator-fixed"; 122 regulator-name = "vsys_5v0"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 vin-supply = <&evm_12v0>; 126 regulator-always-on; 127 regulator-boot-on; 128 }; 129 130 vsys_3v3: regulator-2 { 131 /* output of LM5140 */ 132 compatible = "regulator-fixed"; 133 regulator-name = "vsys_3v3"; 134 regulator-min-microvolt = <3300000>; 135 regulator-max-microvolt = <3300000>; 136 vin-supply = <&evm_12v0>; 137 regulator-always-on; 138 regulator-boot-on; 139 }; 140 141 vdd_mmc1: regulator-3 { 142 /* TPS2051BD */ 143 compatible = "regulator-fixed"; 144 regulator-name = "vdd_mmc1"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 regulator-boot-on; 148 enable-active-high; 149 vin-supply = <&vsys_3v3>; 150 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 151 }; 152 153 vddb: regulator-4 { 154 compatible = "regulator-fixed"; 155 regulator-name = "vddb_3v3_display"; 156 regulator-min-microvolt = <3300000>; 157 regulator-max-microvolt = <3300000>; 158 vin-supply = <&vsys_3v3>; 159 regulator-always-on; 160 regulator-boot-on; 161 }; 162 163 vtt_supply: regulator-5 { 164 compatible = "regulator-fixed"; 165 regulator-name = "vtt"; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&ddr_vtt_pins_default>; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; 171 vin-supply = <&vsys_3v3>; 172 enable-active-high; 173 regulator-always-on; 174 regulator-boot-on; 175 }; 176 177 leds { 178 compatible = "gpio-leds"; 179 180 led-0 { 181 label = "am64-evm:red:heartbeat"; 182 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 183 linux,default-trigger = "heartbeat"; 184 function = LED_FUNCTION_HEARTBEAT; 185 default-state = "off"; 186 }; 187 }; 188 189 mdio_mux: mux-controller { 190 compatible = "gpio-mux"; 191 #mux-control-cells = <0>; 192 193 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 194 }; 195 196 mdio-mux-1 { 197 compatible = "mdio-mux-multiplexer"; 198 mux-controls = <&mdio_mux>; 199 mdio-parent-bus = <&cpsw3g_mdio>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 mdio@1 { 204 reg = <0x1>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 208 cpsw3g_phy3: ethernet-phy@3 { 209 reg = <3>; 210 }; 211 }; 212 }; 213 214 transceiver1: can-phy0 { 215 compatible = "ti,tcan1042"; 216 #phy-cells = <0>; 217 max-bitrate = <5000000>; 218 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>; 219 }; 220 221 transceiver2: can-phy1 { 222 compatible = "ti,tcan1042"; 223 #phy-cells = <0>; 224 max-bitrate = <5000000>; 225 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; 226 }; 227}; 228 229&main_pmx0 { 230 main_mmc1_pins_default: main-mmc1-default-pins { 231 pinctrl-single,pins = < 232 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 233 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 234 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 235 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 236 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 237 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 238 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 239 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 240 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 241 >; 242 }; 243 244 main_uart1_pins_default: main-uart1-default-pins { 245 pinctrl-single,pins = < 246 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ 247 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ 248 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ 249 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ 250 >; 251 }; 252 253 main_uart0_pins_default: main-uart0-default-pins { 254 pinctrl-single,pins = < 255 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 256 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 257 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 258 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 259 >; 260 }; 261 262 main_spi0_pins_default: main-spi0-default-pins { 263 pinctrl-single,pins = < 264 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 265 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 266 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 267 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 268 >; 269 }; 270 271 main_i2c0_pins_default: main-i2c0-default-pins { 272 pinctrl-single,pins = < 273 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ 274 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ 275 >; 276 }; 277 278 main_i2c1_pins_default: main-i2c1-default-pins { 279 pinctrl-single,pins = < 280 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 281 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 282 >; 283 }; 284 285 mdio1_pins_default: mdio1-default-pins { 286 pinctrl-single,pins = < 287 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 288 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 289 >; 290 }; 291 292 rgmii1_pins_default: rgmii1-default-pins { 293 pinctrl-single,pins = < 294 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 295 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 296 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 297 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 298 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 299 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 300 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 301 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 302 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 303 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 304 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 305 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 306 >; 307 }; 308 309 rgmii2_pins_default: rgmii2-default-pins { 310 pinctrl-single,pins = < 311 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 312 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 313 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 314 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 315 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 316 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 317 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 318 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 319 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 320 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 321 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 322 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 323 >; 324 }; 325 326 main_usb0_pins_default: main-usb0-default-pins { 327 pinctrl-single,pins = < 328 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 329 >; 330 }; 331 332 ospi0_pins_default: ospi0-default-pins { 333 pinctrl-single,pins = < 334 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 335 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 336 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 337 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 338 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 339 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 340 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 341 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 342 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 343 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 344 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 345 >; 346 }; 347 348 main_ecap0_pins_default: main-ecap0-default-pins { 349 pinctrl-single,pins = < 350 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 351 >; 352 }; 353 354 main_mcan0_pins_default: main-mcan0-default-pins { 355 pinctrl-single,pins = < 356 AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ 357 AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ 358 >; 359 }; 360 361 main_mcan1_pins_default: main-mcan1-default-pins { 362 pinctrl-single,pins = < 363 AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ 364 AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ 365 >; 366 }; 367 368 ddr_vtt_pins_default: ddr-vtt-default-pins { 369 pinctrl-single,pins = < 370 AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ 371 >; 372 }; 373}; 374 375&main_uart0 { 376 status = "okay"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&main_uart0_pins_default>; 379 current-speed = <115200>; 380}; 381 382/* main_uart1 is reserved for firmware usage */ 383&main_uart1 { 384 status = "reserved"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&main_uart1_pins_default>; 387}; 388 389&main_i2c0 { 390 status = "okay"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&main_i2c0_pins_default>; 393 clock-frequency = <400000>; 394 395 eeprom@50 { 396 /* AT24CM01 */ 397 compatible = "atmel,24c1024"; 398 reg = <0x50>; 399 }; 400}; 401 402&main_i2c1 { 403 status = "okay"; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&main_i2c1_pins_default>; 406 clock-frequency = <400000>; 407 408 exp1: gpio@22 { 409 compatible = "ti,tca6424"; 410 reg = <0x22>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 414 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 415 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 416 "MMC1_SD_EN", "FSI_FET_SEL", 417 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 418 "CPSW_FET_SEL", "CPSW_FET2_SEL", 419 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 420 "GPIO_OLED_RESETn", "VPP_LDO_EN", 421 "TEST_LED1", "TP92", "TP90", "TP88", 422 "TP87", "TP86", "TP89", "TP91"; 423 }; 424 425 /* osd9616p0899-10 */ 426 display@3c { 427 compatible = "solomon,ssd1306fb-i2c"; 428 reg = <0x3c>; 429 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 430 vbat-supply = <&vddb>; 431 solomon,height = <16>; 432 solomon,width = <96>; 433 solomon,com-seq; 434 solomon,com-invdir; 435 solomon,page-offset = <0>; 436 solomon,prechargep1 = <2>; 437 solomon,prechargep2 = <13>; 438 }; 439}; 440 441/* mcu_gpio0 is reserved for mcu firmware usage */ 442&mcu_gpio0 { 443 status = "reserved"; 444}; 445 446&main_spi0 { 447 status = "okay"; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&main_spi0_pins_default>; 450 ti,pindir-d0-out-d1-in; 451 eeprom@0 { 452 compatible = "microchip,93lc46b"; 453 reg = <0>; 454 spi-max-frequency = <1000000>; 455 spi-cs-high; 456 data-size = <16>; 457 }; 458}; 459 460&sdhci0 { 461 /* emmc */ 462 bus-width = <8>; 463 non-removable; 464 ti,driver-strength-ohm = <50>; 465 disable-wp; 466}; 467 468&sdhci1 { 469 /* SD/MMC */ 470 vmmc-supply = <&vdd_mmc1>; 471 pinctrl-names = "default"; 472 bus-width = <4>; 473 pinctrl-0 = <&main_mmc1_pins_default>; 474 ti,driver-strength-ohm = <50>; 475 disable-wp; 476}; 477 478&usbss0 { 479 ti,vbus-divider; 480 ti,usb2-only; 481}; 482 483&usb0 { 484 dr_mode = "otg"; 485 maximum-speed = "high-speed"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&main_usb0_pins_default>; 488}; 489 490&cpsw3g { 491 pinctrl-names = "default"; 492 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; 493}; 494 495&cpsw_port1 { 496 phy-mode = "rgmii-rxid"; 497 phy-handle = <&cpsw3g_phy0>; 498}; 499 500&cpsw_port2 { 501 phy-mode = "rgmii-rxid"; 502 phy-handle = <&cpsw3g_phy3>; 503}; 504 505&cpsw3g_mdio { 506 status = "okay"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&mdio1_pins_default>; 509 510 cpsw3g_phy0: ethernet-phy@0 { 511 reg = <0>; 512 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 513 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 514 }; 515}; 516 517&tscadc0 { 518 /* ADC is reserved for R5 usage */ 519 status = "reserved"; 520}; 521 522&ospi0 { 523 status = "okay"; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&ospi0_pins_default>; 526 527 flash@0 { 528 compatible = "jedec,spi-nor"; 529 reg = <0x0>; 530 spi-tx-bus-width = <8>; 531 spi-rx-bus-width = <8>; 532 spi-max-frequency = <25000000>; 533 cdns,tshsl-ns = <60>; 534 cdns,tsd2d-ns = <60>; 535 cdns,tchsh-ns = <60>; 536 cdns,tslch-ns = <60>; 537 cdns,read-delay = <4>; 538 539 partitions { 540 compatible = "fixed-partitions"; 541 #address-cells = <1>; 542 #size-cells = <1>; 543 544 partition@0 { 545 label = "ospi.tiboot3"; 546 reg = <0x0 0x100000>; 547 }; 548 549 partition@100000 { 550 label = "ospi.tispl"; 551 reg = <0x100000 0x200000>; 552 }; 553 554 partition@300000 { 555 label = "ospi.u-boot"; 556 reg = <0x300000 0x400000>; 557 }; 558 559 partition@700000 { 560 label = "ospi.env"; 561 reg = <0x700000 0x40000>; 562 }; 563 564 partition@740000 { 565 label = "ospi.env.backup"; 566 reg = <0x740000 0x40000>; 567 }; 568 569 partition@800000 { 570 label = "ospi.rootfs"; 571 reg = <0x800000 0x37c0000>; 572 }; 573 574 partition@3fc0000 { 575 label = "ospi.phypattern"; 576 reg = <0x3fc0000 0x40000>; 577 }; 578 }; 579 }; 580}; 581 582&mailbox0_cluster2 { 583 status = "okay"; 584 585 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 586 ti,mbox-rx = <0 0 2>; 587 ti,mbox-tx = <1 0 2>; 588 }; 589 590 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 591 ti,mbox-rx = <2 0 2>; 592 ti,mbox-tx = <3 0 2>; 593 }; 594}; 595 596&mailbox0_cluster4 { 597 status = "okay"; 598 599 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 600 ti,mbox-rx = <0 0 2>; 601 ti,mbox-tx = <1 0 2>; 602 }; 603 604 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 605 ti,mbox-rx = <2 0 2>; 606 ti,mbox-tx = <3 0 2>; 607 }; 608}; 609 610&mailbox0_cluster6 { 611 status = "okay"; 612 613 mbox_m4_0: mbox-m4-0 { 614 ti,mbox-rx = <0 0 2>; 615 ti,mbox-tx = <1 0 2>; 616 }; 617}; 618 619&main_r5fss0_core0 { 620 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; 621 memory-region = <&main_r5fss0_core0_dma_memory_region>, 622 <&main_r5fss0_core0_memory_region>; 623}; 624 625&main_r5fss0_core1 { 626 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; 627 memory-region = <&main_r5fss0_core1_dma_memory_region>, 628 <&main_r5fss0_core1_memory_region>; 629}; 630 631&main_r5fss1_core0 { 632 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; 633 memory-region = <&main_r5fss1_core0_dma_memory_region>, 634 <&main_r5fss1_core0_memory_region>; 635}; 636 637&main_r5fss1_core1 { 638 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; 639 memory-region = <&main_r5fss1_core1_dma_memory_region>, 640 <&main_r5fss1_core1_memory_region>; 641}; 642 643&serdes_ln_ctrl { 644 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 645}; 646 647&serdes0 { 648 serdes0_pcie_link: phy@0 { 649 reg = <0>; 650 cdns,num-lanes = <1>; 651 #phy-cells = <0>; 652 cdns,phy-type = <PHY_TYPE_PCIE>; 653 resets = <&serdes_wiz0 1>; 654 }; 655}; 656 657&pcie0_rc { 658 status = "okay"; 659 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 660 phys = <&serdes0_pcie_link>; 661 phy-names = "pcie-phy"; 662 num-lanes = <1>; 663}; 664 665&pcie0_ep { 666 phys = <&serdes0_pcie_link>; 667 phy-names = "pcie-phy"; 668 num-lanes = <1>; 669}; 670 671&ecap0 { 672 status = "okay"; 673 /* PWM is available on Pin 1 of header J12 */ 674 pinctrl-names = "default"; 675 pinctrl-0 = <&main_ecap0_pins_default>; 676}; 677 678&main_mcan0 { 679 status = "okay"; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&main_mcan0_pins_default>; 682 phys = <&transceiver1>; 683}; 684 685&main_mcan1 { 686 status = "okay"; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&main_mcan1_pins_default>; 689 phys = <&transceiver2>; 690}; 691